JPH10189778A - Semiconductor memory element and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory element, and a fabrication method thereof, in which coupling capacity is increased while avoiding abnormal patterning which occurs easily when HSG(hemispherical grain) polisilicon is employed in an EEPROM, for example. SOLUTION: A gate oxide 1 is deposited on a semiconductor substrate and a floating gate 2 is formed thereon. An oxide 9 is then deposited thereon and removed from a region for forming a control gate 5. Subsequently, it is annealed at 575±5 deg.C to form a hemispheric HSG polysilicon 3 and a spheric HSG polysilicon 3'. Thereafter, the oxide 9 is removed using an HF solution, or the like, such that the spheric HSG polysilicon 3' is removed but the hemispheric HSG polysilicon 3 is left. Furthermore, an insulation layer 4 is formed and a control gate 5 is formed of a polisilicon layer. Since etching residue of the control gate 5 is not left, abnormal patterning can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
More specifically, the present invention relates to a nonvolatile semiconductor memory element such as M and a method for manufacturing the same. More specifically, the HSG (Hemi Spherical Grain) is formed only in a control gate formation region by forming an HSG polysilicon (HSG polysilicon). The present invention relates to a semiconductor memory element in which an etching residue at the time of using polycrystalline silicon is avoided to increase a coupling capacity and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the miniaturization of non-volatile semiconductor storage elements such as EEPROMs has been advanced along with high integration, and the area in which a capacitance section can be formed has been reduced. Along with that, EEP
It is expected that the coupling capacitance between the control gate and the floating gate in the ROM also decreases, and the operating voltage at the time of charge writing and erasing to the floating gate is not scaled.

In order to increase the coupling capacitance between the floating gate and the control gate in the EEPROM, there are measures such as reducing the thickness of the insulating film and increasing the overlap area. There is a possibility that the degree of integration may be reduced.

On the other hand, a DRAM (DYNAMIC RANDOM ACCESS M)
HSG polysilicon has attracted attention as an example of a cell capacity increasing method in (EMORY). This method is called EEPRO
M is also effective, and the coupling capacitance between the floating gate and the control gate can be increased by using HSG polysilicon for the EEPROM. In other words, this method is a method of increasing the surface area by roughening the polysilicon surface, and increasing the CV of the polysilicon.
It can be easily realized by controlling the D temperature.

FIGS. 3A to 3C are views showing a manufacturing process of a memory cell portion of a semiconductor memory device according to the present invention, wherein FIG. 3A is a sectional view of a floating gate forming step, FIG. 3B is a sectional view of an insulating film forming step, and FIG. () Is a cross-sectional view of a control gate forming step, and (d) is a cross-sectional view after forming a memory cell.

First, in the step of FIG. 3A, a floating gate 2 made of amorphous silicon (amorphous silicon) is formed on a semiconductor substrate via a gate oxide film 1 by CVD. Next, the atmosphere around the semiconductor substrate is approximated to about 0.2 Tool, and annealing is performed at a temperature at which a transition from amorphous to polycrystalline is performed, for example, at about 600 to 800 ° C., so that the entire surface of the floating gate 2 is HSG.
Polysilicon 3 is formed.

In the step of FIG. 3B, after forming an insulating film 4 on the HSG polysilicon 3 of the floating gate 2 by thermal oxidation or the like, a polycrystalline silicon layer (not shown) to be a control gate 5 described later is formed. I do.

Thereafter, patterning is performed by a lithography process and an etching process to form a control gate 5 (see FIG. 1C). After the formation of the control gate 5, the etching residue 6 of the control gate remains at the step portion of the HSG polysilicon 3 and a pattern abnormality may occur.

Further, patterning is performed by the lithography step and the etching step using the control gate 5 as a mask to form the memory cell 7. here,
As described above, when the floating gate 2 is processed using the control gate 5 having the pattern abnormality as a mask, a floating gate etching residue 8 is formed around the memory cell 7.

That is, the HSG polysilicon 3 used as a DRAM cell capacity increasing method is replaced by EEPRO.
When the HSG polysilicon 3 is formed on the entire surface of the floating gate 2, the process of patterning the floating gate 2 using the control gate 5 as a mask is the mainstream in EEPROM. Is likely to occur at the stepped portion due to the etching residue 6 of the control gate. When the floating gate 2 is processed using the abnormal pattern as a mask, there is a problem that the floating gate pattern also becomes abnormal. The gist of the present invention is to propose a method of limiting the region where the HSG polysilicon 3 is formed to only the region where the control gate 5 is formed in order to avoid the occurrence of the pattern abnormality.

[0011]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems.
Provided are a semiconductor memory element and a method of manufacturing the same, in which a pattern abnormality that is likely to occur when HSG polysilicon is used for the OM is avoided and a coupling capacitance is increased.

[0012]

According to the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising the steps of: forming a first silicon layer by using amorphous silicon via a first insulating film formed on a semiconductor substrate; Forming an oxide film on the first silicon layer, removing an oxide film in a region where a second silicon layer described later is formed, and forming at least the first silicon layer. Crystallizing and roughening the upper surface of the semiconductor device, removing the oxide film, forming a second insulating film on the first silicon layer, and forming a second insulating film on the second insulating film by using polysilicon. 2
Forming a silicon layer (such as a control gate), and limiting the portion to be crystallized and roughened to the second silicon layer formation region.

Further, the semiconductor memory device of the present invention comprises: a semiconductor substrate; a first silicon layer (eg, a floating gate) formed of amorphous silicon via a first insulating film formed on the semiconductor substrate; It is composed of a second insulating film formed on one silicon layer and a second silicon layer (such as a control gate) formed on an oxide film. The upper surface of the region of the first silicon layer where the second silicon layer is formed is characterized by having a structure in which amorphous silicon is crystallized to be polysilicon to have a roughened surface.

Therefore, in the semiconductor memory device and the method of manufacturing the same according to the present invention, the location where the HSG polysilicon is formed is limited to only the formation region of the second silicon layer (control gate).
It is possible to avoid an etching residue which is likely to be generated when applying SG polysilicon, and to expand an operation margin of the EEPROM.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings.

First, the sectional structure of the semiconductor memory device of the present invention will be described with reference to FIG. FIG. 1 is a schematic sectional view showing a semiconductor memory device of the present invention. Note that portions common to those described in the related art are denoted by the same reference numerals.

A semiconductor memory device of the present invention as shown in FIG. 1 has a gate insulating film 1 as a first insulating film formed on a semiconductor substrate, and a first insulating film formed via the gate oxide film 1.
The memory cell of the present invention comprises a floating gate 2 as a silicon layer, an insulating film 4 as a second insulating film formed on the floating gate 2, and a control gate 5 as a second silicon layer formed on the insulating film 4. 17 is constituted. The upper surface of the region of the floating gate 2 where the control gate 5 is formed has a roughened structure by crystallizing amorphous silicon into polysilicon.

Next, a method for manufacturing a semiconductor memory device according to the present invention will be sequentially described for each process with reference to FIG. 2A and 2B are cross-sectional views of a process for forming a floating gate and an oxide film, FIG. 2B is a cross-sectional view of a process for forming an HSG polysilicon, and FIG. () Is a sectional view of an oxide film removing step, (d) is a sectional view of an insulating film forming step, and (e) is a sectional view after forming a memory cell.

First, in the step of FIG. 2A, after forming a gate oxide film 1 on a semiconductor substrate, a floating gate 2 made of amorphous silicon is formed by CVD.
Subsequently, after an oxide film 9 is formed by a CVD method or thermal oxidation, the oxide film 9 in a region where a control gate to be described later is formed is removed.

Next, in the step of FIG. 2B, after an amorphous silicon layer is deposited by a CVD method or the like,
The atmosphere around the semiconductor substrate is approximated to about 0.2 Tool, and annealing is performed at a temperature of about 600 to 800 ° C. At this time, the portion without the oxide film 9 is mixed with the amorphous silicon layer of the floating gate 2 to form a hemispherical HS.
G polysilicon 3 is formed, and spherical HSG polysilicon 3 ′ is formed on oxide film 9.

In the step (c), the oxide film 9 is removed with an HF solution or the like. At this time, the spherical HSG polysilicon 3 ′ formed on the oxide film 9 is removed by lift-off when removing the oxide film 9, but the hemispherical HSG polysilicon 3 formed in the region without the oxide film 9 is floating. Since it is in direct contact with the gate 2, it remains without being removed.

In the step (d), an insulating film 4 is formed on the HSG polysilicon 3 of the floating gate 2 by thermal oxidation or the like.

Referring to FIG. 2E, after forming a polycrystalline silicon layer (not shown) serving as a control gate, patterning is performed by a lithography step and an etching step to form a control gate 5. At this time, there is no etching residue of the control gate 5, so that no pattern abnormality occurs.

Further, patterning is performed by a lithography step and an etching step using the control gate as a mask to form a memory cell 17 of the present invention. Here, the lower surface of the control gate 5 formed in close contact with the HSG polysilicon 3 is a layer having a hemispherical shape like the insulating film 4 because the insulating film 4 is a layer having a hemispherical shape. And its surface area is larger than that of a flat surface.

According to the method of manufacturing a semiconductor memory device of the present invention, the region where the HSG polysilicon 3 is formed is limited to only the region where the control gate 5 is formed by the oxide film 9, so that the HSG polysilicon 3 is formed in the EEPROM. It is possible to avoid an etching residue which is likely to be generated when applied, and to increase a coupling capacitance between a floating gate and a control gate in a semiconductor memory element.

The present invention relates to the EE illustrated in the above embodiment.
It goes without saying that the present invention can be appropriately applied not only to the floating gate of the PROM but also to other semiconductor storage elements such as a flash memory.

[0027]

As described above, according to the semiconductor memory device and the method of manufacturing the same of the present invention, the region where the HSG polysilicon is formed is limited to only the region where the second silicon layer (such as a control gate) is formed. As a result, the coupling capacitance of the semiconductor memory element can be increased without lowering the degree of integration. Further, for example, an etching residue which is likely to be generated when HSG polysilicon is applied to an EEPROM can be avoided, and the operation margin of the EEPROM can be expanded.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a semiconductor memory element of the present invention.

FIGS. 2A and 2B are manufacturing process diagrams of a memory cell portion of a semiconductor memory element of the present invention, wherein FIG. 2A is a cross-sectional view of a floating gate and oxide film forming step, FIG. 3C is a sectional view of an oxide film removing step, FIG. 4D is a sectional view of an insulating film forming step, and FIG. 4E is a sectional view after a memory cell is formed.

3A and 3B are manufacturing process diagrams of a memory cell portion of a semiconductor memory element according to the present invention, wherein FIG. 3A is a cross-sectional view of a floating gate forming step, FIG. 3B is a cross-sectional view of an insulating film forming step, and FIG. Sectional view of a control gate forming step,
(D) is a cross-sectional view after the memory cell is formed.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Gate oxide film, 2 ... Floating gate, 3 ... H
SG polysilicon, 4 insulating film, 5 control gate, 6 etching residue of control gate, 7 memory cell, 8 etching residue of floating gate, 9 oxide film, 17 memory cell of the present invention

Claims (3)

[Claims] A step of forming a first silicon layer by amorphous silicon via a first insulating film formed on a semiconductor substrate; and forming an oxide film on the first silicon layer. Removing the oxide film in a region where the second silicon layer is formed; crystallizing and roughening at least an upper surface of the first silicon layer; removing the oxide film; A step of forming a second insulating film on the first silicon layer; and a step of forming a second silicon layer of polysilicon on the second insulating film by using polysilicon. Method. 2. A semiconductor substrate, a first silicon layer formed of amorphous silicon via a first insulating film formed on the semiconductor substrate, and a first silicon layer formed on the first silicon layer. And a second silicon layer formed on the oxide film. An upper surface of a region of the first silicon layer where the second silicon layer is formed is formed by crystallizing amorphous silicon. A semiconductor memory element having a structure roughened by using polysilicon. 3. The semiconductor memory device according to claim 2, wherein said semiconductor memory device is an EEPROM.