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JPH10189637A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH10189637A
JPH10189637A JP8344755A JP34475596A JPH10189637A JP H10189637 A JPH10189637 A JP H10189637A JP 8344755 A JP8344755 A JP 8344755A JP 34475596 A JP34475596 A JP 34475596A JP H10189637 A JPH10189637 A JP H10189637A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor device
semiconductor element
holes
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8344755A
Other languages
Japanese (ja)
Inventor
Hiroyuki Hozoji
裕之 宝蔵寺
Shigeharu Tsunoda
重晴 角田
Junichi Saeki
準一 佐伯
Akira Haruta
亮 春田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8344755A priority Critical patent/JPH10189637A/en
Publication of JPH10189637A publication Critical patent/JPH10189637A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
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    • H01L2224/05553—Shape in top view being rectangular
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

(57)【要約】 【課題】小型・多ピン化が進んで基板上の端子間隔が狭
くなったとしても、半導体素子からボール搭載部までの
配線を基板に形成するのを可能にしたＢＧＡ等の半導体
装置を提供することにある。 【解決手段】表面から裏面まで導体でつながった多数の
スルーホール６を外形の内側にこの外形辺に沿って所望
の間隔で配設し、且つ前記表面において各々が前記スル
ーホール６の各々に接続されて該スルーホールの近傍の
範囲で互いに接触しないように伸びた多数の電極片部８
を並設形成した基板２を設け、該基板の表面における前
記多数の電極片部の内側に半導体素子１を搭載し、該半
導体素子の外形辺に沿って配設された多数のボンディン
グパッド５の各々と前記基板の表面に並設形成された多
数の電極片部８の各々との間においてボンディングワイ
ヤ４により接続を行い、少なくとも前記半導体素子及び
前記基板の表面を前記ボンディングワイヤが埋設される
ように樹脂３０により封止した半導体装置である。 (57) [Problem] A BGA or the like which enables a wiring from a semiconductor element to a ball mounting portion to be formed on a substrate even if the spacing between terminals on the substrate is reduced due to progress in miniaturization and increase in the number of pins. Another object of the present invention is to provide a semiconductor device. A plurality of through-holes (6) connected by conductors from the front surface to the back surface are arranged inside the outer shape at a desired interval along the outer side, and each is connected to each of the through-holes (6) on the front surface. And a large number of electrode pieces 8 extended so as not to contact each other in a range near the through hole.
Are provided in parallel with each other, the semiconductor element 1 is mounted inside the large number of electrode pieces on the surface of the substrate, and a large number of bonding pads 5 are arranged along the outer side of the semiconductor element. A connection is made between each of the plurality of electrode pieces 8 formed side by side on the surface of the substrate by a bonding wire 4 so that at least the semiconductor element and the surface of the substrate are embedded with the bonding wire. Is a semiconductor device sealed with a resin 30.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、端子間隔の狭いＢ
ＧＡ（Ball Grid Array）等の半導体装置、特に基板上
に半導体素子を搭載し、ボンディングワイヤにより半導
体素子と基板上の電極の接続を行う方式の半導体装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a semiconductor device such as a GA (Ball Grid Array) or the like, and particularly to a semiconductor device in which a semiconductor element is mounted on a substrate and a semiconductor element is connected to an electrode on the substrate by a bonding wire.

【０００２】[0002]

【従来の技術】各種電子機器は高機能化あるいは小型化
の傾向にあり、これに搭載する半導体装置は、電子機器
の実装密度を向上させるため、小型・薄型化の傾向にあ
る。さらに半導体素子一つ当たりで処理する情報量も増
大する傾向にあり、半導体装置当たりの入出力用端子数
も増大する傾向にある。一般に小型・多ピンの半導体装
置としてパッケージの周囲にガルウイング状に成形した
端子を配列したＱＦＰ（Quad Flat Package）がある
が、入出力端子数が増加すると半導体装置の外形寸法を
大きくするか、あるいは端子間隔を狭くする必要が生じ
る。半導体装置の外形寸法の大型化は電子機器への実装
密度を低下させるため好ましくは無い。また、端子間隔
を狭くすると、電子機器の回路基板上に半導体装置を実
装する上で従来より高度な実装技術が必要となり、簡単
に対応することは困難である。そこで、端子をパッケー
ジの外周に配列するのではなくパッケージ表面あるいは
底面にピン状の端子を配列したＰＧＡ（Pin Grid Arra
y）やボール状の半田を配列したＢＧＡ（Ball Grid Arr
ay）が考案された。これらの半導体装置は端子をパッケ
ージの周辺に一次元に配列するのではなく、パッケージ
の表面あるいは底面に二次元的に配列するため同じ端子
数であっても端子間隔が広く、回路基板上への実装が容
易になる。特に、近年、回路基板上への実装密度向上を
目的として米国特許第５，２１６，２７８号明細書ある
いは米国特許第５，１４８，２６５号明細書に記載のよ
うな表面実装型のＢＧＡが主流になってきている。2. Description of the Related Art Various electronic devices tend to have higher functions or smaller sizes, and semiconductor devices mounted on them tend to be smaller and thinner in order to increase the mounting density of the electronic devices. Furthermore, the amount of information processed per semiconductor element tends to increase, and the number of input / output terminals per semiconductor device also tends to increase. In general, there is a QFP (Quad Flat Package) in which terminals formed in a gull wing shape are arranged around a package as a small and multi-pin semiconductor device. However, when the number of input / output terminals increases, the external dimensions of the semiconductor device must be increased, or It becomes necessary to reduce the terminal interval. Increasing the external dimensions of the semiconductor device is not preferable because it reduces the mounting density in electronic devices. Also, when the terminal interval is reduced, a higher mounting technology is required to mount the semiconductor device on the circuit board of the electronic device than before, and it is difficult to easily cope with the problem. Therefore, PGA (Pin Grid Arra) in which pins are arranged on the surface or bottom of the package instead of being arranged on the outer periphery of the package.
y) and BGA (Ball Grid Arr) with ball-shaped solder
ay) was devised. In these semiconductor devices, terminals are not arranged one-dimensionally around the package, but are arranged two-dimensionally on the top or bottom surface of the package. Easy mounting. Particularly, in recent years, surface mount BGAs such as those described in US Pat. No. 5,216,278 or US Pat. No. 5,148,265 have become mainstream for the purpose of improving the mounting density on a circuit board. It is becoming.

【０００３】上記米国特許第５，２１６，２７８号明細
書に記載の半導体装置は、配線を施した基板上に半導体
素子を搭載し、半導体素子上のボンディングパッドと基
板上の電極部分とはボンディングワイヤによって接続さ
れ、さらに基板上の配線を介してスルーホールへと導か
れ、回路基板との接続を行うための半田ボール搭載電極
に接続され、半導体素子を樹脂で封止した構造となって
いる。また、米国特許第５，１４８，２６５号明細書に
記載の半導体装置は配線を施した基板上に弾性体を介し
て半導体素子を搭載し、半導体素子上のボンディングパ
ッドと基板上の電極部分とはボンディングワイヤによっ
て接続され、さらに基板上の配線を介して回路基板との
接続を行うための半田ボール搭載電極に接続される構造
となっている。また従来技術としては、特開平６−１１
２３５４号公報が知られている。In the semiconductor device described in the above-mentioned US Pat. No. 5,216,278, a semiconductor element is mounted on a wiring-provided substrate, and bonding pads on the semiconductor element are bonded to electrode portions on the substrate. It is connected by wires, further led to through holes via wiring on the board, connected to solder ball mounting electrodes for connection with the circuit board, and has a semiconductor element sealed with resin . Further, in the semiconductor device described in US Pat. No. 5,148,265, a semiconductor element is mounted on an interconnected substrate via an elastic body, and a bonding pad on the semiconductor element and an electrode portion on the substrate are connected to each other. Are connected by bonding wires and further connected to solder ball mounting electrodes for connection to a circuit board via wiring on the board. Further, as a prior art, Japanese Patent Laid-Open Publication No.
No. 2354 is known.

【０００４】[0004]

【発明が解決しようとする課題】上記従来技術では、半
導体素子から回路基板との接続を行うための半田ボール
搭載電極までの接続は何れも基板上の配線を介して行わ
れた。半導体装置の小型・多ピン化が進むと基板上の端
子間隔が狭くなり、半導体素子からボール搭載部までの
配線を基板に形成するのが困難になってくるという課題
を有していた。In the above-mentioned prior art, the connection from the semiconductor element to the solder ball mounting electrode for connection with the circuit board is made via wiring on the board. As the size and the number of pins of the semiconductor device increase, the distance between terminals on the substrate becomes narrower, and it is difficult to form wiring from the semiconductor element to the ball mounting portion on the substrate.

【０００５】本発明の目的は、上記従来技術の課題を解
決すべく、小型・多ピン化が進んで基板上の端子間隔が
狭くなったとしても、半導体素子からボール搭載部まで
の配線を基板に形成するのを可能にしたＢＧＡ等の半導
体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art by providing a wiring from a semiconductor element to a ball mounting portion even if a terminal spacing on a substrate is reduced due to progress in miniaturization and multi-pin. An object of the present invention is to provide a semiconductor device such as a BGA which can be formed in a semiconductor device.

【０００６】[0006]

【課題を解決するための手段】上記目的を達成するため
に、本発明は、基板に半導体素子を搭載し、ボンディン
グワイヤにより素子と基板の接続を行い、半導体素子及
び基板上面を樹脂により封止する方式において、基板上
のワイヤボンディングを基板に設けたスルーホール近
傍、スルーホール上、あるいは半導体装置と外部基板と
接続する電極の裏面に行った構造の半導体装置である。
また本発明は、表面から裏面まで導体でつながった多数
のスルーホールを外形の内側にこの外形辺に沿って所望
の間隔で配設し、且つ前記表面において各々が前記スル
ーホールの各々に接続されて該スルーホールの近傍の範
囲で互いに接触しないように伸びた多数の電極片部を並
設形成した基板を設け、該基板の表面における前記多数
の電極片部の内側に半導体素子を搭載し、該半導体素子
の外形辺に沿って配設された多数のボンディングパッド
の各々と前記基板の表面に並設形成された多数の電極片
部の各々との間においてボンディングワイヤにより接続
を行い、少なくとも前記半導体素子及び前記基板の表面
を前記ボンディングワイヤが埋設されるように樹脂によ
り封止したことを特徴とする半導体装置である。According to the present invention, there is provided a semiconductor device having a semiconductor element mounted on a substrate, connecting the element to the substrate by bonding wires, and sealing the semiconductor element and the upper surface of the substrate with a resin. The semiconductor device has a structure in which wire bonding on the substrate is performed in the vicinity of a through hole provided on the substrate, on the through hole, or on the back surface of an electrode connecting the semiconductor device to an external substrate.
The present invention also provides a large number of through-holes connected by conductors from the front surface to the back surface inside the outer shape at desired intervals along the outer side, and at the front surface each is connected to each of the through-holes. A substrate is formed in which a number of electrode pieces extending in parallel to each other in a range near the through hole are provided, and a semiconductor element is mounted on the surface of the substrate inside the plurality of electrode pieces, A connection is made by a bonding wire between each of a large number of bonding pads disposed along the outer side of the semiconductor element and each of a large number of electrode pieces formed in parallel on the surface of the substrate, and A semiconductor device, wherein surfaces of a semiconductor element and the substrate are sealed with a resin so that the bonding wires are embedded therein.

【０００７】また本発明は、前記半導体装置において、
前記各電極辺部の端の中心と各スルーホールの中心との
間の長さＬを前記スルーホールのピッチＰに対してＰ／
√２以下とすることを特徴とする。また本発明は、前記
半導体装置において、前記スルーホールのピッチが０．
８ｍｍ以下とすることを特徴とする。また本発明は、前
記半導体装置において、前記各電極片部の伸びた方向
が、前記半導体素子が搭載される内側に向かうことを特
徴とする。また本発明は、前記半導体装置において、前
記各電極片部の伸びた方向が、前記半導体素子が搭載さ
れる内側で、且つ前記半導体素子の２つの対称線に対し
てほぼ対称に向かうことを特徴とする。また本発明は、
前記半導体装置において、前記各電極片部の伸びた方向
が、前記半導体素子上に配設された各ボンディングパッ
ドに向かうことを特徴とする。また本発明は、前記半導
体装置において、前記各電極片部の伸びた方向が、所望
の方向に向かうことを特徴とする。また本発明は、表面
から裏面まで導体でつながった多数のスルーホールを外
形の内側にこの外形辺に沿って所望の間隔で配設し、且
つ前記表面において各々が前記スルーホールの各々に同
心状に接続された多数の電極部を並設形成した基板を設
け、該基板の表面における前記多数の電極部の内側に半
導体素子を搭載し、該半導体素子の外形辺に沿って配設
された多数のボンディングパッドの各々と前記基板の表
面に並設形成された多数の電極部の各々との間において
ボンディングワイヤにより接続を行い、少なくとも前記
半導体素子及び前記基板の表面を前記ボンディングワイ
ヤが埋設されるように樹脂により封止したことを特徴と
する半導体装置である。Further, the present invention provides the semiconductor device,
The length L between the center of the edge of each electrode side and the center of each through hole is defined as P / P with respect to the pitch P of the through holes.
√2 or less. Further, according to the present invention, in the semiconductor device, the pitch of the through holes is set to 0.1.
It is characterized by being 8 mm or less. Further, the invention is characterized in that, in the semiconductor device, the direction in which each of the electrode pieces extends extends toward the inside on which the semiconductor element is mounted. The present invention is also characterized in that, in the semiconductor device, the direction in which each of the electrode pieces extends is substantially symmetric with respect to two symmetry lines of the semiconductor element inside the semiconductor element is mounted. And The present invention also provides
In the semiconductor device, the direction in which each of the electrode pieces extends extends toward each of the bonding pads disposed on the semiconductor element. Further, according to the present invention, in the semiconductor device, the direction in which each of the electrode pieces extends extends in a desired direction. Also, the present invention provides a large number of through holes connected by conductors from the front surface to the back surface inside the outer shape at a desired interval along the outer side, and on the surface, each is concentric with each of the through holes. A plurality of electrode portions connected in parallel to each other are provided, a semiconductor element is mounted inside the plurality of electrode portions on the surface of the substrate, and a number of the plurality of electrode portions are arranged along the outer side of the semiconductor element. Are connected by bonding wires between each of the bonding pads and a plurality of electrode portions formed in parallel on the surface of the substrate, and the bonding wires are buried at least in the surfaces of the semiconductor element and the substrate. A semiconductor device characterized by being sealed with a resin as described above.

【０００８】また本発明は、多数の穴を外形の内側にこ
の外形辺に沿って所望の間隔で配設し、且つ裏面におい
て各々が前記各穴に対応するように多数の電極部を並設
形成した基板を設け、該基板の表面における前記多数の
穴の内側に半導体素子を搭載し、該半導体素子の外形辺
に沿って配設された多数のボンディングパッドの各々と
前記基板の裏面に並設形成された多数の電極部の裏面の
各々との間において前記各穴を通してボンディングワイ
ヤにより接続を行い、少なくとも前記半導体素子及び前
記基板の表面を前記ボンディングワイヤが埋設されるよ
うに樹脂により封止したことを特徴とする半導体装置で
ある。また本発明は、前記半導体装置において、前記基
板を絶縁フィルムを基材として形成したことを特徴とす
る。また本発明は、前記半導体装置において、前記ボン
ディングワイヤにワイヤ表面を絶縁性の樹脂で被覆した
ボンディングワイヤを用いることを特徴とする。また本
発明は、前記半導体装置において、前記基板の裏面に、
各々が前記各導体に接続された多数のパッドを並設し、
該多数のパッドの内近接したものの同士の一方を内側ま
たは外側に配線を引き出して回路基板との接続端子（接
合材）を形成することを特徴とする。また本発明は、前
記半導体装置において、前記基板における表面の最外周
部に、封止する液状の樹脂が流出するのを防止するため
のダムを設けたことを特徴とする。Further, according to the present invention, a large number of holes are provided inside the external shape at desired intervals along the external side, and a large number of electrode portions are arranged in parallel on the rear surface so as to correspond to the respective holes. A formed substrate is provided, a semiconductor element is mounted inside the plurality of holes on the front surface of the substrate, and a plurality of bonding pads arranged along the outer side of the semiconductor element are arranged in parallel with the back surface of the substrate. A connection is made between each of the formed back surfaces of the plurality of electrode portions with a bonding wire through each of the holes, and at least the surfaces of the semiconductor element and the substrate are sealed with a resin so that the bonding wires are embedded. A semiconductor device characterized by the following. Further, the invention is characterized in that in the semiconductor device, the substrate is formed using an insulating film as a base material. Further, the present invention is characterized in that in the semiconductor device, a bonding wire whose surface is covered with an insulating resin is used for the bonding wire. Further, according to the present invention, in the semiconductor device, on a back surface of the substrate,
A number of pads, each connected to the respective conductor, juxtaposed,
The method is characterized in that a wiring is drawn out inside or outside of one of the plurality of pads which are close to each other to form a connection terminal (joining material) with a circuit board. Further, the present invention is characterized in that in the semiconductor device, a dam for preventing a liquid resin to be sealed from flowing out is provided at an outermost peripheral portion of a surface of the substrate.

【０００９】以上説明したように、前記構成により、半
導体素子を搭載する基板上においてピッチが０．８ｍｍ
以下と狭い電極部（パッド部）と電極部（パッド部）と
の間に配線を引き回すことなく、半導体素子上のボンデ
ィングパッドと回路基板（プリント基板）に搭載・接続
するための裏面に形成されるはんだボール等の端子との
間の電気的な導体接続を容易に実現したＢＧＡ等の半導
体装置を得ることができる。As described above, according to the above configuration, the pitch is 0.8 mm on the substrate on which the semiconductor element is mounted.
It is formed on the bonding pad on the semiconductor element and the back surface for mounting and connecting to the circuit board (printed board) without routing the wiring between the narrow electrode part (pad part) and the electrode part (pad part) A semiconductor device such as a BGA that easily realizes electrical conductor connection with a terminal such as a solder ball can be obtained.

【００１０】[0010]

【発明の実施の形態】本発明の実施の形態について、図
を用いて説明する。図１は、本発明に係る半導体装置の
一実施の形態を示す樹脂で封止していない状態の上面概
略図である。本発明に係るＢＧＡ等の半導体装置は、半
導体素子１を基板２の上に導電ペーストからなる接着剤
あるいははんだ等（何れも図示せず）により固定し、半
導体素子１上に外形辺に沿って配設形成された多数のボ
ンディングパッド５の各々と基板２上に外形の内側にこ
の外形辺に沿って例えば２列に０．８ｍｍ以下のピッチ
で配設された多数のボンディングワイヤ接続部（電極
部）３の各々とをボンディングワイヤ４により電気的に
接続し、上記半導体素子１の上面およびボンディングワ
イヤ４の部分および基板２の上面が樹脂封止されて構成
される。そして、本発明に係るＢＧＡ等の半導体装置
は、小型・多ピン化が図られたものであり、そのためボ
ンディングワイヤ接続部（電極部）３のピッチが０．８
ｍｍ以下と狭く構成されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention, which is not sealed with a resin. In a semiconductor device such as a BGA according to the present invention, a semiconductor element 1 is fixed on a substrate 2 with an adhesive made of a conductive paste or solder or the like (neither is shown). A large number of bonding wire connections (electrodes) arranged on each of the large number of bonding pads 5 and the substrate 2 on the inside of the external shape along the external side at a pitch of, for example, 0.8 mm or less in two rows. 3) are electrically connected to each other by a bonding wire 4, and the upper surface of the semiconductor element 1, the portion of the bonding wire 4 and the upper surface of the substrate 2 are sealed with a resin. The semiconductor device such as a BGA according to the present invention has a small size and a large number of pins. Therefore, the pitch of the bonding wire connection portion (electrode portion) 3 is 0.8.
mm or less.

【００１１】図１には、上記多数の電極部３を、基板２
の半導体素子搭載面２０上に半導体素子１の周囲に外形
に沿って０．８ｍｍ以下の等ピッチで２列に配置した場
合の実施の形態を示す。上記基板２としては、ガラスク
ロス等の無機物からなる繊維あるいはケブラー等の有機
物からなる繊維に、エポキシ樹脂、フェノール樹脂、ポ
リイミド樹脂等の内の一種類あるいは二種類以上の熱硬
化性樹脂を含浸・硬化させた基材に対してスルーホール
も含めて銅等の導体による配線を形成させたものや、ア
ルミナ、ムライト、窒化アルミ等のセラミック基材に対
してスルーホールも含めて銅等の導体による配線を形成
させたものや、ポリイミド等の絶縁テーブの基材に対し
て銅等の導体による配線を形成させたものを用いること
ができる。特に基板２として、安価なポリイミド等の絶
縁テーブの基材を用いることによって、半導体装置とし
て原価低減をはかることができる。FIG. 1 shows that the large number of electrode portions 3 are
An embodiment in which two rows are arranged at equal pitches of 0.8 mm or less along the outer shape around the semiconductor element 1 on the semiconductor element mounting surface 20 of FIG. As the substrate 2, an inorganic fiber such as a glass cloth or an organic fiber such as Kevlar is impregnated with one or two or more thermosetting resins such as an epoxy resin, a phenol resin, and a polyimide resin. Wiring formed by conductors such as copper including through holes on hardened base materials, and conductors such as copper including through holes on ceramic base materials such as alumina, mullite, and aluminum nitride It is possible to use one having wiring formed thereon or one having wiring formed of a conductor such as copper on a base of an insulating tape such as polyimide. In particular, by using an insulative tape base such as polyimide as the substrate 2, the cost of the semiconductor device can be reduced.

【００１２】図２は、基板２の半導体素子搭載面２０上
に半導体素子１の周囲に多数の電極部３を等ピッチで２
列に配置し、半導体素子１上の各ボンディングパッド５
と基板２上に設けた各電極部３との間をボンディングワ
イヤ４によって接続した実施の形態を示したものであ
る。図２(ａ)は、各スルーホール６上の電極部７にボン
ディングワイヤ４の一端を接続した第１の実施の形態を
示す斜視図である。図２(ｂ)は各スルーホール上ではな
くスルーホールから隣接した範囲内に伸びて形成された
電極片部８にボンディングワイヤ４の一端を接続した第
２の実施の形態を示す斜視図である。スルーホール６
は、本半導体装置を搭載するプリント配線板（図示せ
ず）との接続を行う端子部分（ランド部分やはんだボー
ル等の接合材も含む）１８と半導体素子搭載面２０との
間を導体で接続するものであり、上記電極部３に対応さ
せて多数２列に並設される。各ボンディングワイヤ４と
基板上の各電極部３との間の接続は、前記図２(ａ)、
(ｂ)いずれの方法も可能であるが、各ボンディングワイ
ヤ４を接続する各電極部３の構造により異なることにな
る。例えば、スルーホール６の内部が全て銅等のボンデ
ィング温度より融点の高い金属２１で充填された構造で
あれば、図２（ａ）に示すようにスルーホール６上の電
極部７へのボンディングワイヤ４の接続が可能である。
しかし、図２（ｂ）に示すようにスルーホール６の部分
が、プリント配線板（回路基板）との接続を行うために
裏面に形成される端子部分１８と半導体素子搭載面（表
面）２０との間を銅めっき等で形成した銅等の導体膜２
２内に有機物あるいは融点がボンディング温度より低い
半田等２３で充填される構造の場合には、基板２の半導
体素子搭載面（表面）においてスルーホール６から隣接
した範囲内（Ｌ≦Ｐ／√２）で僅か伸びて、しかも上記
導体膜２２に接続された電極片部８を設け、該電極片部
８にボンディングワイヤ４による接続を行った方が接続
部の信頼性の点で有利である。電極片部８の形成の方法
としては、めっきによって所望の形状にＣｕの薄膜パタ
ーンを形成し、その上にＮｉ等をめっきによって形成
し、更にＡｕ，Ａｇ等をめっきによって形成する方法が
ある。なお、Ｃｕの薄膜パターン上に直接Ａｕ，Ａｇ等
をめっきによって形成してもよい。また電極片部８の形
成の方法としては、基板２の基材上にＣｕはくを接着
し、エッチング等でパターンニングすることによって形
成し、その表面にＮｉ等を介して、または直接Ａｕ，Ａ
ｇ等をめっきによって形成する方法がある。FIG. 2 shows that a large number of electrode portions 3 are formed on the semiconductor element mounting surface 20 of the substrate 2 around the semiconductor element 1 at equal pitches.
Each bonding pad 5 on the semiconductor element 1 is arranged in a row.
FIG. 1 shows an embodiment in which a bonding wire 4 is connected between a substrate and each electrode portion 3 provided on a substrate 2. FIG. 2A is a perspective view showing a first embodiment in which one end of a bonding wire 4 is connected to an electrode portion 7 on each through hole 6. FIG. 2B is a perspective view showing a second embodiment in which one end of the bonding wire 4 is connected to an electrode piece 8 formed not on each through hole but in an area adjacent to the through hole. . Through hole 6
Is a connection between a terminal portion (including a bonding material such as a land portion and a solder ball) 18 for connection with a printed wiring board (not shown) on which the present semiconductor device is mounted and a semiconductor element mounting surface 20 by a conductor. Many are arranged in parallel in two rows corresponding to the electrode portions 3. The connection between each bonding wire 4 and each electrode portion 3 on the substrate is as shown in FIG.
(b) Either method is possible, but it differs depending on the structure of each electrode portion 3 connecting each bonding wire 4. For example, if the inside of the through hole 6 is filled with a metal 21 having a melting point higher than the bonding temperature such as copper, a bonding wire to the electrode portion 7 on the through hole 6 as shown in FIG. 4 connections are possible.
However, as shown in FIG. 2B, the portion of the through hole 6 has a terminal portion 18 formed on the back surface and a semiconductor element mounting surface (front surface) 20 for connection with a printed wiring board (circuit board). Conductor film 2 made of copper or the like formed by copper plating or the like
2 is filled with an organic substance or a solder 23 whose melting point is lower than the bonding temperature, in a region adjacent to the through hole 6 on the semiconductor element mounting surface (surface) of the substrate 2 (L ≦ P / √2). ), It is more advantageous to provide the electrode piece 8 connected to the conductor film 22 and to connect the electrode piece 8 with the bonding wire 4 from the viewpoint of the reliability of the connection. As a method for forming the electrode piece 8, there is a method in which a Cu thin film pattern is formed in a desired shape by plating, Ni or the like is formed thereon by plating, and Au, Ag, or the like is formed by plating. Note that Au, Ag, or the like may be directly formed on the Cu thin film pattern by plating. As a method of forming the electrode piece 8, a Cu foil is adhered on the base material of the substrate 2 and formed by patterning by etching or the like, and the surface of the electrode piece 8 is made of Au, A
There is a method of forming g or the like by plating.

【００１３】図３は、図２（ｂ）に示す実施の形態にお
けるスルーホール６から隣接した範囲で伸びてスルーホ
ール内の導体と接続された電極片部８の形状とスルーホ
ール接続部のランド部分９の径との関係を示したもので
ある。スルーホール中心（ランド部分９の中心）からス
ルーホールに隣接した範囲内で僅か伸ばされた電極片部
８の端までの長さ（距離）Ｌは、ランド部分９も含め、
隣り合った電極同士が接触しない範囲で使用可能であ
る。即ちこの長さＬは次に示す（数１）式の関係を満足
させることが必要である。 Ｌ≦Ｐ／√２ （数１） 但し、Ｐはランド部分９（電極部３）のピッチを示す。
またこのピッチＰは、０．８ｍｍ以下の狭いものであ
る。即ち、ピッチＰが０．８ｍｍの場合にはＬは約０．
５７ｍｍ以下となり、ピッチＰが０．６ｍｍの場合には
Ｌは約０．４３ｍｍ以下となり、ピッチＰが０．５ｍｍ
の場合にはＬは約０．３６ｍｍ以下となる。図５（ｃ）
に矢印２６、２７で示す電極片部８については、Ｌは、
スルーホール中心からスルーホールに隣接した範囲内で
僅か伸ばされた電極片部８の端までの距離が対応するこ
とになる。この距離Ｌは、途中の曲がりには関係しない
ものとする。FIG. 3 shows the shape of the electrode piece 8 extending in a range adjacent to the through hole 6 in the embodiment shown in FIG. 2B and connected to the conductor in the through hole, and the land of the through hole connecting portion. This shows the relationship with the diameter of the portion 9. The length (distance) L from the center of the through hole (the center of the land portion 9) to the end of the electrode piece portion 8 slightly extended in a range adjacent to the through hole includes the land portion 9,
It can be used as long as adjacent electrodes do not contact each other. That is, it is necessary that the length L satisfies the relationship of the following equation (1). L ≦ P / √2 (Equation 1) Here, P indicates the pitch of the land portion 9 (the electrode portion 3).
The pitch P is as narrow as 0.8 mm or less. That is, when the pitch P is 0.8 mm, L is about 0.5.
When the pitch P is 0.6 mm, L becomes about 0.43 mm or less, and the pitch P becomes 0.5 mm.
In this case, L is about 0.36 mm or less. FIG. 5 (c)
L of the electrode piece 8 indicated by arrows 26 and 27 in FIG.
The distance from the center of the through-hole to the end of the electrode piece 8 slightly extended in the range adjacent to the through-hole corresponds. It is assumed that the distance L does not relate to a turn in the middle.

【００１４】図４は、図２（ｂ）に示す実施の形態にお
いてスルーホール６に隣接した範囲内で僅か伸びて接続
した電極片部８を各種に配列した実施の形態を示したも
のである。図４(ａ)は電極片部８を全て同じ角度で同一
方向に配列して設けた実施の形態を示すものであり、図
４(ｂ)は基板上に配列された電極片部８を複数のブロッ
クに分け（図４(ｂ)では４ブロックに分けている）、ブ
ロック内で電極片部８の角度、方向を揃えた実施の形態
を示すものであり、図４(ｃ)は各電極片部８毎に角度と
方向を変化させた実施の形態を示すものである。各方向
毎に電極の角度と方向を変化させる実施の形態の場合に
は、図５(ａ)に示したようにスルホール中心（ランド部
分９の中心）とボンディングワイヤ４で接続する半導体
素子１上のボンディングパッド５を直線２４で結んだ方
向に電極片部８を設けることによりボンディングワイヤ
４の長さを最短にすることが可能となり、ボンディング
ワイヤ接続後の樹脂封止工程等でボンディングワイヤ同
士の接触を防止することができる。さらに、図５(ｂ)に
矢印２５で示すように、スルーホール中心（ランド部分
９の中心）と半導体素子１上のボンディングパッド５を
結んだ線が、他の同様な線と接触あるいはボンディング
ワイヤ４の径以下に接近する場合には、図５(ｃ)に矢印
２６、２７で示すように電極片部８の形状を曲げて形成
して変更することによりボンディングワイヤ４を接触あ
るいは接近しないようにすることが可能となる。また、
ボンディングワイヤ４のボンディングループ形状は、全
てのボンディングワイヤを同一形状としても良いし、半
導体素子１に近いボンディングワイヤ４の高さを低く
し、半導体素子１から遠くなるにつれボンディングワイ
ヤ４の高さを高くすることにより、ボンディングワイヤ
４同士の接触等が起こりにくくすることも可能となる。FIG. 4 shows an embodiment of the embodiment shown in FIG. 2 (b) in which the electrode pieces 8 which are slightly extended and connected within a range adjacent to the through hole 6 are arranged in various ways. . FIG. 4A shows an embodiment in which all the electrode pieces 8 are arranged at the same angle and in the same direction, and FIG. 4B shows a plurality of electrode pieces 8 arranged on a substrate. FIG. 4C shows an embodiment in which the angles and directions of the electrode pieces 8 are aligned in the block (FIG. 4B). This shows an embodiment in which the angle and direction are changed for each piece 8. In the case of the embodiment in which the angle and direction of the electrode are changed in each direction, the semiconductor element 1 connected to the center of the through hole (the center of the land portion 9) and the bonding wire 4 as shown in FIG. By providing the electrode piece portions 8 in the direction connecting the bonding pads 5 with the straight lines 24, the length of the bonding wires 4 can be minimized. Contact can be prevented. Further, as shown by an arrow 25 in FIG. 5B, a line connecting the center of the through hole (the center of the land portion 9) and the bonding pad 5 on the semiconductor element 1 is in contact with another similar line or a bonding wire. In the case of approaching less than the diameter of 4, the shape of the electrode piece 8 is bent and changed as shown by arrows 26 and 27 in FIG. It becomes possible to. Also,
The bonding loop shape of the bonding wire 4 may be the same shape for all the bonding wires, the height of the bonding wire 4 close to the semiconductor element 1 may be reduced, and the height of the bonding wire 4 may increase as the distance from the semiconductor element 1 increases. By increasing the height, it is possible to make it difficult for the bonding wires 4 to contact each other.

【００１５】以上説明したように電極片部８を上記（数
１）式の関係を有するように形成したことにより、半導
体素子１を搭載する基板２上においてピッチが０．８ｍ
ｍ以下と狭い隣接した電極部の間を配線を引き回すこと
なく、上記基板２を介して半導体素子上のボンデイング
パッド５とプリント配線板（回路基板）に実装するため
のはんだボール等の接合材との間の接続を可能にするこ
とができる。次に本発明に係る半導体装置の他の実施の
形態を図６を用いて説明する。図６は本発明に係る半導
体装置の他の実施の形態を示す樹脂で封止していない状
態の部分断面図である。この実施の形態の場合、基板２
には、多数の穴５３を外形の内側にこの外形辺に沿って
所望のピッチで配設し、且つ裏面において前記各穴５３
に対応するように多数の電極部５２を２列に並設形成し
た。そして半導体素子１を、基板２の表面における前記
多数の穴５３の内側に導電ペーストからなる接着剤ある
いははんだ等を用いて固定して搭載する。半導体素子１
の外形辺に沿って配設された多数のボンディングパッド
５の各々と前記基板２の裏面に並設形成された多数の電
極部５２の裏面の各々との間において前記各穴５３を通
してボンディングワイヤ４により接続を行う。その後半
導体素子１の上面およびボンディングワイヤ４の部分お
よび基板２の上面を樹脂封止してＢＧＡの半導体装置が
構成される。この半導体装置は、プリント基板（回路基
板）５５にはんだボール等の接合材５４を用いて基板２
の裏面に並設された多数の電極部５２との間で接合され
て実装される。この実施の形態においても、上面から見
ると図１に示すような配列関係となる。As described above, since the electrode piece 8 is formed so as to have the relationship of the above equation (1), the pitch is 0.8 m on the substrate 2 on which the semiconductor element 1 is mounted.
m and a bonding material such as a solder ball to be mounted on a printed wiring board (circuit board) with the bonding pad 5 on the semiconductor element via the substrate 2 without routing the wiring between adjacent electrode portions as narrow as m or less. Connection between the two. Next, another embodiment of the semiconductor device according to the present invention will be described with reference to FIG. FIG. 6 is a partial cross-sectional view of another embodiment of the semiconductor device according to the present invention in a state where the semiconductor device is not sealed with a resin. In the case of this embodiment, the substrate 2
Has a large number of holes 53 arranged at a desired pitch along the outer side of the outer shape, and each of the holes 53 on the back surface.
A number of electrode portions 52 are formed in two rows in parallel to correspond to the above. Then, the semiconductor element 1 is mounted on the inside of the large number of holes 53 on the surface of the substrate 2 by using an adhesive made of a conductive paste or solder or the like. Semiconductor element 1
The bonding wire 4 passes through each of the holes 53 between each of a large number of bonding pads 5 arranged along the outer side of the substrate and each of the back surfaces of a large number of electrode portions 52 formed in parallel on the back surface of the substrate 2. The connection is made by. Thereafter, the upper surface of the semiconductor element 1, the portion of the bonding wire 4 and the upper surface of the substrate 2 are sealed with a resin to form a BGA semiconductor device. This semiconductor device uses a bonding material 54 such as a solder ball on a printed circuit board (circuit board) 55 to form a substrate 2.
Are mounted by being joined to a large number of electrode portions 52 arranged in parallel on the back surface of the substrate. Also in this embodiment, when viewed from above, the arrangement relationship is as shown in FIG.

【００１６】本発明に係るボンディングワイヤ４は、通
常の半導体に用いられている、金、アルミニウム、銅
等、あるいはこれらに微量の添加物を混合したもの、ま
たはこれらの表面にエポキシ、フェノール、ポリイミ
ド、シリコーン等の絶縁性の樹脂を被覆したものを使用
することが可能である。本発明に係る半導体装置は、半
導体素子１上のボンディングパッド５と基板２上の電極
部７または電極片部８をボンディングワイヤ４で接続
後、半導体素子１およびボンディングワイヤ接続部等を
保護し、取り扱いを容易にするため、樹脂により封止さ
れる。図７(ａ)は、トランスファモールド方式による樹
脂封止工程状態の概略を示したものである。内部の接続
が終了した半導体装置１０は、加熱した上金型１１と下
金型１２の間に保持される。その後、加熱溶融した封止
樹脂１３が金型のキャビティ部分１４に移送される。移
送された封止樹脂１３により金型のキャビティ部分１４
が充填され、さらに金型から取り出し可能な硬さまで封
止樹脂が硬化した後、樹脂封止後の半導体装置が金型１
１、１２より取り出される。その後、封止樹脂の硬化反
応をより進めるため高温槽内で加熱を行い、図７(ｂ)に
示す形態で樹脂封止工程が終了する。The bonding wire 4 according to the present invention is made of gold, aluminum, copper, or the like used in ordinary semiconductors, or a mixture of these with a small amount of additives, or epoxy, phenol, polyimide on the surface thereof. It is possible to use those coated with an insulating resin such as silicone. In the semiconductor device according to the present invention, after connecting the bonding pad 5 on the semiconductor element 1 to the electrode part 7 or the electrode piece part 8 on the substrate 2 by the bonding wire 4, the semiconductor element 1 and the bonding wire connection part are protected. It is sealed with resin for easy handling. FIG. 7A schematically shows a state of a resin sealing step by a transfer molding method. The semiconductor device 10 for which the internal connection has been completed is held between the heated upper mold 11 and the lower mold 12. Thereafter, the heat-melted sealing resin 13 is transferred to the cavity portion 14 of the mold. The cavity part 14 of the mold is transferred by the transferred sealing resin 13.
Is filled, and the sealing resin is cured to a hardness that can be taken out of the mold.
It is taken out from 1 and 12. Thereafter, heating is performed in a high-temperature bath in order to further advance the curing reaction of the sealing resin, and the resin sealing step is completed in the form shown in FIG. 7B.

【００１７】図８(ａ)は、液状の樹脂を用いる封止工程
状態の概略を示したものである。シリンジ１５に入れら
れた液状樹脂１６を配線が終了した半導体装置１０上に
塗布し、高温槽内で加熱により封止樹脂の硬化を行い、
図８(ｂ)に示す形態で樹脂封止工程が終了する。この場
合において、基板２における表面の最外周部にダム７１
を設けることによって封止する液状の樹脂が流出するの
を防止することができる。本発明に用いられる封止樹脂
は、一般に半導体封止に用いられているものが使用可能
で、例えばエポキシ樹脂、フェノール樹脂、ポリイミド
樹脂、シリコーン樹脂夫々単独あるいは混合物に、これ
らの硬化剤、硬化促進剤、着色剤、難燃剤、および二酸
化珪素、アルミナ等の充填剤、アルコキシシラン、チタ
ネート、アルミキレート等のカップリング剤等を配合し
たものがトランスファモールドに使用され、上記樹脂混
合物を適当な溶剤で溶解、分散したもの、あるいは塗布
温度で液状となる樹脂組成物がシリンジ等による封止用
樹脂として用いられる。図９には、本発明に係る半導体
装置の組立工程の概略を示す。先ず、図９(ａ)に示すよ
うに基板２上に接着剤等１７を用いて半導体素子１を搭
載する。次に、図９(ｂ)に示すように半導体素子１上の
ボンディングパッド５と基板２上の電極部７、８とをボ
ンディングワイヤ４を用いて接続する。次に、図９(ｃ)
に示すようにトランスファモールドあるいは液状樹脂の
塗布よる樹脂３０による封止を行う。次に、図９(ｄ)に
示すように樹脂封止後、当該半導体装置をプリント配線
板（図示せず）に搭載・接続するためのはんだボール等
の接合材１８を接続し、目的の半導体装置を得る。FIG. 8A schematically shows a state of a sealing step using a liquid resin. The liquid resin 16 put in the syringe 15 is applied on the semiconductor device 10 on which wiring has been completed, and the sealing resin is cured by heating in a high-temperature bath.
The resin sealing step ends in the mode shown in FIG. In this case, the dam 71 is provided at the outermost peripheral portion of the surface of the substrate 2.
Is provided, it is possible to prevent the liquid resin to be sealed from flowing out. As the encapsulating resin used in the present invention, those generally used for semiconductor encapsulation can be used. For example, epoxy resin, phenol resin, polyimide resin, and silicone resin may be used alone or in a mixture of these curing agents and curing accelerators. Agents, coloring agents, flame retardants, and fillers such as silicon dioxide and alumina, and coupling agents such as alkoxysilanes, titanates, and aluminum chelates are used in the transfer mold, and the above resin mixture is mixed with an appropriate solvent. A resin composition that is dissolved or dispersed or becomes liquid at the application temperature is used as a sealing resin with a syringe or the like. FIG. 9 shows an outline of an assembling process of the semiconductor device according to the present invention. First, as shown in FIG. 9A, the semiconductor element 1 is mounted on the substrate 2 using an adhesive 17 or the like. Next, as shown in FIG. 9B, the bonding pads 5 on the semiconductor element 1 and the electrode portions 7 and 8 on the substrate 2 are connected using the bonding wires 4. Next, FIG.
As shown in (1), sealing with resin 30 by transfer molding or application of liquid resin is performed. Next, as shown in FIG. 9D, after sealing with a resin, a bonding material 18 such as a solder ball for mounting and connecting the semiconductor device to a printed wiring board (not shown) is connected, and the intended semiconductor is formed. Get the device.

【００１８】以上説明した実施の形態では、基板２上に
設けた電極部７または電極片部８の説明を容易にするた
め２列としたが、本発明に於いては基板２上の電極部７
または電極片部８の配列は必ずしも２列に限定されるも
のではなく、図１０に示したようにボンディングワイヤ
４の接触等が発生しない範囲で、電極部７または電極片
部８の配列数を例えば３列、４列と増加させることが可
能である。さらに、図１１（ａ）（ｂ）に示したように
プリント配線板との接続端子部１８には、ランド部５１
から内周及び／又は外周に向かって繋げた配線パターン
１９を設け、プリント配線板とははんだ等の接合材１８
ａ、１８ｂ、１８ｃ、１８ｄで接続することによって、
プリント配線板側において必要に応じてランド間を通ら
ないように、配線同士が交差しないように配線を形成す
ることが可能となる。図１１（ｂ）には、２列のランド
部５１の各々に所望の長さで内周および外周に伸ばして
繋げた配線パターン１９を一つおきに形成した場合を示
す。これによって、半導体装置１を搭載する基板２の寸
法を増大させるのを少なくし、しかも端子数の減少が生
じないようにして、プリント配線板との間における接合
材１８ａ〜１８ｄによる接続ピッチを広げることが可能
となる。以上、本発明に係る実施の形態について具体的
に説明したが、本発明は前記実施の形態に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
である。In the embodiment described above, the electrode section 7 or the electrode piece section 8 provided on the substrate 2 is arranged in two rows in order to facilitate the description. 7
Alternatively, the arrangement of the electrode pieces 8 is not necessarily limited to two rows, and the number of the electrode pieces 7 or the electrode pieces 8 may be reduced as long as the contact of the bonding wire 4 does not occur as shown in FIG. For example, the number can be increased to three rows or four rows. Further, as shown in FIGS. 11A and 11B, a land portion 51 is provided on the connection terminal portion 18 with the printed wiring board.
And a wiring pattern 19 connected to the inner and / or outer periphery of the printed wiring board.
By connecting at a, 18b, 18c, 18d,
Wiring can be formed on the printed wiring board side so that the wiring does not cross each other as necessary so as not to pass between lands. FIG. 11B shows a case where wiring patterns 19 extending to the inner and outer peripheries of a desired length and connected to each other are formed on each of the two rows of land portions 51. This reduces the increase in the size of the substrate 2 on which the semiconductor device 1 is mounted, and increases the connection pitch between the printed wiring board and the bonding materials 18a to 18d so that the number of terminals does not decrease. It becomes possible. As described above, the embodiment according to the present invention has been specifically described. However, the present invention is not limited to the above embodiment, and can be variously modified without departing from the gist thereof.

【００１９】[0019]

【発明の効果】本発明によれば、基板に半導体素子を搭
載し、ボンディングワイヤにより基板上の電極と半導体
素子上のボンディングパッドとの間の接続を行う方式に
おいて、基板上に配線の引き回しを行わず、スルーホー
ル上、スルーホール近傍等にワイヤボンディングを行う
ことにより、配線引き回しの間隔をとることができない
端子ピッチが０．８ｍｍ以下の狭い半導体装置を実現す
ることが可能となる効果を奏する。According to the present invention, in a system in which a semiconductor element is mounted on a substrate and a connection is made between an electrode on the substrate and a bonding pad on the semiconductor element by a bonding wire, wiring is provided on the substrate. By performing the wire bonding on the through-hole, in the vicinity of the through-hole, or the like without performing the above, there is an effect that it is possible to realize a semiconductor device having a narrow terminal pitch of 0.8 mm or less, which cannot take a wiring interval. .

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明に係る半導体装置の一実施の形態であっ
て樹脂封止を行っていない状態を示す上面概略図であ
る。FIG. 1 is a schematic top view showing an embodiment of a semiconductor device according to the present invention, in which resin sealing is not performed.

【図２】本発明に係る基板上の電極とボンディングワイ
ヤとの接続に関する実施の形態を示す概略図である。FIG. 2 is a schematic view showing an embodiment relating to connection between an electrode on a substrate and a bonding wire according to the present invention.

【図３】本発明に係る実施の形態におけるスルーホール
に隣接した範囲内に形成された電極片部とランド径との
関係を示す説明図である。FIG. 3 is an explanatory diagram showing a relationship between an electrode piece formed in a range adjacent to a through hole and a land diameter in the embodiment according to the present invention.

【図４】本発明に係るスルーホールに隣接した範囲内に
形成された電極片部についての各種の実施の形態を示す
配列状態についての説明図である。FIG. 4 is an explanatory view of an arrangement state showing various embodiments of an electrode piece formed in a range adjacent to a through hole according to the present invention.

【図５】図４に示す実施の形態と異なる電極片部につい
ての実施の形態を示す配列方法についての説明図であ
る。FIG. 5 is an explanatory diagram of an arrangement method showing an embodiment of an electrode piece different from the embodiment shown in FIG. 4;

【図６】本発明に係る半導体装置の他の実施の形態であ
って樹脂封止を行っていない状態を示す一部断面図であ
る。FIG. 6 is a partial cross-sectional view showing another embodiment of the semiconductor device according to the present invention, in which resin sealing is not performed.

【図７】本発明に係る半導体装置を製造するためのトラ
ンスファモールド方式による樹脂封止工程を説明するた
めの概略図である。FIG. 7 is a schematic diagram for explaining a resin sealing step by a transfer molding method for manufacturing a semiconductor device according to the present invention.

【図８】本発明に係る半導体装置を製造するための液状
樹脂塗布による樹脂封止工程を説明するための概略図で
ある。FIG. 8 is a schematic diagram for explaining a resin sealing step by applying a liquid resin for manufacturing a semiconductor device according to the present invention.

【図９】本発明に係る半導体装置を組立る工程を説明す
るための概略図である。FIG. 9 is a schematic diagram for explaining a step of assembling the semiconductor device according to the present invention.

【図１０】本発明に係る半導体装置において電極の配列
を増した場合の実施の形態を示す概略断面図である。FIG. 10 is a schematic sectional view showing an embodiment in which the arrangement of electrodes is increased in the semiconductor device according to the present invention.

【図１１】本発明に係る半導体装置において、プリント
配線板との接続側に端子間隔を広げるための配線を設け
た場合の実施の形態を示す図である。FIG. 11 is a view showing an embodiment in a case where a wiring for widening a terminal interval is provided on a connection side with a printed wiring board in a semiconductor device according to the present invention.

【符号の説明】[Explanation of symbols]

１…半導体素子、 ２…基板、 ３…ボンディングワイ
ヤ接続部（電極部）、４…ボンディングワイヤ、 ５…
ボンディングパッド、 ６…スルーホール、７…電極
部、 ８…電極片部、 ９…ランド、 １０…半導体装
置、 １１…上金型、 １２…下金型、 １３…封止樹
脂、 １４…キャビティ、 １５…シリンジ、 １６…
液状封止樹脂、 １７…接着剤、 １８…端子部分、１
８ａ〜１８ｄ…はんだボール等の接合材、 １９…配
線、 ３０…樹脂、 ５１…ランド部、 ７１…ダムDESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Substrate, 3 ... Bonding wire connection part (electrode part), 4 ... Bonding wire, 5 ...
Bonding pad, 6 through-hole, 7 electrode part, 8 electrode piece part, 9 land, 10 semiconductor device, 11 upper mold, 12 lower mold, 13 sealing resin, 14 cavity, 15 ... Syringe, 16 ...
Liquid sealing resin, 17 ... adhesive, 18 ... terminal part, 1
8a to 18d: bonding material such as solder balls, 19: wiring, 30: resin, 51: land, 71: dam

───────────────────────────────────────────────────── フロントページの続き (72)発明者 春田 亮 東京都小平市上水本町五丁目20番１号株式 会社日立製作所半導体事業部内 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Ryo Haruta 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo In the semiconductor division of Hitachi, Ltd.

Claims (13)

【特許請求の範囲】[Claims] 【請求項１】表面から裏面まで導体でつながった多数の
スルーホールを外形の内側にこの外形辺に沿って所望の
間隔で配設し、且つ前記表面において各々が前記スルー
ホールの各々に接続されて該スルーホールの近傍の範囲
で互いに接触しないように伸びた多数の電極片部を並設
形成した基板を設け、該基板の表面における前記多数の
電極片部の内側に半導体素子を搭載し、該半導体素子の
外形辺に沿って配設された多数のボンディングパッドの
各々と前記基板の表面に並設形成された多数の電極片部
の各々との間においてボンディングワイヤにより接続を
行い、少なくとも前記半導体素子及び前記基板の表面を
前記ボンディングワイヤが埋設されるように樹脂により
封止したことを特徴とする半導体装置。1. A plurality of through-holes connected by conductors from the front surface to the back surface are arranged inside the outer shape at a desired interval along the outer side, and each of the through-holes is connected to each of the through-holes on the front surface. A substrate is formed in which a number of electrode pieces extending in parallel to each other in a range near the through hole are provided, and a semiconductor element is mounted on the surface of the substrate inside the plurality of electrode pieces, A connection is made by a bonding wire between each of a large number of bonding pads disposed along the outer side of the semiconductor element and each of a large number of electrode pieces formed in parallel on the surface of the substrate, and A semiconductor device, wherein surfaces of a semiconductor element and the substrate are sealed with a resin so that the bonding wires are embedded therein. 【請求項２】前記各電極辺部の端と各スルーホールの中
心との間の長さＬを前記スルーホールのピッチＰに対し
てＰ／√２以下とすることを特徴とする請求項１記載の
半導体装置。2. The method according to claim 1, wherein a length L between an end of each electrode side portion and a center of each through hole is not more than P / √2 with respect to a pitch P of the through holes. 13. The semiconductor device according to claim 1. 【請求項３】前記スルーホールのピッチが０．８ｍｍ以
下とすることを特徴とする請求項１または２記載の半導
体装置。3. The semiconductor device according to claim 1, wherein the pitch of the through holes is 0.8 mm or less. 【請求項４】前記各電極片部の伸びた方向が、前記半導
体素子が搭載される内側に向かうことを特徴とする請求
項１記載の半導体装置。4. The semiconductor device according to claim 1, wherein the direction in which each of the electrode pieces extends extends toward the inside on which the semiconductor element is mounted. 【請求項５】前記各電極片部の伸びた方向が、前記半導
体素子が搭載される内側で、且つ前記半導体素子の２つ
の対称線に対してほぼ対称に向かうことを特徴とする請
求項１記載の半導体装置。5. The semiconductor device according to claim 1, wherein the direction in which each of the electrode pieces extends is substantially symmetric with respect to two symmetry lines of the semiconductor element inside the semiconductor element. 13. The semiconductor device according to claim 1. 【請求項６】前記各電極片部の伸びた方向が、前記半導
体素子上に配設された各ボンディングパッドに向かうこ
とを特徴とする請求項１記載の半導体装置。6. The semiconductor device according to claim 1, wherein the direction in which each of the electrode pieces extends extends toward each of the bonding pads provided on the semiconductor element. 【請求項７】前記各電極片部の伸びた方向が、所望の方
向に向かうことを特徴とする請求項１記載の半導体装
置。7. The semiconductor device according to claim 1, wherein the direction in which each of the electrode pieces extends extends in a desired direction. 【請求項８】表面から裏面まで導体でつながった多数の
スルーホールを外形の内側にこの外形辺に沿って所望の
間隔で配設し、且つ前記表面において各々が前記スルー
ホールの各々に同心状に接続された多数の電極部を並設
形成した基板を設け、該基板の表面における前記多数の
電極部の内側に半導体素子を搭載し、該半導体素子の外
形辺に沿って配設された多数のボンディングパッドの各
々と前記基板の表面に並設形成された多数の電極部の各
々との間においてボンディングワイヤにより接続を行
い、少なくとも前記半導体素子及び前記基板の表面を前
記ボンディングワイヤが埋設されるように樹脂により封
止したことを特徴とする半導体装置。8. A plurality of through-holes connected by conductors from the front surface to the back surface are arranged inside the outer shape at a desired interval along the outer side, and each of the through-holes is concentric with the through-hole on the front surface. A plurality of electrode portions connected in parallel to each other are provided, a semiconductor element is mounted inside the plurality of electrode portions on the surface of the substrate, and a number of the plurality of electrode portions are arranged along the outer side of the semiconductor element. Are connected by bonding wires between each of the bonding pads and a plurality of electrode portions formed in parallel on the surface of the substrate, and the bonding wires are buried at least in the surfaces of the semiconductor element and the substrate. Semiconductor device characterized by being sealed with a resin as described above. 【請求項９】多数の穴を外形の内側にこの外形辺に沿っ
て所望の間隔で配設し、且つ裏面において各々が前記各
穴に対応するように多数の電極部を並設形成した基板を
設け、該基板の表面における前記多数の穴の内側に半導
体素子を搭載し、該半導体素子の外形辺に沿って配設さ
れた多数のボンディングパッドの各々と前記基板の裏面
に並設形成された多数の電極部の裏面の各々との間にお
いて前記各穴を通してボンディングワイヤにより接続を
行い、少なくとも前記半導体素子及び前記基板の表面を
前記ボンディングワイヤが埋設されるように樹脂により
封止したことを特徴とする半導体装置。9. A substrate in which a large number of holes are arranged at desired intervals along the outer side of the outer shape and a plurality of electrode portions are formed in parallel on the back surface so as to correspond to the respective holes. A semiconductor element is mounted inside the plurality of holes on the surface of the substrate, and is formed in parallel with each of a number of bonding pads arranged along the outer side of the semiconductor element and on the back surface of the substrate. A connection was made between each of the back surfaces of the large number of electrode portions with a bonding wire through each of the holes, and at least the surface of the semiconductor element and the substrate were sealed with a resin so that the bonding wire was embedded. Characteristic semiconductor device. 【請求項１０】前記基板を絶縁フィルムを基材として形
成したことを特徴とする請求項１または８または９記載
の半導体装置。10. The semiconductor device according to claim 1, wherein said substrate is formed using an insulating film as a base material. 【請求項１１】前記ボンディングワイヤにワイヤ表面を
絶縁性の樹脂で被覆したボンディングワイヤを用いるこ
とを特徴とする請求項１または８または９記載の半導体
装置。11. The semiconductor device according to claim 1, wherein said bonding wire is a bonding wire whose surface is covered with an insulating resin. 【請求項１２】前記基板の裏面に、各々が前記各スルー
ホールに接続された多数のパッドを並設し、該多数のパ
ッドの内近接したものの同士の一方を内側または外側に
配線を引き出して回路基板との接続端子を形成すること
を特徴とする請求項１または８記載の半導体装置。12. A plurality of pads, each of which is connected to each of said through holes, are arranged in parallel on the back surface of said substrate, and one of adjacent ones of said plurality of pads is drawn out inward or outward by wiring. 9. The semiconductor device according to claim 1, wherein a connection terminal to a circuit board is formed. 【請求項１３】前記基板における表面の最外周部に、封
止する液状の樹脂が流出するのを防止するためのダムを
設けたことを特徴とする請求項１または８記載の半導体
装置。13. The semiconductor device according to claim 1, wherein a dam for preventing a liquid resin to be sealed from flowing out is provided at an outermost peripheral portion of a surface of said substrate.
JP8344755A 1996-12-25 1996-12-25 Semiconductor device Pending JPH10189637A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8344755A JPH10189637A (en) 1996-12-25 1996-12-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8344755A JPH10189637A (en) 1996-12-25 1996-12-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH10189637A true JPH10189637A (en) 1998-07-21

Family

ID=18371730

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8344755A Pending JPH10189637A (en) 1996-12-25 1996-12-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH10189637A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008010729A (en) * 2006-06-30 2008-01-17 Hitachi Aic Inc Mounting board
JP2011211211A (en) * 2011-05-11 2011-10-20 Nec Corp Wiring board, semiconductor device, and method of manufacturing the same
CN112117268A (en) * 2020-09-25 2020-12-22 中科芯(苏州)微电子科技有限公司 Chip integrated module

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008010729A (en) * 2006-06-30 2008-01-17 Hitachi Aic Inc Mounting board
JP2011211211A (en) * 2011-05-11 2011-10-20 Nec Corp Wiring board, semiconductor device, and method of manufacturing the same
CN112117268A (en) * 2020-09-25 2020-12-22 中科芯(苏州)微电子科技有限公司 Chip integrated module
CN112117268B (en) * 2020-09-25 2023-02-10 中科芯(苏州)微电子科技有限公司 Chip integrated module

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