JPH10188471A - Data producing device and data reproducing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data reproducing device and data reproducing method capable of shortening the time from read-out of a disk to output of decoded data without increasing the circuit scale and the speed of clock. SOLUTION: Reproduced data reproduced by reproducing means 2, 3, 13 are sent to an error correcting circuit 7 and a ring buffer memory 6 from a recording medium 1 through a first buffer memory 5A accumulating data for one frame, reproduced data error-corrected by the error correcting circuit 7 is sent to a ring buffer memory 5B through a second buffer memory 5B accumulating data for one frame, and reproduced data error-corrected by the error correcting circuit 7 is outputted with a variable rate thorough a ring buffer memory 6. The device is controlled by controllers 10, 11 controlling operation of a reproducing means 13 and the ring buffer memory 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a data reproducing apparatus and a data reproducing method suitable for performing variable rate reproduction on (Digital Video Disc).

[0002]

2. Description of the Related Art An optical disk (DVD) has been developed which can record a large amount of data by using a laser beam having a short wavelength and using an objective lens having a large numerical aperture. DVD includes, for example, MPEG (Moving Pictu
re Experts Group 2). DVD is
It is also expected as a data recording medium for recording a large amount of data.

As a reproducing apparatus for reproducing recorded data of a DVD, there has been proposed a reproducing apparatus adapted to a variable rate. Such a variable-rate compatible playback device is provided with a ring buffer memory. The ring buffer memory is basically configured as shown in FIG.

[0006] As shown in FIG. 16, the ring buffer memory has such an address structure that when it reaches the end address, it returns to the start address. That is, as shown in FIG. 16, when the address is from “0” to “11”, the address is advanced to “0”, “1”, “2”,... Next, the process returns to the address “0” and proceeds again to “1”, “2”,. Such a ring buffer memory is specifically constituted by a FIFO.

[0005] The write pointer WP indicates an address at which writing has been completed. The ECC end pointer indicates an address at which the error correction processing has been completed. The read pointer RP indicates an address at which reading has been completed. In the case shown in the figure, since the write pointer WP is located at the address “11”, data has been written up to the address “11”. E
Since the CC end pointer EP is located at the address “9”, the error correction processing has been completed up to the address “9”. Since the read pointer RP is located at the address “2”, the writing has been completed up to the address “2”. Therefore, the error correction processing is completed at addresses “3” to “9”, readable data is located, and data that has already been read and becomes unnecessary is located at addresses “0” to “2”. Address "10", "1"
The newly written data is located at "1".

In the above-described ring buffer memory, it is necessary to prevent the read pointer RP from overtaking the ECC end pointer EP. The ECC end pointer E
It is necessary to prevent P from overtaking the write pointer WP. When the write pointer WP catches up with the read pointer RP, the writing of demodulated data is temporarily stopped (overflow control).

[0007] As a configuration of a data reproducing apparatus provided with such a ring buffer memory and adapted to a variable rate, those shown in FIGS. 17 to 19 are conceivable.

In FIG. 17, demodulation circuit 101 outputs
Demodulated data of a reproduction signal of the optical disk is output. This demodulated data is first stored in the ring buffer memory 102 (access e). Ring buffer memory 102
18 stores data of one ECC block in FIG.
As shown in (1), the data stored in the ring buffer memory 102 is transferred to an error correction processing circuit 103, where an error correction process is performed. First, the error correction process
The processing of the I series is performed (access f1), the processing of the P0 series is performed (access f2), and the processing of the PI series is performed again (access f3). When the error correction processing for the PI series, the PO series, and the PI series again is completed, data transfer becomes possible. In response to the output request, as shown in FIG. 19, the data for which the error correction processing has been completed is read from the ring buffer memory 102, and the read data is used as the descramble and error detection circuit 104.
, And transferred to the external host computer 105 via the interface 106 (access g).

[0009]

In a disk playback apparatus compatible with a variable rate, it is conceivable that a connection with a host computer is established by, for example, an ATAPI interface, and data is transferred at a transfer rate of the ATAPI interface (16.6 MB / s). Have been. Further, it has been considered to read the disk at twice the normal speed.

However, in the above-described conventional data reproducing apparatus, the ring buffer memory 102 performs variable rate control,
Since it is used for error correction encoding processing, many accesses to the ring buffer memory 102 occur,
It is difficult to meet such demands.

That is, in the configuration described above, the access (access e) for writing the data of the demodulation circuit 101 and the access (access f1) for error correction processing of the PI series are performed on the ring buffer memory 102. P
Access for access to O-series error correction (access f
2), an access (access f3) for error correction processing of the PI sequence again, and an access (access g) for outputting data in response to an output request occur. FIG. 20 shows the timing of these accesses. As described above, since a large number of accesses occur to the ring buffer memory 102, it is difficult to double the disk reading speed and make the output rate correspond to the rate of the ATAPI interface.

By increasing the data width of the ring buffer memory or increasing the frequency of the operation clock,
Although it is conceivable to meet such a demand, increasing the data width of the buffer memory or increasing the frequency of the operation clock leads to an increase in circuit size and cost.

Therefore, as shown in FIGS. 21 to 24, it is conceivable to provide a memory 113 for error correction processing separately from the ring buffer memory 112. In FIG. 21, a demodulation circuit 111 outputs demodulated data of a reproduction signal of an optical disk. The demodulated data for one ECC block is first stored in the error correction memory 113 (access H). Then, as shown in FIG.
The error correction circuit 114 performs the processing of the PI series (access I1), performs the processing of the PO series (access 12), and performs the processing of the PI series again (access 1).
3). When the error correction processing for the PI series, the PO series, and the PI series again is completed, as shown in FIG. 23, the data in the memory 113 for error correction processing is read (access J), and the descrambling and error detection circuit 115 is performed. Is descrambled. Then, this data is transferred to the ring buffer memory 112 (access h). In response to the output request, as shown in FIG. 24, the data after the error correction processing is read from the ring buffer memory 112 and transferred to the external host computer 116 via the interface 117 (access i). .

As described above, when the error correction memory 113 is provided separately from the ring buffer 112, it is not necessary to access the ring buffer memory 112 at the time of error correction processing. However, in this example, since the access (access h) of the input data to the ring buffer memory 112 occurs after the error correction processing is completed, the timing is as shown in FIG. , It is difficult to meet the requirement that the output be an ATAPI interface.

Therefore, as shown in FIGS. 26 to 29, two memories, ie, a memory 123 and a memory 124, are prepared for error correction. Correction processing may be performed. In FIG. 26, the demodulation circuit 121
Outputs demodulated data of the reproduction signal of the optical disk. The demodulated data for one ECC block is first stored in the error correction memory 123 (access K). Then, as shown in FIG.
25, the processing of the PI series is performed (access L
1) The processing of the P0 series is performed (access L2), and the processing of the PI series is performed again (access L3). At this time, at the same time, the demodulated data for the next 1 ECC block from the demodulation circuit 121 is stored in the other memory I for error correction processing.
24 (access K). When the error correction processing for the PI series, the PO series, and the PI series again is completed, as shown in FIG. 28, data in the memory 123 for error correction processing is read (access M), and the descrambling and error detection circuit 116 is used. Is descrambled. Then, this data is transferred to the ring buffer memory 122 (access k). In response to the output request, as shown in FIG. 29, the data for which the error correction processing has been completed is read from the ring buffer memory 122, and is output to the external host computer 2 via the interface 128.
7 (access 1).

By doing so, the writing of demodulated data (access K) and the error correction processing (access L1, L2) are performed.
2, L3) occur at the same time, so that the timing is as shown in FIG. 30, and the time from the reading of the disk to the output of the error correction processing data can be reduced. This allows
It is possible to meet the requirement that the reading speed of the disk is double speed and the output is the ATAPI interface.

However, in such a configuration, two memories 123 and 12 are used as memories for error correction processing.
4B is required, which causes a problem that the circuit scale increases.

Therefore, an object of the present invention is to provide a data reproducing apparatus and a data reproducing method capable of shortening the time from reading a disk to outputting decoded data without increasing the circuit scale or increasing the clock speed. Is to provide.

[0019]

A data reproducing apparatus according to the present invention comprises: reproducing means for reproducing digital data from a recording medium; error correcting means for performing error correction processing on data reproduced by the reproducing means; A ring buffer memory for variable rate control for outputting the reproduced data having been error-corrected by the error correcting means at a variable rate, and storing at least one frame of reproduced data supplied from the reproducing means for storing the error corrected means and the ring buffer; A first buffer memory for sending to the memory; and a second buffer memory for storing at least one frame of the reproduced data having the error corrected by the error correcting means and sending the data to the ring buffer memory.
Buffer memory, and control means for controlling the operation of the reproducing means and the ring buffer memory. When data of one frame is stored in the first buffer memory, one frame of data is stored in the first buffer memory. The data is sent to the error correction means and written to the ring buffer memory. The data written to the ring buffer memory is subjected to a first series of error correction by the error correction means, and the error-corrected data is written to the ring buffer memory. When the first series of error corrections is completed, the second series of data is read from the ring buffer memory and written to the second buffer memory, and the second series of data is error corrected from the second buffer memory. Error correction for the data written to the ring buffer memory. Means for correcting the second series of errors, writing the error-corrected data to the ring buffer memory, and, upon completion of the PI error correction, transferring the first series of data from the ring buffer memory to the error correcting means. And write the data to the second buffer memory, perform error correction on the data written to the second buffer memory by the error correction means, write the error-corrected data to the ring buffer memory, and respond to the output request. The error-corrected data is output from the ring buffer memory at the transfer speed.

The first and second buffer memories in the data reproducing apparatus according to the present invention have, for example, storage capacities for two to three frames of the error correction block, respectively.

[0021] In the data reproducing method according to the present invention, the first buffer memory stores demodulated reproduced data in the first buffer memory.
And when the data of one frame is accumulated in the first buffer memory, the data of one frame is sent from the first buffer memory to the error correction means, written to the ring buffer memory, and written to the ring buffer memory. A second series of error correction means for performing error correction of the first stream by the error correction means and writing the error-corrected data to the ring buffer memory; A second series of data is read from the memory and written to the second buffer memory, and the second series of data is read from the second buffer memory.
Is sent to the error correction means, the data written to the ring buffer memory is subjected to a second error correction by the error correction means, and the error-corrected data is written to the ring buffer memory. A fourth step of sending the first series of data from the ring buffer memory to the error correcting means to the error correcting means and writing the data in the second buffer memory when the PI error correction is completed, and a second buffer memory. A fifth step of performing error correction on the data written in the ring buffer by the error correction means, and writing the error-corrected data to the ring buffer memory; And a sixth step of outputting data.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an optical disk reproducing apparatus to which the present invention is applied. In the optical disk reproducing apparatus shown in FIG. 1, as the optical disk 1, an optical disk (DVD) that can record a large amount of data by using a laser beam having a short wavelength and using an objective lens having a large numerical aperture is used. Can be

One sector of data recorded on the optical disk 1 is composed of data of 12 rows × 172 bytes, as shown in FIG. At the beginning of one sector, a 4-byte ID indicating a physical address and a 2-byte parity IED are provided for the ID. Then, 2048 bytes after the 6-byte reserve data RSV are used as a main data area. At the end of one sector, a 4-byte error detection code is added.

Then, as shown in FIG. 3, data of one sector (12 rows × 172 bytes) is collected for 16 sectors and two-dimensionally arranged in (192 rows × 172 bytes).
An ECC block is configured. A parity PI ((182, 172, 11) Reed-Solomon code) of 10 bytes of an inner code is added to the data of (192 rows × 172 bytes) in the row direction, and an outer code of 16 columns in the column direction. A parity PO ((208, 192, 17) Reed-Solomon code) is added.

The error-correction-encoded data is interleaved such that 16 rows of parity PO are arranged one row at a time in one data sector. Then, a sync of a predetermined pattern is added, and 8-16 modulation (called EFM plus) is performed and recorded. Therefore, the physical configuration of one sector of data recorded on the disc is as shown in FIG. Since it is 8-16 modulated, 1456
The bits correspond to 91 bytes. In FIG. 4, S
Y0, SY1, SY2,... Indicate sync patterns.

As shown in FIG. 1, a pickup 2 is provided so as to face the optical disc 1. The pickup 2 is movable by a servo circuit 13 in the radial direction of the disk. The pickup 2 reproduces a recording signal of the optical disc 1. The reproduction signal from the optical pickup 2 is supplied to the demodulation circuit 3. Demodulation circuit 3
Then, demodulation processing by EFM Plus is performed.

The output of the demodulation circuit 3 is supplied to a sector detection circuit 4. The sector detection circuit 4 detects a sync pattern SY0, SY1, SY2,... In the reproduced data, thereby detecting a sector. The output of the sector detection circuit 4 is supplied to the memory controller 10.

This optical disk reproducing apparatus includes first and second buffer memories 5A and 5B for temporarily storing reproduction data for performing error correction processing on the output of the demodulation circuit 3. The first and second buffer memories 5A, 5B are:
Each has 512 bytes and a capacity of 2.5 frames. The optical disc 1 is reproduced at, for example, a double speed. Then, a ring buffer memory 6 is provided to enable variable rate reproduction. The ring buffer memory 6 is composed of, for example, a FIFO. The ring buffer memory 6 is controlled by a buffer controller 10.

FIG. 5 shows a timing chart of a data processing operation based on ECC block timing in the optical disc reproducing apparatus, and a timing chart of a PI / PO error correction operation based on ECC frame timing. 6 and a timing chart of the PI / PI2 error correction operation based on the ECC frame timing is shown in FIG.

That is, in this optical disk reproducing apparatus,
As shown in FIG. 6, first, the output of the demodulation circuit 3 is written to the first buffer memory 5A. When one frame of demodulated data is stored in the first buffer memory 5A, ECC transfer (PI1 data transfer) is performed from the first buffer memory 5A to the error correction circuit 7, and at the same time,
Write data to the ring buffer memory 6. And
The error correction circuit 7 performs PI error correction, and writes error-corrected data to the ring buffer memory 6. Further, when PI error correction is completed, PO data is read from the ring buffer memory 6 and written into the second buffer memory 5B, and ECC transfer (PO data transfer) is executed from the second buffer memory 5B to the error correction circuit 7. I do. A 16-bit width memory is used as the ring buffer memory 6, and data of PO2 frames is accessed in words in the ring buffer memory 6 and ECC transfer (PO) of one frame is executed at the same time.
The remaining one frame is written into the second buffer memory 5B, and after the data transfer of one frame is completed, the data is read from the second buffer memory 5B and ECC transfer (P
Perform O). As a result, the PO error correction is performed in the error correction circuit 7, and the error-corrected data is written to the ring buffer memory 6. That is, PI / P
The O error correction is performed by reading (R: READ) / writing (W: WRITE) the error data from / to the ring buffer memory 6.

In the optical disk reproducing apparatus, when the PI error correction is completed, as shown in FIG. 7, the ECC transfer (PI2 data transfer) is performed from the ring buffer memory 6 to the error correction circuit 7 and the second Is written to the buffer memory 5B. Then, PI2 error correction is performed in the error correction circuit 7, and error-corrected data is written to the ring buffer memory 6.

This PI2 error correction is performed by reading (R: READ) / writing (W: WRITE) the error data from / to the second buffer memory 5B. That is, the PI2 error is
Since the data is output while the ECC transfer of the next frame following the ECC transfer (PI2 data transfer) of the data of the series is performed, if an error is output, the ECC transfer is temporarily stopped and the second buffer memory is output. PI2 error correction is performed by reading (R: READ) / writing (W: WRITE) error data for 5B.

After the PI2 error correction, the data of the frame is subjected to a descrambling process by a descrambling and error detecting circuit 8, an error detecting code is calculated, and the data is written to the ring buffer memory 6. In the scrambling process, scramble data generated using a value selected by the lower 7 to 4 bits of the physical address as an initial value and the main data take exclusive logic. When all the data of the PI2 error correction frame has been written into the ring buffer memory 6, the temporarily stopped ECC transfer is resumed.

As described above, the data completed up to the PI2 error correction is stored in the ring buffer memory 6. If the data requested to be output from the host computer 14 has been decoded, the data is transferred from the ring buffer memory 6 to the host computer 14 via the ATAPI interface 15 (host transfer).

Here, if the write pointer of the ring buffer memory 6 catches up with the read pointer, the ring buffer memory 6 overflows. Therefore, the system controller 11 shown in FIG. 1 monitors the read pointer WP and the write pointer RP in the buffer controller 10. The amount of data currently stored in the ring buffer memory 6 is calculated based on the write pointer WP and the read pointer RP. If the data amount exceeds a predetermined storage amount, it is determined that the ring buffer memory 6 may overflow, and a track jump command is sent to the track jump control circuit 12 (overflow processing).
The output of the track jump control circuit 12 is supplied to the servo circuit 13, and the track jump control is performed as needed.

The optical disk reproducing apparatus according to this embodiment is provided with an ATAPI interface 15, through which data can be transferred from the ring buffer memory 6 to the host computer 16 via the ATAPI interface 15. Further, a video decoder 17 and an audio decoder 18 are provided, and when a video signal compressed by MPEG2 is recorded on the optical disc 1, this video signal can be reproduced.

That is, the ATAPI interface 1
When data is transferred to the host computer 16 via the host computer 5, the data is read from the ring buffer memory 6 by a request signal from the host computer 16. This data is sent to the host computer 16 via the ATAPI interface 15.

To reproduce a video signal recorded on the optical disc 1 by being compressed by MPEG2,
A request signal is generated based on the remaining buffer capacity of the video buffer 20 and the audio buffer 21, and data is read from the ring buffer memory 6 by the request signal. The output of the ring buffer memory 6 is
It is supplied to the demultiplexer 19. The demultiplexer 19 separates video data and audio data according to the information in the packet header.

The video data is supplied to the video buffer video decoder 17 via the video buffer 20. The audio data is supplied to the audio decoder 18 via the audio buffer 21. The video data is decoded by the video decoder 17 based on, for example, MPEG2. The decoded video signal is output from the output terminal 22. Audio data is decoded by the audio decoder 18. The decoded audio data is output from the output terminal 23.

As described above, in the optical disk reproducing apparatus according to this embodiment, the following processing steps (1) to (1)
According to (6), the reproduction data is decoded.

(1) The demodulated reproduced data is written to the first buffer memory 5A.

(2) When one frame of data is accumulated in the first buffer memory 5A, the ECC transfer (PI1 data transfer) is executed from the first buffer memory 5A to the error correction circuit 7, and at the same time, the ring buffer memory 6
The error correction circuit 7 performs PI error correction, and writes the error-corrected data to the ring buffer memory 6.

(3) When the PI error correction is completed, the PO data is read from the ring buffer memory 6 and written into the second buffer memory 5B, and the ECC transfer (POC) from the second buffer memory 5B to the error correction circuit 7 is performed.
Data transfer), and the error correction circuit 7
Error correction is performed, and the error-corrected data is written to the ring buffer memory 6.

(4) When the PI error correction is completed, ECC transfer (PI2 data transfer) from the ring buffer memory 6 to the error correction circuit 7 is performed, and at the same time, data is written to the second buffer memory 5B.

(5) PI2 error correction is performed by the error correction circuit 7, and the descrambling and error detection circuit 8
Then, the error-corrected data is written to the ring buffer memory 6 via.

(6) The data corresponding to the output request from the host computer 14 is transferred from the ring buffer memory 6 to the AT.
The data is transferred to the host computer 14 via the API interface 15 (host transfer).

In the ring buffer memory 6, pointers are arranged as shown in FIG. 8, and the pointers move as shown in FIGS.

That is, the end address of the address of the ring buffer memory 6 follows the start address, and when the end address is reached, the address returns to the start address. WP is a write pointer, and this write pointer WP indicates an address at which writing has been completed. EP is an ECC end pointer, and this ECC end pointer indicates an address at which the error correction processing has been completed. RP is a read pointer, and this read pointer RP indicates an address at which reading has been completed.

Up to the write pointer WP, data before error correction has been written. The data before the error correction is subjected to error correction processing by the error correction circuit 7 and sent from the second buffer memory 5B to the ring buffer memory 6, and the error correction processing is completed up to the error pointer EP. Possible data.
Then, the reading has been completed up to the reading pointer RP.

As shown in FIG. 9, first, demodulated data is written to the ring buffer memory 6. When the writing of the demodulated data is completed, the write pointer WP is set to 1 ECC
The block is advanced by the number of blocks and the second
Data is transferred to the buffer memory 5B of
The data is transferred to the error correction circuit 7, and the PI series, PO
An error correction process for the series and the PI series is performed. When the error correction processing is completed, descrambling and error detection processing are executed, the error-corrected data is transferred from the second buffer memory 5B to the ring buffer memory 6, and when the data transfer of that block is completed, The error pointer EP is advanced by one block.

As shown in FIG. 10, the data after the error correction processing becomes outputable data. When there is an output request signal, data is read from the ring buffer memory 6, and
The read pointer RP is advanced. At this time, it is determined from the read pointer RP and the error pointer EP whether there is data that can be output. That is, the relationship between the error pointer EP and the read pointer RP is determined. If the relationship between the error pointer EP and the read pointer RP is EP> RP, there is data that can be output, so that data is output to the subsequent stage and the read pointer RP is advanced. If EP = RP, there is no outputable data, and no data is output.

As shown in FIG. 11, when there is no data output request from the subsequent circuit, the write pointer WP
Progresses, but the read pointer RP has stopped, so the write pointer WP catches up with the read pointer RP. The write pointer WP becomes the read pointer R
When P has caught up and EP = RP, the write operation is temporarily stopped. Then, when a track jump is required, the track jump is performed.
(Overflow control). Then, the read pointer R
When P advances and an input possible area is generated, writing of demodulated data becomes possible.

FIG. 12 shows an example of the configuration of the error correction circuit 7 used in this optical disk reproducing apparatus.

In FIG. 12, the error correction circuit 7 comprises an error correction integrated circuit 51, an error buffer 52, a flag memory 53, and an error counter 54. The error correction integrated circuit 51 is an integrated circuit that performs a Reed-Solomon code error correction process. The data EDT [7: 0] and the flag EFLG for erasure correction from the flag memory 53 are input to the error correction integrated circuit 51 via the RAM interface 56. In the error correction integrated circuit 51, parameters such as a code length and a parity number can be set programmably.

The error buffer 52 is composed of a FIFO. As a result of the error correction processing in the error correction integrated circuit 51, the error pattern is stored in the error buffer 52. The output of the error buffer 52 is supplied to the EX-OR circuit 55. The EX-OR circuit 55 includes R
Data is supplied from the second buffer memory 6 via the AM interface 56. In the case of an error pattern, in order to correct the error, the exclusive logic of the data from the error buffer 52 and the data from the second buffer memory 5B is obtained at the timing of the error position. Is corrected and returned to the second buffer memory 5B again.

The flag memory 53 stores an error flag pointer indicating an error position. The error flag is used when performing erasure correction.

The error counter 54 counts the number of errors as a result of the error correction processing in the error correction integrated circuit 51.

FIGS. 13 and 14 are timing charts showing the operation of the error correction circuit. In FIG.
STT is a control signal indicating the beginning of the code, ECD
E is a control signal indicating the end of the code, and ECYE is a control signal indicating the end of the code cycle. FIG.
As shown in FIG. 3, the correction result is output in a cycle as in the following equation.

Throughput = 2 × NCYC + 3 × PCYC + 13 Note that NCYC indicates the longer code length, and PCYC indicates the longer parity number.

As shown in FIG. 14, the integrated circuit for error correction 51 operates with a single clock ECCK. In FIG. 14, OSTT is a delayed output of the control signal ESTT, and is output 477 clocks (ECCK clock) after the control signal ESTT in a certain code sequence. Then, if an error is detected and the error can be corrected, ECOD =
The error pattern ECD [7: 0] and the error position ECA [7:
0] is output.

In the erasure correction mode,
Error pattern ECD [7: 0] and error position E
CA [7: 0] data is always output, but if the data at that position is correct, the error pattern is ECD
[7: 0] = 00 (H).

The error correction result, error pattern ECD
[7: 0] and error position ECA [7: 0]
At the error correction timing, the data in the error buffer 51 is read from the second buffer memory 5B, and the exclusive pattern of the error pattern read from the buffer 52 is obtained. The data is written back to the buffer memory 5B.

Here, the data in which the error pattern ECD [7: 0] = 00 (H) at the time of the erasure correction is actually correct, and is not meaningful even if the correction operation is performed. Not performed.

As described above, in the optical disk reproducing apparatus according to the present embodiment, when the demodulated reproduction data is accumulated in the first buffer memory 5A for one frame, it is sent to the ring buffer memory 6 and the error correction circuit 7, and the PI A series of error correction processing is performed, error-corrected data is written to the ring buffer memory 6, and when PI error correction is completed, PO data is read from the ring buffer memory 6 and written to the second buffer memory 5B.
EC from the second buffer memory 5B to the error correction circuit 7
C transfer (PO data transfer) is performed, PO error correction is performed by the error correction circuit 7, and the error-corrected data is written to the ring buffer memory 6. When the PI error correction is completed, the ECC transfer (PI2 data transfer) is performed from the ring buffer memory 6 to the error correction circuit 7, and at the same time, the data is written to the second buffer memory 5B, and the PI2 error correction is performed by the error correction circuit 7. Do
The error-corrected data is written to the ring buffer memory 6 via the descramble and error detection circuit 8.
Then, data corresponding to the output request from the host computer 14 is transferred (host transfer) from the ring buffer memory 6 to the host computer 14 via the ATAPI interface 15 at a required transfer rate. In this optical disc reproducing apparatus, the writing of data from the ring buffer memory 6 to the second buffer memory 5B and the error correction processing of the PI sequence in the error correction circuit 7 occur simultaneously, so that the data processing speed is reduced. It is possible to read the disk at double speed and transfer data at 16.6 Mbit / s by the ATAPI interface. This will be verified below.

The rate of demodulated data when the disc is reproduced at 1 × speed is 26.16 MB / s. ATAP
The transfer rate required by the I interface is 16.
6 MB / s.

The ring buffer memory 6 performs word access (16 bits), and sets the number of cycles of n-word page access to 3 + 2 × n cycles. Further, the second buffer memory 6B performs byte access (8 bits),
The number of cycles for n-byte page access is 3 + 2 × n cycles. Furthermore, the frequency of the master clock is 4
0 MHz.

As shown in FIG. 4, the number of bits of one sync frame is 1456 bits, which is 32 bits.
A bit sync pattern is added. Therefore, the total number of bits of one sync frame is 1456 + 32
= 1488 bits.

The rate of demodulated data when the disc is reproduced at 1 × speed is 26.16 Mbit / s. Therefore, the sync frame frequency is as follows: sync frame frequency = 26.16 MHz / (32 + 1456) = 26.16 MHz / 1488 = 17.58065 KHz.

The master clock is 40 MHz, and one cycle of the master clock is defined as one cycle. The sync frame frequency is 17.58065 KHz
And 2 sync frames are PI series (182 bytes)
Therefore, when one frame of the PI sequence is converted into the number of cycles, 2 × 40 MHz / 17.58
065 KHz = 4550 cycles. Therefore,
For one ECC block, ie, 208 frames, 455
0 cycles × 208 = 946400 cycles.

Here, as shown in FIG. 15, page access is made to the ring buffer memory 6 every 16 bytes / 19 cycles, and host transfer access and other accesses are performed alternately (ECC). If there is no access request other than the above, the ECC access can be repeated, but in that case, the end of the 16 cycles of the CC is waited.) The host transfer rate at this time is 16.84 MB.
/ S, which satisfies 16.6 MB / s.

The number of cycles required for writing demodulated data and reading and correcting PI data is 182/16 = 11.3 when 182 bytes of the PI sequence are page-accessed every 16 bytes / 19 cycles. Therefore, in one ECC block 208 frame, 12 × 19 × 208 = 47424 cycles (1). Also, since it is a 5-byte correction, (5 + 5) × 5 × 208 = 1040 cycles (2) is required.

Further, the number of cycles required for reading and correcting the PO data is 208/16 = 26 when 208 bytes of the PO-series frame are accessed every 16 bytes / 19 cycles. 19 × 172/2 + 15064 (#) = 57548 cycles (3) Also, since the correction is 16 bytes, (16 + 16) × 5 × 172 = 27520 cycles (4) is required. It should be noted that 15064 (#) takes into account the transfer other than the host in the ECC transfer (PO data transfer) cycle from the second buffer memory 5B.

The number of cycles required for reading the PI2 data is calculated excluding the 16 columns of PO parity data. When 182 bytes of the PI series are page-accessed every 16 bytes / 19 cycles, 182/16 = 11.
Since it is 3, in one ECC block 208 frames, 12 × 19 × (208−19) = 437764 cycles (5)

When writing EDC end data, only 192 frames of main data are calculated, and page access is performed every 16 bytes / 19 cycles.
Since 16 = 10.75, one ECC block 208
In the frame, 11 × 19 × 192 = 47424 cycles (6) are required.

The sum of (1) to (6) is 2266
This is 0 cycles.

Further, if a DRAM requires a refresh operation, and if a CAS before RAS refresh cycle is inserted approximately once every 16 μsec, 23660/16 = 1478.75 times in one ECC block period.
If one refresh cycle is 5 cycles, 1479 × 5 = 7395 cycles.

Therefore, the limit of the decoding processing speed when securing all host transfers is (946400 + 7)
395) × (19/38) / (226796 + 739)
5) = 2.02, and double speed becomes possible.

In the above example, a product code composed of a PI sequence and a PO sequence is used as the error correction code, but an error correction code having another configuration may be used. In this example, the PI sequence is decoded and P
After the decoding of the O sequence, the decoding of the PI sequence may be further performed, or the decoding of the PI sequence and the decoding of the P0 sequence may complete the error correction processing.

[0080]

According to the present invention, the demodulated reproduced data is written to the first buffer memory, and when one frame of data is accumulated in the first buffer memory, 1
The PI data for the frame is sent to the error correction circuit and written to the ring buffer memory, the error correction circuit performs error correction processing of the PI series, and the error-corrected data is written to the ring buffer memory.
When the error correction is completed, the PO data is sent from the ring buffer memory to the error correction circuit and written into the second buffer memory, and the error correction circuit performs a PO series error correction process, and the error-corrected data is stored in the ring buffer memory. Write. Further, when the PI error correction is completed, the PI2 data is sent from the ring buffer memory to the error correction circuit and the data is written to the second buffer memory, and the PI2 error correction is performed by the error correction circuit using the data stored in the second buffer memory. When the processing is completed and the PI2 error correction processing is completed, the data is transferred from the second buffer memory to the ring buffer memory, and the data is output from the ring buffer memory at a required transfer rate. As a result, writing of data from the ring buffer memory to the second buffer memory and error correction processing of the PI series in the error correction circuit occur simultaneously, so that the data processing speed is reduced, and, for example, the disk is read at double speed. , ATAPI interface can transfer data at 16.6 Mbit / s.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an optical disk reproducing apparatus to which the present invention has been applied.

FIG. 2 is a schematic diagram illustrating a data format of a DVD.

FIG. 3 is a schematic diagram illustrating a data format of a DVD.

FIG. 4 is a schematic diagram illustrating a data format of a DVD.

FIG. 5 is a timing chart of a data processing operation based on an ECC block timing in the optical disc reproducing apparatus.

FIG. 6 is a timing chart of a PI / PO error correction operation based on an ECC frame timing in the optical disc reproducing apparatus.

FIG. 7 is a timing chart of a PI / PI2 error correction processing operation based on an ECC frame timing in the optical disc reproducing apparatus.

FIG. 8 is a schematic diagram used for describing a ring buffer in the optical disk reproducing device.

FIG. 9 is a schematic diagram used for describing the ring buffer.

FIG. 10 is a schematic diagram used for describing the ring buffer.

FIG. 11 is a schematic diagram used for describing the ring buffer.

FIG. 12 is a block diagram showing a configuration example of an error correction circuit in the optical disc reproducing device.

FIG. 13 is a timing chart used for describing the error correction circuit.

FIG. 14 is a timing chart used for describing the error correction circuit.

FIG. 15 is a timing chart used for explaining the operation of the optical disc reproducing apparatus.

FIG. 16 is a schematic diagram used for describing a basic configuration of a ring buffer memory.

FIG. 17 is a block diagram used for explaining an example of a conventional disk reproducing apparatus.

FIG. 18 is a block diagram used for explaining an example of a conventional disk reproducing apparatus.

FIG. 19 is a block diagram used for explaining an example of a conventional disk reproducing apparatus.

FIG. 20 is a timing chart used to describe an example of a conventional disk reproducing apparatus.

FIG. 21 is a block diagram used for explaining another example of the conventional disk reproducing apparatus.

FIG. 22 is a block diagram used for explaining another example of the conventional disk reproducing apparatus.

FIG. 23 is a block diagram used for explaining another example of the conventional disk reproducing apparatus.

FIG. 24 is a block diagram used for explaining another example of the conventional disk reproducing apparatus.

FIG. 25 is a timing chart used for explaining another example of the conventional disk reproducing apparatus.

FIG. 26 is a block diagram used for explaining still another example of the conventional disk reproducing apparatus.

FIG. 27 is a block diagram used for explaining still another example of the conventional disk reproducing apparatus.

FIG. 28 is a block diagram used for explaining still another example of the conventional disk reproducing apparatus.

FIG. 29 is a block diagram used for explaining still another example of the conventional disk reproducing apparatus.

FIG. 30 is a timing chart used for explaining still another example of the conventional disk reproducing apparatus.

[Explanation of symbols]

1 optical disk, 5A first buffer memory, 5B
Second buffer memory, 6 Ring buffer memory, 7
Error correction circuit

Claims (3)

[Claims] A reproducing means for reproducing digital data from a recording medium; an error correcting means for performing an error correction process on the data reproduced by the reproducing means; A ring buffer memory for variable rate control output at
A first buffer memory that accumulates the frames and sends the error correction means and the ring buffer memory to the first buffer memory; A buffer memory; and control means for controlling the operation of the reproducing means and the ring buffer memory. When data of one frame is accumulated in the first buffer memory, data of one frame is stored in the first buffer memory. Is sent to the error correction means and written in the ring buffer memory, the first error correction is performed on the data written in the ring buffer memory by the error correction means, and the error-corrected data is written in the ring buffer memory When the error correction of the first series is completed, the ring back The second series of data is read out from the buffer memory and written to the second buffer memory, and the second series of data is sent from the second buffer memory to the error correction means. The second series of error correction is performed by the error correction means, the error-corrected data is written to the ring buffer memory, and when the PI error correction is completed, the first series of data is transferred from the ring buffer memory to the error correction means. The data is sent to the correction means and written in the second buffer memory, the data written in the second buffer memory is subjected to error correction by the error correction means, the error-corrected data is written to the ring buffer memory, and Error-corrected data from the ring buffer memory at the appropriate transfer speed Data reproduction apparatus and outputs a. 2. The first and second buffer memories,
2. The data reproducing apparatus according to claim 1, wherein the data reproducing apparatus has a storage capacity for two to three frames of the error correction block. 3. A first step of writing demodulated reproduced data to a first buffer memory, and, when data of one frame is accumulated in the first buffer memory, one frame of data from the first buffer memory. The data is sent to the error correction means and written to the ring buffer memory. The data written to the ring buffer memory is subjected to a first series of error correction by the error correction means, and the error-corrected data is written to the ring buffer memory. When the second step and the first series of error corrections are completed, the second series of data is read from the ring buffer memory and written into the second buffer memory, and the second series of data is read from the second buffer memory. To the error correction means, and corrects the error written to the ring buffer memory. A third step of performing the second series of error correction by the stage and writing the error-corrected data to the ring buffer memory; A fourth step of sending the data to the error correction means and writing the data to the second buffer memory; and performing error correction on the data written to the second buffer memory by the error correction means, and ringing the error-corrected data in a ring. A data reproducing method comprising: a fifth step of writing data in a buffer memory; and a sixth step of outputting error-corrected data from a ring buffer memory at a transfer rate according to an output request.