JPH10187647A - Method and device for data transmission - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make processors transmit data to each other while matching their data transmission and reception rates with each other by sending basic data indicating whether or not data is effective together with the transmitting data, and storing only effective data. SOLUTION: The reference data with which it can be recognized whether or not currently transmitted from a transmission-side processor is effective data is transmitted together with the transmit data. An effective data detection part 30 after detecting the effective data transmits the successive effective data directly to an FIFO 10. When discontinuous effective data is inputted, it is outputted in a different route after ineffective data is removed. An effective data combination part 40 after receiving the discontinuous effective data and matching the transmission length of the data with the format of the continuous data sends the data to the FIFO 10. The FIFO 10 transmits the data to a reception-side processor after storing the data according to specific data capacity so as to match the data transmission rate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission method and apparatus for use in computer communications and the like, and more particularly to reducing data area waste by removing invalid data while matching data transmission speeds. About technology.

[0002]

2. Description of the Related Art Generally, as shown in FIG. 2, a device for communicating between computer devices has a transmission speed matching between a first processor A on a transmitting side and a second processor B on a receiving side. Is provided with a data transmission rate matching unit C for calculating the data transmission speed. Although such a structure is also used for two-way data communication between processors, the example of FIG. 2 shows a concept for one-way communication. Data communication based on this concept is a technique used for achieving consistency when the data input / output speeds of the processors are different from each other.

[0003] It should be noted that the processors are not in an equal relationship,
It is a technique that is often used in subordinate relationships, such as data communications between a computer processor and a printer processor. The data transmission rate matching unit C shown in FIG. 2 is configured as shown in FIG. According to FIG. 3, the conventional data transmission rate matching unit C receives data to be transmitted from the transmitting processor A and stores the data according to a predetermined data capacity for data transmission rate matching. FIFO to send to receiving processor B
10 and a data amount detection unit 20 which detects whether or not the data of the FIFO 10 has reached the limit amount, and requests the transmitting processor to suspend the data transmission for a while when the limit amount is reached. It is provided with.

Next, the operation will be described. When data is transmitted from the first processor A on the transmitting side, it is received by the FIFO 10 and transmitted to the second processor B on the receiving side. At this time, if the speed at which data is received by the second processor B is lower than the speed at which data is transmitted from the first processor A,
Data that cannot be received by the second processor B is FIFO
Stored at 10.

As described above, the data stored in the FIFO 10 is variable depending on the data reception speed of the receiving processor B. However, when the data storage capacity of the FIFO 10 is exceeded, there is a possibility that the excess data overflows and is not transmitted. Occurs. At this time, the data amount detector 20
When it is detected that the data storage amount of the FO 10 has reached the limit, a stop signal is output to the first processor A on the transmitting side, and the data transmission is stopped for a while.

[0006]

However, in such a conventional data transmission apparatus, it is sufficient if the data transmitted from the first processor A on the transmission side is only normal valid data. In the case where unnecessary data is mixed after transmission as in the above, that is, when valid transmission data is discontinuous, the FI having a limited capacity is used.
The data storage capacity of the FO is substantially reduced.

[0007] Further, since the data amount detecting section 20 is operated more frequently, the data transmission speed is reduced, and the user may be dissatisfied with the data transmission speed between the processors. The present invention has been made in view of such a conventional problem, and a data transmission method and a data transmission method capable of transmitting data with consistency of data transmission / reception speed between processors by storing only valid data. It is intended to provide a device.

[0008]

According to a first aspect of the present invention, there is provided a data transmission method in which data is transmitted between processors with data transmission / reception speed being consistent. A first step of dividing the transmitted transmission data for each predetermined bit unit and transmitting reference data indicating whether the divided data is valid together with the transmission data, and receiving the transmission data and the reference data; A second step of determining whether or not data is valid based on the reference data for each section; and, when determining that the data is not valid, removing the data and storing only the valid data in the auxiliary storage means. A third step of storing the valid data stored in the auxiliary storage means when the valid data has a predetermined bit length, and a fourth step of storing the data in the main storage means. Data according to the transmission rate of the receiving processor, and to include a fifth step of transmitting to the receiving processor.

In the data transmission method according to the second aspect of the present invention, in the third step, when it is determined in the second step that valid data is continuously present for a predetermined bit length, the valid data having a predetermined bit length is transmitted. The method further includes a step of directly storing in the main storage means. According to a third aspect of the present invention, there is provided a data transmission apparatus which stores transmission data transmitted from a data transmitting processor which transmits data, and transmits the data in accordance with a data transmission speed of the data receiving processor which receives the data. Storage means, data amount detection means for detecting the amount of data stored in the main storage means, and when the data amount reaches a predetermined amount, outputs a signal to stop data transmission to the data transmission side processor, In the data transmission device comprising, valid data detection means for detecting valid data from the transmission data transmitted from the data transmitting processor, auxiliary storage means for storing the valid data,
The valid data detection means, when the transmission data is inputted and the valid data is continuously detected, the continuous valid data is directly transmitted to the main storage means, and when the valid data is not continuous, Only the valid data is output to the auxiliary storage means, and the auxiliary storage means is configured to transmit the valid data to the main storage means when the valid data has a predetermined data length.

In the data transmission apparatus according to a fourth aspect of the present invention, the data transmitting processor transmits reference data indicating whether or not the transmission data is valid, together with the transmission data, and the valid data detecting means includes: It is configured to detect valid transmission data based on the data.
In the data transmission apparatus according to a fifth aspect of the present invention, the data transmission-side processor classifies the transmission data for each predetermined bit and assigns reference data, and the valid data detection unit classifies the transmission data based on the reference data. It is configured to detect valid data for each data.

In the data transmission apparatus according to the present invention, the valid data detecting means may be configured such that when the bit value of the reference data is in a first logical state indicating that the data is not valid,
The data in the area corresponding to the bit value is recognized as invalid data, and the data in the area is removed. In the data transmission apparatus according to the invention of claim 7, the auxiliary storage means is a first-in first-out memory element of a predetermined size.

[0012]

FIG. 1 is a block diagram showing an embodiment of the present invention.
It will be described based on. FIG. 1 is a conceptual configuration diagram of the data transmission rate matching unit. According to FIG. 1, as a main storage means for receiving input of data to be transmitted from a processor on the transmission side, storing the data in accordance with a predetermined data capacity for data transmission speed matching, and transmitting the data to the reception side processor. F
The data amount detection means for detecting whether the data of the FIFO 10 has reached the limit amount and, when the data amount has reached the limit amount, requests the transmitting processor to suspend the data transmission for a while. After receiving the input of the data transmitted from the transmitting processor and detecting the valid data, the unit 20 transmits the continuous valid data directly to the FIFO 10 and, when the discontinuous valid data is input, based on the time point, After removing invalid data, the valid data detecting unit 30 serving as valid data detecting means for outputting the data on another path, and when the discontinuous valid data is output from the valid data detecting unit 30, the data is received and continued. After adjusting the transmission length of the data to the data format, the FIFO1
Valid data linking unit 4 as auxiliary storage means for transmitting the data to 0
0.

Next, the operation will be described. First, reference data is transmitted from the transmitting processor together with the transmission data so that the current transmission data can be recognized as valid data or invalid data, that is, data that is unnecessary after transmission. . That is, Table 1 below
As shown in (1), when the transmission data is, for example, 32-bit data, the data is divided into four areas of 8 bits each, and each area is recognized as to whether the corresponding data is valid data or invalid data. Each of the reference data that can be transmitted is assigned one bit, and the transmission data is transmitted.

[0014]

[Table 1]

Therefore, each of the reference data a, b, c, and d is one bit, and for example, the logic state value is "0".
Is recognized as valid data, and the case of "1" is recognized as invalid data. Therefore, when transmitting 32 bits of data at one time from the transmitting side to collectively transmit 32 bits of data, the transmitting side processor transmits 32 bits of transmission data and 4 bits of reference data, and the valid data detecting section 3 transmits the data.
When 0 is input, the continuity of the valid data is determined by detecting the logical state of the signal in response to the input of the 4-bit reference data. It is determined that the data is continuous valid data, and the data is directly transmitted to the FIFO 10.

In this case, as compared with the conventional operation for matching the data transmission rate, the operation is not different from the whole and becomes the same. At this time, the valid data detection unit 30 detects a discontinuous portion of the valid data during the operation of determining the continuity of the valid data by receiving the input of the 4-bit reference data, that is, “0010”. If it is determined that the data in the C area is invalid data in Table 1, the data in the A area, the B area, and the D area are transmitted to the valid data combining unit 40 after the data in the C area is removed. You.

In the valid data combining unit 40, this A area,
Data of the B area and the D area are stored. Thereafter, the valid data detection unit 30 outputs
Invalid data is continuously detected and removed,
All input data, even continuous valid data, is transmitted to the valid data combiner 40. by this,
In the valid data combiner 40, the data input from the valid data detector 30 is recombined 32 bits at a time,
It is transmitted to O10.

The operations of the valid data detecting unit 30 and the valid data combining unit 40 are summarized in Table 2 below.

[0019]

[Table 2]

Incidentally, a FIFO of a predetermined size can be used for the effective data combining section 40.

[0021]

As described above, according to the data transmission method of the first aspect, even if invalid data is generated, the limited data storage capacity of the main storage unit is not wasted. Therefore, effective use is possible.
According to the data transmission method of the second aspect, the transmission speed can be increased.

According to the data transmission apparatus of the third aspect, even if invalid data frequently occurs due to an error or the like occurring during data transmission, the limited data storage capacity of the main storage means is wasted. Because
Effective use is possible. According to the data transmission device of the fourth aspect, valid transmission data can be detected based on the reference data.

According to the data transmission apparatus of the present invention, it is possible to detect whether or not the transmission data is valid data for each predetermined section. According to the data transmission apparatus of the sixth aspect, invalid data can be removed. According to the data transmission apparatus of the present invention, valid data can be transmitted to the main storage unit in the order of input.

[Brief description of the drawings]

FIG. 1 is a conceptual configuration diagram of a data transmission rate matching unit according to the present invention.

FIG. 2 is a conceptual diagram of general unidirectional computer communication.

FIG. 3 is a conceptual configuration diagram of a conventional data transmission rate matching unit.

[Explanation of symbols]

 A, B Processor C Data transmission speed matching unit 10 FIFO 20 Data amount detection unit 30 Valid data detection unit 40 Valid data combining unit

Claims (7)

[Claims] In a data transmission method for transmitting data between processors while maintaining data transmission / reception speed consistency, transmission data transmitted from a data transmitting processor is divided into predetermined bit units, and the divided data is divided. A first step of transmitting reference data indicating whether the data is valid together with the transmission data, receiving the transmission data and the reference data, and determining whether the data is valid based on the reference data for each section A second step of determining that the data is not valid, removing the data when it is determined that the data is not valid, and storing only the valid data in the auxiliary storage means; A fourth step of storing the data in the main storage means when the length of the data becomes longer, and matching the data stored in the main storage means with the transmission speed of the receiving processor. Data transmission method, which comprises a fifth step of transmitting to Tsu support, the. 2. The method according to claim 2, wherein when the valid data is determined to be continuously present for a predetermined bit length in the second process,
2. The data transmission method according to claim 1, further comprising a step of directly storing valid data of a predetermined bit length in the main storage means. 3. Main storage means for storing transmission data transmitted from a data transmitting processor for transmitting data, and transmitting data in accordance with a data transmission speed of a data receiving processor for receiving data. A data amount detecting means for detecting an amount of data stored in the means, and outputting a signal for stopping data transmission to a data transmitting side processor when the data amount reaches a predetermined amount. A valid data detecting unit that detects valid data from transmission data transmitted from the data transmitting processor; and an auxiliary storage unit that stores the valid data. The valid data detecting unit inputs transmission data. When the valid data is continuously detected, the continuous valid data is directly transmitted to the main storage means. Data transmission means for outputting only valid data to the auxiliary storage means, wherein the auxiliary storage means is configured to transmit the valid data to the main storage means when the valid data has a predetermined data length. apparatus. 4. The data transmission side processor transmits reference data indicating whether or not the transmission data is valid together with the transmission data, and the valid data detection means detects valid transmission data based on the reference data. 4. The data transmission device according to claim 3, wherein the data transmission device is configured to perform the operation. 5. The data transmission-side processor classifies transmission data for each predetermined bit and assigns reference data, and the valid data detection means converts valid data for each data classified based on the reference data. 5. The data transmission device according to claim 4, wherein the data transmission device is configured to detect. 6. When the bit value of the reference data is in a first logical state indicating that the data is not valid, the valid data detecting means recognizes data in an area corresponding to the bit value as invalid data. The data transmission device according to claim 4, wherein data in a corresponding area is removed. 7. The memory according to claim 3, wherein said auxiliary storage means is a first-in first-out memory element of a predetermined size.
The data transmission device according to claim 6.