JPH10187595A - Bus bridge - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bus bridge by which bus efficiency can be improved. SOLUTION: When a read command is issued from a high-order bus, a bus acquire request/command issue part 1 outputs a bus acquire request signal to a low-order bus and when the right to use the low-order bus is acquired, the read command is issued and sent out to the low-order bus. Then, a V bit (ID registered) and an MY bit (read issued by itself) are written in a read ID register part 3. When any external agent acquire the data bus using right while the V bit and the MY bit are written in the read ID register part 3, a bus acquire request issue part 5 outputs the bus acquire request signal to a high- order bus. When coincidence is detected at a read ID check part 4, a data command issue part 7 fetches data outputted from the low-order bus and outputs them to the high-order bus. When non-coincidence is detected at the read ID check part 4 and the bus acquire request is outputted from a CPU, the bus bridge abandons the right to use the high-order bus.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus bridge, and more particularly, to a bus bridge corresponding to a split bus capable of issuing another command without waiting for data transmitted in response to a read request.

[0002]

2. Description of the Related Art Conventionally, in this type of bus bridge, when a read command is issued to an upper bus, a command bus acquisition request signal is issued to a lower bus to acquire a lower bus, and then a read request is issued. After issuing the read request, the right to use the lower bus is relinquished.
In this case, the bus bridge that has issued the read request registers the registration number of the read issued by itself in the holding unit.

When any of the external agents connected to the lower bus issues a data bus acquisition request signal to the lower bus to acquire the lower bus, the bus bridge acquires a read ID issued to the lower bus. Check whether it is a registered lead ID.

When the read ID issued to the lower bus matches the registered read ID, the bus bridge takes in data from the lower bus, and after completing preparations for transferring data to the upper bus, a bus acquisition request signal to the upper bus. Is output. This bus bridge is disclosed in Japanese Patent Application Laid-Open No. 4-3042.
No. 8 discloses this.

That is, as shown in FIG. 6, the bus bridge includes a bus acquisition request / command issuing unit 21, an upper bus arbiter 22, a read ID registration unit 23, a read ID check unit 24, a bus acquisition request Issuer 25;
Lower bus arbiter 26 and data / command issuing unit 27
It is composed of

As shown in FIG. 2, a system using this bus bridge includes bus bridges 13 and 14 and C bus bridges.
Bus bridges 13 and 14 connect between an upper bus 100 for connecting PUs (central processing units) 11 and 12 and a lower bus 200 for connecting bus bridges 13 and 14 and external agents 15 and 16. Connected.

The bus bridges 13 and 14 are connected to the upper bus 100
When a read command is issued, as shown in FIG.
The bus acquisition request / command issuing unit 21 issues a command bus acquisition request signal to the lower bus 200.

When the bus bridges 13 and 14 acquire the lower bus 200 by the command bus acquisition request signal, they issue a read request to the lower bus 200 and relinquish the right to use the lower bus 200 after issuing the read request. In this case, the bus bridges 13 and 14 register the read ID (registration number) issued by themselves in the read ID registration unit 23.

When any one of the external agents 15 and 16 connected to the lower bus 200 issues a data bus acquisition request signal to the lower bus 200 to acquire the lower bus 200, the bus bridges 13 and 14 thereafter thereafter. The read ID issued to the lower bus 200 is the read ID registration unit 2
3 is checked by the read ID check unit 24 to determine whether the read ID is registered.

The bus bridges 13 and 14 are connected to the lower bus 200
When the read ID that is issued to the read ID register 23 matches the read ID registered in the read ID registration unit 23, data is read from the lower bus 200, and after preparation for transferring data from the data / command issuing unit 27 to the upper bus 100 is completed, The bus acquisition request issuing unit 25 outputs a bus acquisition request signal to the bus 200.

Here, a bus acquisition request to the upper bus 100 is arbitrated by the upper bus arbiter 22 and the lower bus 20 is arbitrated.
The bus acquisition request for 0 is arbitrated by the lower bus arbiter 26.

[0012]

In the conventional bus bridge described above, when the bus bridge holds the read ID, one of the external agents connected to the lower bus issues a data bus acquisition request signal, and the arbitration is performed. Check the read ID issued after acquiring the data bus according to the read ID of the read issued by itself.
After confirming that the data is acquired, the data is ready to issue read data to the upper bus, and then a bus acquisition request is output to the upper bus, so the upper bus issues a read command and receives data. It will take some time.

Therefore, an object of the present invention is to solve the above-mentioned problems, to reduce the time from when a higher-level bus issues a read command to when data is received, and to improve bus efficiency. To provide a bus bridge.

[0014]

A bus bridge according to the present invention comprises: issuing means for issuing a command from a higher-level bus connecting to a higher-level device to a lower-level bus connecting to a plurality of lower-level devices; A bus bridge including upper bus arbitration means for arbitrating an acquisition request for an upper bus, and lower bus arbitration means for arbitrating the acquisition request for the lower bus, wherein the lower right bus arbitration means arbitration by the lower bus arbitration means. And holding means for holding information indicating that the command has been issued, and when any of the plurality of lower-level devices obtains the right to use the lower-level bus, Control means for controlling the issuing means so as to issue the acquisition request to a higher-order bus.

Another bus bridge according to the present invention is:
Issuing means for issuing a read command from an upper bus connecting to an upper device to a lower bus connecting to a plurality of lower devices; upper bus arbitrating means for arbitrating an acquisition request for the upper bus; A lower bus arbitration means for arbitrating an acquisition request for the lower bus, wherein the lower bus arbitration means obtains the right to use the lower bus by arbitration and issues the read command when the read command is issued. Holding means for holding a registration number, and when the read registration number is held in the holding means when one of the plurality of lower-level devices obtains the right to use the lower-level bus, Control means for controlling the issuing means so as to issue the acquisition request.

That is, in the case of a split bus read, the bus bridge of the present invention registers a read ID for the issued read. In the prior art, the information of each read ID includes whether the read ID is valid,
D has information about whether or not it is a lead issued by himself,
After confirming that the read ID issued on the lower bus is its own read ID, data is fetched and a bus acquisition request signal is issued to the upper bus after the data reply is ready.

On the other hand, in the bus bridge of the present invention, the read ID of the read request newly issued to the lower bus is
Data is issued from the lower bus when holding the read ID of the read issued by itself, and when the acquisition of the right to use the bus is determined, Before confirming the ID, a bus acquisition request signal is output to the upper bus.

In the processing after acquiring the right to use the upper bus, in the prior art, the bus bridge issues a bus acquisition request signal after data bus preparation is completed for the upper bus. After acquiring the usage right, the data may be normally replied.

On the other hand, in the bus bridge of the present invention, the bus acquisition signal is output before the preparation of the data reply to the upper bus is completed. If it is not the response of the issued read, or it is the response of the read issued by itself, a state where the data cannot be replied due to an error or the like may occur.

Therefore, the bus bridge of the present invention retains the right to use the bus until a normal response is returned unless the CPU connected to the upper bus has issued a bus acquisition request. However, the right to use the bus is relinquished when the CPU connected to the higher-level bus issues or has issued the bus acquisition request, and
Give the right to use the bus to.

Therefore, in the bus bridge corresponding to the split bus, when the lower bridge issues the data request and acquires the data bus while the bus bridge holds the read ID issued by itself,
By issuing the bus acquisition request signal to the upper bus without waiting for the issuance of data, it is possible to reduce the time from the issuance of the read request to the return of data, thereby improving the bus efficiency.

[0022]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. Referring to FIG. 1, a bus bridge according to an embodiment of the present invention includes a bus acquisition request / command issuing unit 1, an upper bus arbiter 2, and a read ID registration unit 3.
Read ID check unit 4 and bus acquisition request issuing unit 5
, Lower bus arbiter 6, and data / command issuing unit 7
And an AND circuit 8.

The bus acquisition request / command issuing unit 1 receives a command from an upper bus (not shown) and issues a bus acquisition request signal / command to a lower bus (not shown). The upper bus arbiter 2 arbitrates a bus acquisition request for the upper bus.

The read ID registration unit 3 stores the read ID registration information, and the read ID check unit 4 checks the read ID registered in the read ID registration unit 3 and the read ID issued by the lower bus. AND circuit 8 has read ID
An AND operation is performed on the read IDV bit (ID registration) and the MY bit (read issued by itself) of the registration unit 3, and the operation result is sent to the bus acquisition request issuing unit 5.

The bus acquisition request issuing unit 5 issues a bus acquisition request signal to the upper bus, and the lower bus arbiter 6 arbitrates a bus acquisition request for the lower bus. The data command issuing unit 7 issues a data command from the lower bus to the upper bus.

FIG. 2 is a block diagram showing a system configuration according to an embodiment of the present invention. In the figure, CPUs (Central Processing Units) 11 and 12 are connected to bus bridges 13 and 14 via an upper bus 100, and the bus bridges 13 and 14 are connected to external agents 15 and 16 via a lower bus 200. . Each of the bus bridges 13 and 14 is shown in FIG.
The configuration is as shown in FIG.

FIG. 3 is a timing chart showing the operation of one embodiment of the present invention. FIG. 3A shows the operation when the read IDs match, and FIG. 3B shows the operation when the read IDs do not match.

FIG. 4 is a diagram showing a format of the upper bus 100 of FIG. 2, and FIG. 5 is a diagram showing a bus cycle of the lower bus 200 of FIG. The operation of the embodiment of the present invention will be described with reference to FIGS.

Normally, the bus master of the upper bus 100
PU11,12, and bus bridges 13,14
Asserts a bus acquisition request signal when it is desired to use the upper bus 100. When the CPUs 11 and 12 can release the upper bus 100, the CPUs 11 and 12
Asserts the bus release signal to release the upper bus 100.

Thereafter, the bus bridges 13 and 14 become bus masters and output commands and data to the upper bus 100. When the output is completed, the bus bridge 13,
14 asserts a bus release signal and sets the upper bus 100
To release.

The lower bus 200 is one cycle of four cycles, and cycle 1 is a data bus or command bus acquisition request cycle. The external agent 15, which wishes to issue a command or read ID data to the lower bus 100,
16 outputs a signal. Cycle 2 is an arbitration cycle for determining an agent to acquire a bus.

Cycle 3 is a cycle in which the external agents 15 and 16 that have acquired the bus issue a command or a read ID. Cycle 4 is external agent 15,
This is a cycle for decoding the command or read ID issued from No. 16 and registering the read ID or checking the read ID. In the case of acquiring the data bus, data is issued on the data bus in the cycle after the issuance of the read ID.

From the upper bus 100 to the bus bridges 13, 1
4 (read command in FIG. 3), the bus bridges 13 and 14 send the read command to the lower bus 2 by the bus acquisition request / command issuing unit 1.
Convert to 00 format. Thereafter, the bus bridges 13 and 14 output a bus acquisition request signal from the bus acquisition request / command issuing unit 1 to the lower bus 200 in cycle 1 of the lower bus 200 (read request in FIG. 3).

The bus bridges 13 and 14 are connected to the lower bus 200
In the cycle 2 of the lower bus 2
When the right to use is determined, the read command is issued in cycle 3 of the lower bus 200, and the read IDV bit (ID registration) and M
Write Y bit (read issued by yourself).

When the V bit and the MY bit are written in the read ID registration section 3, a data bus acquisition request signal is issued from one of the external agents 15 and 16 in cycle 1 of the lower bus 200, and When the acquisition of the right to use the data bus is determined for the external agents 15 and 16 that have issued the data bus acquisition request signal in cycle 2 of 200 (data request of the lower bus 200 in FIG. 3), the bus bridges 13 and 14 change the buses Acquisition request issuing part 5
Outputs a bus acquisition request signal to the upper bus 100 (data request of the upper bus 200 in FIG. 3).

The bus bridges 13 and 14 are connected to the lower bus 200
The read ID issued in the cycle 3 and the read ID held in the read ID registration unit 3 are checked by the read ID check unit 4, and when the read IDs match, the data output from the lower bus 200 is checked. The data and command issuance unit 7 fetches the data, and the upper bus arbiter 2 determines that the right to use the upper bus 100 is acquired.
Is output to the upper bus 100 [FIG. 3 (a)
Data output].

On the other hand, when the read ID issued by the read ID check unit 4 does not match the read ID issued in the cycle 3 of the lower bus 200 with the read ID held in the read ID registration unit 3, the bus bridge 13, 14 normally waits for a normal data reply without releasing the bus, but upon receiving a bus acquisition request signal from the CPUs 11 and 12, asserts a bus release and transfers the right to use the upper bus 100 to the CPUs 11 and 12 [ Opening the bus in FIG. 3 (b)].

As described above, the split bus (not shown)
In the bus bridges 13 and 14 corresponding to
When the lower bus 200 issues a data request and acquires the data bus while the D registration unit 3 holds the read ID issued by itself, the lower bus 200 does not wait for the issuance of the read ID from the lower bus 200 and waits for the issuance of the read ID. By issuing the bus acquisition request signal to the bus 100, the time from when the upper bus 100 issues a read command to when data is received can be reduced, and the bus efficiency can be improved.

[0039]

As described above, according to the present invention, issuing means for issuing a command from an upper-level bus connecting to a higher-level device to a lower-level bus connecting to a plurality of lower-level devices; In a bus bridge including upper bus arbitration means for arbitrating an acquisition request for a bus and lower bus arbitration means for arbitrating an acquisition request for a lower bus, a command is issued after the right to use the lower bus is acquired by arbitration by the lower bus arbitration means. Is held, and when one of the plurality of lower-level devices obtains the right to use the lower-level bus, control is performed to issue an acquisition request to the upper-level bus according to the held content. Thus, the time from when the upper bus issues the read command to when the data is received can be shortened, and the bus efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a system configuration according to an embodiment of the present invention.

FIG. 3A shows a read ID according to an embodiment of the present invention;
FIG. 7B is a diagram showing an operation when the read IDs match, and FIG. 7B is a diagram showing an operation when the read IDs do not match in one embodiment of the present invention.

FIG. 4 is a diagram showing a format of an upper bus of FIG. 2;

FIG. 5 is a diagram showing a bus cycle of a lower bus in FIG. 2;

FIG. 6 is a block diagram showing a configuration of a conventional example.

FIG. 7 is a timing chart showing the operation of the conventional example.

[Explanation of symbols]

 1 Bus Acquisition Request / Command Issuing Unit 2 Upper Bus Arbiter 3 Read ID Register 4 Read ID Checking Unit 5 Bus Acquisition Request Issuing Unit 6 Lower Bus Arbiter 7 Data / Command Issuing Unit 8 AND Circuit 11, 12 CPU (Central Processing Unit) 13, 14 Bus bridge 15, 16 External agent 100 Upper bus 200 Lower bus

Claims (5)

[Claims] An issuing means for issuing a command from an upper bus connecting to an upper device to a lower bus connecting to a plurality of lower devices, and an upper bus arbitrating to arbitrate an acquisition request for the upper bus. Means and a lower bus arbitration means for arbitrating an acquisition request for the lower bus, wherein the lower bus arbitration means obtains the right to use the lower bus by arbitration and issues the command. Holding means for holding the indicated information, and issuing the acquisition request to the upper bus in accordance with the holding content of the holding means when any of the plurality of lower devices has obtained the right to use the lower bus. And a control means for controlling the issuing means. And means for relinquishing the right to use the upper bus obtained under the control of the control means when a lower device other than the lower device corresponding to the command has obtained the right to use the lower bus. The bus bridge according to claim 1, wherein 3. The bus bridge according to claim 1, wherein the command is a read request to the lower-level device. 4. An issuing means for issuing a read command from an upper bus connecting to an upper device to a lower bus connecting to a plurality of lower devices, and an upper bus arbitrating an acquisition request for the upper bus. A bus bridge including arbitration means and lower bus arbitration means for arbitrating an acquisition request for the lower bus, wherein the read command is issued by acquiring the right to use the lower bus by arbitration by the lower bus arbitration means. Holding means for holding the read registration number obtained at the time, and when the read registration number is held in the holding means when any of the plurality of lower-level devices has acquired the right to use the lower-order bus, Control means for controlling the issuing means so as to issue the acquisition request to a higher-order bus. 5. A device for relinquishing the right to use the upper bus acquired under control of the control means when a lower device other than the lower device corresponding to the read command acquires the right to use the lower bus. The bus bridge according to claim 4, characterized in that: