JPH10187442A - Device and method for prefetching instruction - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a prefetch instruction for reducing delay caused by a branch predictive error by continuously prefetching a condition branching instruction according to conditions when these conditions are fixed at the time point when the instruction is prefetched. SOLUTION: A 1st decode part 101 discriminates whether a processed instruction S112 is the condition branching instruction or not and whether the instruction is a condition generating instruction for fixing branching conditions or not, and a condition fix signal generating means 120 outputs a condition fix signal A118 to a condition fixture discriminating part 103 by comparing the address of condition generating instruction with contents of the program counter. Corresponding to this signal, the condition fixture discriminating part 103 outputs prefetch address information S114 for address generation to a prefetch address generating part 100 while using a condition code S119.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an instruction prefetch apparatus and an instruction prefetch method, and more particularly, to an instruction prefetch apparatus and an instruction prefetch method capable of efficiently executing pipeline processing in a processor.

[0002]

2. Description of the Related Art At present, most computers store programs as well as data in a storage device.
A Neumann-type architecture that reads and executes this is adopted. In general, a Neumann-type computer mainly includes a computer having a processor such as a CPU for controlling the execution of a program and a main memory for temporarily storing a program and data, and is an I / O for performing input / output with a user or the outside. (I / O device) and a computer system having an auxiliary storage device (secondary storage device) for storing programs and data for a long period of time.

In execution of a program under the control of a processor, an instruction of a program stored in a main memory is read, and an instruction process for sending a control signal to each part of a computer is performed based on the content of the instruction. The processor includes registers such as a program counter for specifying a storage location of an instruction to be executed in a main memory and an instruction register for storing the instruction.

FIG. 6A is a diagram for explaining a control operation in instruction processing under the control of a processor. First, in the instruction fetch process, the next instruction to be executed is read by referring to the program counter.
In the next instruction decoding process, the type of the read instruction is determined, and the instruction is interpreted. In the subsequent instruction execution processing, processing such as data reading and arithmetic processing is executed according to the instruction. Thereafter, in a result storing process, a result obtained by executing the instruction is stored. As shown
Each process is performed from timing CLn to timing CLn + 3 at each timing corresponding to a machine cycle.

In general, a program is executed by sequentially executing a plurality of instructions. FIG. 1B shows a case where an instruction A and an instruction B are sequentially executed. In the case shown in FIG. 2B, first, in the instruction fetch processing, the instruction A is read by referring to the program counter,
The content indicated by the instruction A is interpreted by the instruction decoding process, the process according to the specified content is performed in the instruction execution process, and the result obtained by the instruction execution is stored appropriately in the result storing process. At the next timing, the instruction fetch processing for the instruction B is executed to read the instruction B, and the instructions are sequentially processed in this way. If the processing of the instruction A is performed from the timing CLn to the timing CLn + 3, the execution of the instruction B is performed from the timing CLn + 4 as in FIG.

FIG. 1C is a diagram for explaining a pipeline process for improving the efficiency and speed of the process. Here, four processes of “instruction fetch”, “instruction decode”, “instruction execution”, and “result storage” can be performed in an overlapping manner as pipeline processing, that is, four control operations can be performed in parallel. It is assumed that it can be executed. At the timing CL1,
The instruction fetch processing of the instruction A is performed. Next timing C
In L2, a decoding process for the instruction A and a fetch process for the instruction B are performed. At the next timing CL3, execution processing for instruction A, decoding processing for instruction B, and fetch processing for instruction C are performed. As described above, by executing the pipeline processing, it is possible to process a number of instructions corresponding to the number of pipeline processes that can be performed in parallel, thereby speeding up the processing.

Here, if the instructions A to D are simply instructions to be sequentially executed, by processing the instructions in the order described in the program, ideal pipeline processing can be performed as shown in the figure. But in the program,
The repetition processing and the branch / selection processing are frequently used, and a plurality of instructions are not always processed simply in the order of description. Further, there is a case where the result of the execution processing of the previous instruction is used to process the subsequent instruction, or the branch / selection is performed, so that the pipeline processing along the flow of the program can be efficiently performed. It is necessary for conversion.

Hereinafter, a technique of instruction prefetch with prediction processing in the prior art will be described. Conventionally, in an instruction fetch process in a pipeline process, an instruction fetch process is performed by predicting a next instruction before an address of an instruction to be executed next is finally determined. Such an instruction fetch process by prefetching is called an instruction prefetch process. Hereinafter, an instruction prefetch device according to the related art, which executes an instruction prefetch process with a prediction process in a processor, will be described.

FIG. 7 is a diagram showing a configuration of a conventional prefetch device, FIG. 8 is a diagram showing a part of a program including an instruction to be subjected to prefetch processing, and FIG.
FIG. 4 is a timing chart showing a schematic operation when processing is performed by a conventional prefetch device. As shown in FIG. 7, a conventional instruction prefetch device includes a prefetch address generation unit 300, a first decoding unit 303,
The configuration includes a branch prediction unit 304, an instruction buffer 305, a second decoding unit 306, an operation execution unit 307, and a condition code holding unit 308.

The prefetch address generation unit 300 generates an address to be prefetched next based on the prediction of the branch prediction unit 304 and the condition code, and outputs a prefetch address signal S301. First decoding unit 30
3 performs a decoding process on the prefetched instruction S302 to acquire the instruction, and stores the instruction in an instruction buffer 3 described later.
This is output to 05. Also, the first decoding unit 3
03 determines the type of the prefetched instruction S302 based on the result of the decoding process, and when the instruction S302 is a conditional branch instruction, sends a signal indicating the instruction to the branch prediction unit 304 described later and the prefetch instruction Output to the address generation unit 300. The branch prediction unit 304 predicts how the branch of the processing procedure is performed in order to prefetch the instruction following the conditional branch instruction, and outputs the prediction result to the prefetch address generation unit 300.
As a prediction method, a method of determining a branch direction in advance based on the probability of branching, or a method of storing a branch direction in the same conditional branch in the past and determining the branch direction according to a history of the stored branch direction is used. Etc. can be used. The instruction buffer 305 temporarily stores the instruction acquired by the decoding processing of the first decoding unit 303 for the subsequent processing. The second decoding unit 306 fetches instructions temporarily stored from the instruction buffer 305, sequentially decodes the instructions, and controls an arithmetic process in an arithmetic execution unit, which will be described later, according to the obtained result. Calculation execution unit 3
07 executes an operation under the control of the second decoding unit 306, and if there is a change in a condition code held by a condition code holding unit 308, which will be described later, in accordance with the result of the operation, the condition code holding unit 308 A signal indicating the result is output. The condition code holding unit 308 includes an operation execution unit 307
Holds the condition code obtained based on the calculation processing result input from.

The operation of the conventional instruction prefetch device having the above-mentioned configuration is schematically described below. At a certain timing, the prefetch address generation unit 3
At 00, the address of the next instruction to be fetched is generated and output as the prefetch address signal S301. In the processor using the instruction prefetch device, an instruction is fetched using the prefetch address signal S301 and input to the instruction prefetch device. At the next timing, the prefetched instruction is input to the first decoding unit 303 and decoded.

The first decoding unit 303 determines whether the processed instruction is a conditional branch instruction. If the instruction is a conditional branch instruction, the prefetch address generation unit 300
To the branch prediction unit 304. In both cases where the instruction is a conditional branch instruction and when it is not, the processed instruction is stored in the instruction buffer 305.
Output to

The instruction temporarily stored in the instruction buffer 305 is thereafter fetched by the second decoding unit 306 and subjected to decoding processing, whereby the contents of the instruction are interpreted. The second decoding unit 306 outputs a signal indicating the content of the acquired instruction to the arithmetic execution unit 307, and the arithmetic execution unit 307 performs arithmetic processing according to the content of the instruction based on the input signal. . The result of the arithmetic processing is processed by the processor including the instruction prefetch device, and when the result of the arithmetic processing affects the condition code, the result is output to the condition code holding unit 308 and held. .

On the other hand, when a signal indicating that the instruction is a conditional branch instruction is input from the first decoding unit, the branch prediction unit 304 performs a prediction process according to a set method, and prefetches a signal indicating a prediction result. Output to the address generation unit 300. The prefetch address generation unit 300 generates an address of an instruction to be prefetched next. Here, the prefetch address generation unit 300
If a signal indicating that the instruction is a conditional branch instruction has not been input from the decoding unit 303, the address of the next instruction to be prefetched is referred to after referring to the condition code held in the condition code holding unit 308. Generated and output as a prefetch address signal S301. On the other hand, if a signal indicating that the instruction is a conditional branch instruction is input from the first decoding unit 303, the next prefetch is performed based on the signal indicating the prediction input from the branch prediction unit 304. The address of the power instruction is generated, and this is output as a prefetch address signal S301.

Here, the case where the program shown in FIG. 8 is processed in accordance with the timing chart of FIG. 9 will be described. The program shows the following processing procedure. In the figure, an instruction 400 is an addition instruction, performs an addition process on data stored in registers D0 and D1, and outputs the result to a register D2.
Is stored. In this program, according to the operation result of executing the instruction 400,
The branch in the instruction 401 is to be determined. In other words, the condition code used by the instruction 401, which is a conditional branch instruction, to determine a branch changes according to the execution result of the instruction 400. Here, it is assumed that if the result is 0, the zero flag of the condition code is set. The instruction 401 is a conditional branch instruction, and the processing procedure is branched by selecting the next instruction to be executed according to the zero flag of the condition code. Here, if the zero flag is not set, the next instruction to be executed is the instruction 403. If the zero flag is set, the next instruction to be executed is the instruction 402.

Next, the operation of the conventional instruction prefetch device when the processor using the prefetch device executes the program shown in FIG. 8 will be described with reference to the timing chart of FIG. At the timing t1 shown in the chart of FIG. 9, the address of the instruction 400 is generated by the prefetch address generation unit 300, and the prefetch address signal S301
Is output as The processor using the instruction prefetch device fetches the instruction 400 using the prefetch address signal S301 and inputs the instruction 400 to the instruction prefetch device. At the next timing t2,
The prefetched instruction 400 is transmitted to the first decoding unit 30
3 and decoded.

Since instruction 400 is not a conditional branch instruction,
The instruction 400 is output to the instruction buffer 305 without outputting a signal indicating that the instruction is a conditional branch instruction. The second decoding unit 306 outputs the instruction 40 from the instruction buffer 305.
0 and decode processing, the instruction 40
It interprets that 0 is an addition instruction, and transmits the result of the decoding process to the arithmetic execution unit 307 by signal output. The arithmetic execution unit 307 executes an addition process indicated by the instruction 400,
As described above, since the result of the addition processing of the instruction 400 can affect the condition code, the result of the addition processing is output to the condition code holding unit 308, and the condition code holding unit 308 is changed. Holds condition codes. As described above, if the addition result is 0, the zero flag of the condition code is set. Here, it is assumed that the operation result is not 0 and the zero flag is not set. At timing t3 in FIG. 9, the condition flag for determining the conditional branch in the instruction 401 is determined.

Thereafter, at timing t3, instruction 4
An address of 01 is generated, and an instruction 401, which is a conditional branch instruction, is fetched. The instruction 401 is input to the prefetch device at a timing t4, and is decoded by the first decoding unit 303. Since the instruction 401 is a conditional branch instruction, a signal indicating the instruction is output from the first decoding unit 303 to the prefetch address generation unit 300 and the branch prediction unit 304.

The branch prediction unit 304 to which the signal is input performs prediction, and outputs a signal indicating the result to the prefetch address generation unit 300. Here, the branch prediction unit 304
Is set so as to predict “the instruction described next in the program”. Therefore, a signal indicating the “next instruction” is output from the branch prediction unit 304 to the prefetch address generation unit 300. At timing t5 in FIG.
00 generates the address of the instruction 402 that is the “next instruction” of the conditional branch instruction 401 and outputs a prefetch address signal S301 indicating the “instruction 402”. In the processor, the instruction 402 is prefetched, and the instruction 402 is input to the first decoding unit 303 at timing t4 in FIG.

On the other hand, the conditional branch of the instruction 401 is determined using the condition flag determined at the timing t3. Since the zero flag is not set by the above setting, the next instruction to be executed is the instruction 403.
This corresponds to the determination of the branch destination address at the timing t6 in FIG. At this stage, the address of the instruction to be fetched next is determined. In this example, the original address (the address of the instruction 403) and the address generated by the prefetch address generation unit 300 at the timing t5. (The address of the instruction 402) does not match, that is, a branch prediction error has occurred, so that at the next timing t7, the prefetch of the next instruction is started again.

[0021]

In the instruction prefetch device according to the above-mentioned conventional technique, when there is a conditional branch instruction, the subsequent instruction is prefetched exclusively based on the prediction of the branch prediction unit 304. It shall be. Then, as shown in FIG. 9, even when the execution of the instruction 400 has been completed and the condition code has been determined (timing t3) at the time when the conditional branch instruction 401 is prefetched, the result is utilized. The instruction to be prefetched next cannot be determined. Therefore, when the prediction is correct, smooth pipeline processing is performed, and the processing efficiency is high. However, when the prediction is incorrect, the already fetched instruction is canceled to correct the correct instruction. There is a problem that a delay occurs due to fetching. Also, instruction 40 in this example
The prefetch of No. 2 is a useless operation, and the processor resources including the prefetch device have not been utilized.

The present invention has been made in view of such a problem, and when a conditional branch instruction is prefetched, if the condition is determined, the instruction is prefetched in accordance with the determined condition, whereby It is an object of the present invention to provide an instruction prefetch device capable of performing efficient processing utilizing device resources while reducing delay due to a branch prediction error.

[0023]

According to a first aspect of the present invention, there is provided an instruction prefetch device for prefetching from a storage device for storing the instruction in a computer for executing the instruction. It is determined whether the prefetched instruction is a branch instruction for instructing a branch, and if the instruction is a branch instruction, branch determination means for outputting a branch signal; and It is determined whether or not a condition for determining a branch in the branch instruction is determined. If the condition is determined, the determined condition information corresponding to the determined condition is output to a prefetch address generation unit described later. When the fixed condition information is input from the fixed condition information generating means and the fixed condition information generating means, the address to be prefetched is set based on the fixed condition information. Are those in which a prefetch address generating means for generating for, when prefetching the instruction following the branch, if the condition is identified,
An address of an instruction corresponding to the determined condition is generated.

According to a second aspect of the present invention, in the instruction prefetch apparatus according to the first aspect, the fixed condition information generating means determines whether a condition for determining a branch in the branch instruction is fixed. A condition determination signal generating means for outputting a condition determination signal when the condition is determined, and obtaining the determined condition when the condition determination signal is output, and obtaining the determination condition based on the obtained condition. Condition determination determining means for generating information, and whether or not the condition is determined, is transmitted in a condition determination signal,
If the conditions are determined, the conditions are used.

According to a third aspect of the present invention, there is provided the instruction prefetch apparatus according to the second aspect, wherein the condition determination signal generation means includes a first instruction address holding means for holding an address output from the branch determination means. A second instruction address holding unit that holds the address of the instruction that is being executed at that time, the first instruction address holding unit, and a comparison process of the address held by the second instruction address holding unit. And comparing means for outputting the condition determination signal to the condition determination determination means when it is determined that they match in the comparison, and determining whether or not the condition has been determined, Is executed by comparing the address of the instruction to determine the address with the address of the instruction being executed, and determines whether the condition is determined.

According to a fourth aspect of the present invention, in the instruction prefetch apparatus according to the third aspect, the branch determination means determines whether the prefetched instruction is a condition generation instruction. If there is, the address of the condition generating instruction is output to the first instruction address holding means, and
And outputs, as the output branch signal, information indicating a branch condition in the branch instruction to the condition determination determining means, and indicates a branch destination address in the branch instruction. The information is output to the prefetch address generation means, and a determination process for a condition generation instruction is executed, and by holding the address, a determination on the condition determination by address comparison is executed.

According to a fifth aspect of the present invention, in the instruction prefetch device according to the fourth aspect, when the condition determination signal is inputted, the condition determination determining means receives the next address of the branch instruction or the branch instruction. It outputs condition determination information indicating that the destination address should be used to the prefetch address generation means, and generates an address of an instruction corresponding to the determined condition.

According to a sixth aspect of the present invention, in the instruction prefetch apparatus according to the first aspect of the present invention, the fixed condition information generating means is a condition generating instruction for determining the condition for determining the branch by the prefetched instruction. It is determined whether or not the instruction is a condition generation instruction. If the instruction is a condition generation instruction, an operation process is executed in accordance with the condition generation instruction. Execute with the processing.

According to a seventh aspect of the present invention, in the instruction prefetch apparatus according to the sixth aspect, the condition generating instruction includes information indicating that the instruction is a condition generating instruction. The associated instruction is analyzed.

According to another aspect of the present invention, there is provided an instruction prefetch method for prefetching from a storage device storing the instruction, wherein the prefetched instruction issues a branch. It is determined whether or not the instruction is a branch instruction.
A branch determining step of outputting a branch signal; and determining whether or not a condition for determining a branch in the branch instruction has been determined when the branch signal has been output. And a fixed condition information generating step of outputting the fixed condition information corresponding to the fixed condition information to be used in a prefetch address generating step to be described later. When the fixed condition information is output in the fixed condition information generating step, the fixed condition information is output. And a prefetch address generation step of generating an address to be prefetched based on the prefetch instruction. In the prefetch of an instruction following the branch instruction, if the condition is determined,
An address of an instruction corresponding to the determined condition is generated.

According to a ninth aspect of the present invention, in the method of the eighth aspect, the determining condition information generating step determines whether a condition for determining a branch in the branch instruction is determined. A step of generating a condition determination signal for outputting a condition determination signal when the condition has been determined; and obtaining the determined condition when the condition determination signal has been output, and determining the determination condition based on the obtained condition. And a condition determination step of generating information, wherein whether or not the condition is determined is transmitted in a condition determination signal.

According to a tenth aspect of the present invention, in the method of the eighth aspect, in the determining condition information generating step, the prefetched instruction is a condition generating instruction for determining a condition for determining the branch. It is determined whether or not the instruction is a condition generation instruction. If the instruction is a condition generation instruction, an operation process is executed in accordance with the condition generation instruction. Execute with the processing.

An instruction prefetch method according to claim 11 is the method according to claim 10, wherein the condition generation instruction includes information indicating that the instruction is a condition generation instruction. The associated instruction is analyzed.

[0034]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. The instruction prefetch device according to the first embodiment of the present invention prefetches an instruction corresponding to a branch condition when the condition is determined using a condition determination signal indicating whether or not the branch condition is determined. is there. FIG. 1 is a block diagram showing a configuration of the instruction prefetch device according to the first embodiment. As shown in FIG.
An instruction prefetching apparatus includes a prefetch address generation unit 100, a first decoding unit 101, a condition generation instruction address holding unit 102, a condition determination determining unit 103, an instruction buffer 104, a second decoding unit 105, a condition code holding unit 106, an arithmetic execution Unit 107, program counter 10
8 and a comparator 109.

The prefetch address generating section 100 generates an address to be prefetched next using the prefetch address information S114 output from the condition determination determining section 103, and generates a prefetch address signal S110 which is a device output of the instruction prefetch device. Output. The first decoding unit 101 performs a decoding process on the prefetched instruction S112 and obtains information S indicating the content of the instruction.
116, and outputs it to the instruction buffer 104 described later.

The first decoding unit 101 determines whether or not the instruction is a branch instruction. If the instruction is a branch instruction, the first decode unit 101 functions as a branch determination unit that outputs a branch signal. Is a branch instruction, the signal S1 indicating the branch destination address in the conditional branch instruction
11 and a signal S1 indicating a branch condition in the branch instruction.
15 is output. The signals S111 and S115 are
It is also handled as a branch signal indicating that the instruction is a branch instruction. Further, the first decoding unit 101 determines whether the instruction is an instruction for changing a condition code (for example, a zero flag), that is, a condition generation instruction. Condition generation instruction S1
Twelve instruction addresses S113 are output to the condition generation instruction address holding unit 102 described later, and an undetermined signal S115 is output to the condition determination determining unit 103.

The condition determination unit 103 includes a signal S115 indicating a branch condition input from the first decoding unit 101,
Condition code S11 obtained from condition code holding section 106
9 to generate prefetch address information to be output to the prefetch address generation unit 100.

The instruction buffer 104 includes the first decoding unit 1
The signal S116 indicating the content of the instruction acquired by the decoding process 01 is temporarily stored for the subsequent processing.
The second decoding unit 105 outputs the temporarily stored signal S116
From the instruction buffer 104, sequentially decodes them, and outputs a signal for controlling arithmetic processing in an arithmetic execution unit, which will be described later, according to the obtained result. The condition code holding unit 106 holds a condition code such as a branch condition used for a determination in a process involving a determination such as a conditional branch process. The operation execution unit 107 is provided in the second decoding unit 10
5 in accordance with a control signal inputted from the control signal input unit 5 and a condition code holding unit 106 to be described later according to a result of the calculation.
If there is a change in the condition code stored in the condition code, a signal indicating the result is output to the condition code holding unit 106.

The condition generation instruction address holding section 102 functions as a first instruction address holding means for holding the address of the condition generation instruction, and stores the instruction address S11.
Hold 3. The program counter 108 is a register that holds the address of the instruction being executed in the processor using the instruction prefetch device, and functions as a second instruction address holding unit that holds the instruction address executed by the operation execution unit 107. . Comparator 10
9 compares the instruction address S117 acquired from the condition generation instruction address holding unit 102 with the address held in the program counter 108, and outputs a signal indicating a match if they match. The condition generation instruction address holding unit 102, the program counter 108, and the comparator 109 determine whether or not the condition for determining the branch in the branch instruction is determined. If the condition is determined, the condition generation signal S118 is output. Condition determining signal generating means 12
Functions as 0.

Further, although not shown in FIG. 1, the instruction prefetch device according to the first embodiment includes a branch prediction unit similar to the device according to the prior art, and the condition determination signal S118 determines the condition determination. If the address is not input to the unit 103, the branch prediction is performed using the branch prediction means, and the address is stored in the prefetch address
0 is input.

The operation of the thus configured instruction prefetch device according to the first embodiment will be outlined below. At a certain timing, the prefetch address generation unit 100 generates an address of an instruction to be fetched next, and generates a prefetch address signal S11.
Output as 0. In the processor using the instruction prefetch device, an instruction is fetched using the prefetch address signal S110, and the instruction S1
12 is input to the instruction prefetch device. At the next timing, the prefetched instruction S112
The data is input to the decoding unit 101 and is decoded.

In the first decoding unit 101, the instruction S112
Is a conditional branch instruction and a conditional generation instruction. When the instruction S112 is a conditional branch instruction, the first decoding unit 101 outputs a signal S111 indicating a branch destination address in the conditional branch instruction to the prefetch address unit 100, and indicates a branch condition in the branch instruction. The signal S115 is output to the condition determination unit 103. As the signal indicating the branch destination address, here, a signal S11 indicating an address difference between the branch destination address and the address of the previously prefetched instruction
1 is output. When the instruction S112 is a condition generation instruction, the signal S113 indicating the instruction address of the instruction S112 is output to the condition generation instruction address holding unit 102, and the undetermined signal S115 is output to the condition determination determination unit 103. . The determination as to whether or not the instruction is a condition generation instruction is performed by determining in advance whether or not the instruction is a condition generation instruction according to the type of instruction, for example, an instruction for performing addition, subtraction, multiplication, and division is used as the condition generation instruction.
Can be determined when is input. The instruction S
A signal S116 indicating the content of the instruction S112 is output to the instruction buffer 104 regardless of whether the instruction 112 is a conditional branch instruction, a conditional generation instruction, or neither a conditional branch instruction nor a conditional generation instruction. .

The signal S116, which is temporarily stored in the instruction buffer 104 and indicates the content of the instruction, is thereafter extracted by the second decoding unit 105 and subjected to decoding processing, whereby the content of the instruction is interpreted. The second decoding unit 105 outputs an instruction according to the content of the interpreted instruction to the arithmetic execution unit 107, and the arithmetic execution unit 107 executes arithmetic processing based on the input instruction. The result of the arithmetic processing is processed by the processor including the instruction prefetch device, and when the result of the arithmetic processing affects the condition code, the result is output to the condition code holding unit 106 and held. .

On the other hand, in the condition determination signal generating means 120, the condition generating instruction address
When the second address S113 is input, the address and the address obtained from the program counter 108 are input to the comparator 109 and compared. As described above, since the address of the instruction being executed is stored in the program counter 108 in the processing of the processor including the instruction prefetch device, the target condition generation instruction is executed by the comparison processing. You can know if it is. If the instruction has been executed, it is determined that the condition determined by the execution result of the instruction S112 has been determined. Therefore, a condition determination signal S118 indicating that the condition has been determined is output to the condition determination determining unit 103.

The condition determination unit 103 determines whether or not the condition determination signal S118 has been input from the condition determination signal generation unit 120, and receives an undetermined signal or a signal S115 as a signal indicating a branch condition from the first decoding unit. The operation differs depending on whether or not the operation has been performed. First, the undetermined signal S115
Is input, a reset process is executed in the condition determination unit 103, and the set state is reset by using the condition determination signal S118 based on the condition generation command processed immediately before.

The signal S115 indicating the branch condition is input to the condition determination unit 103 and the condition determination signal S
When 118 is input, a condition code is acquired from the condition code holding unit 106, and this is output to the prefetch address unit 100 as prefetch address information S114. On the other hand, when the signal S115 indicating the branch condition is input but the condition determination signal S118 is not input, the condition determination determining unit 103 does not operate and the branch predicting unit (not shown) operates as described above. The prediction is input to the prefetch address generation unit 100 and used.

In the prefetch address generator 100,
Using the input prefetch address information, a prefetch address signal S110 is generated and output. FIG. 2 is a diagram for explaining the operation of the prefetch address generation unit 100, and shows a main part of the internal configuration. As shown, the prefetch address generation unit 10
0 has a selector 151, an address counter 152, and an adder 153.

The selector 151 has a condition determination unit 103
In response to the prefetch address information S114 input from the controller, either the signal S111 or the fixed length (in this case, the value “4”) is selected, and this is added to the adder 153.
Output to The signal S111 is input as a signal indicating a branch destination address in the prefetched conditional branch instruction as described above, and is used as a relative value of an address difference. On the other hand, the fixed length is for fixedly determining the address difference. For example, if the fixed length is determined to be 4 bytes, the value “4” is used as shown in the figure.

The address counter 152 holds the address generated in the immediately preceding prefetch address generation processing. When the selected signal is output from the selector 151 to the adder 153, the adder 153 performs an addition process on the selected signal and the value held in the address counter 152. It is output as a prefetch address signal S110 which is a device output of the instruction prefetch device. At the same time, the prefetch address signal S110 is also output to the address counter 152 and is held for use in the next address generation processing.

With the above operation, the prefetch address generation unit 100 adds the address of the previously prefetched instruction held in the address counter 152 to the
In the adder 153, the address difference (relative value) transmitted by the signal S111 is added, and the obtained branch destination address becomes the prefetch address signal S110, or the fixed length “4” is added, and Of the instruction becomes the prefetch address signal S110.

Next, as in the case of the device according to the prior art,
The operation when executing the program shown in FIG.
This will be described with reference to the timing chart of FIG. At a timing t1 shown in the chart of FIG. 3, the address of the instruction 400 is generated in the prefetch address generation unit 100 and output as the prefetch address signal S110. In the processor using the instruction prefetch device, the instruction 400 is fetched using the prefetch address signal S110, and is input to the instruction prefetch device. At the next timing t2, the prefetched instruction 400 is input to the first decoding unit 101,
It is decoded.

Since instruction 400 is not a conditional branch instruction,
The signal S111 indicating the branch address and the signal S115 indicating the branch condition are not output. On the other hand, the instruction 400 is an instruction for changing the condition code (zero flag) and is determined to be a condition generation instruction. Therefore, the address of the instruction 400 is output to the condition generation instruction address holding unit 102 and stored, and The code undetermined signal S115 is input to the condition determination determining unit 103.

A signal S11 indicating the content of the instruction 400
6 is output to the instruction buffer 104. The second decoding unit 105 extracts the instruction 400 from the instruction buffer 104 and decodes the instruction 400, interprets that the instruction 400 is an addition instruction, and transmits the result of the decoding processing to the arithmetic execution unit 107 by signal output. The operation execution unit 107
The addition process indicated by the instruction 400 is executed, and the result of the addition process can affect the condition code.
The result of the addition process is output to the condition code holding unit 106, and the condition code holding unit 106 holds the changed condition code. At timing t3 in FIG. 3, the condition flag is determined.

By the execution of the instruction 400, which is a condition generation instruction, in the processing of the condition determination signal generation means 120,
Since the condition determination signal S118 is output, the condition determination unit 103 to which the condition determination signal S118 has been input is output.
Acquires the condition code S119 from the condition code holding unit 106.

At timing t4, the instruction 401, which is a conditional branch instruction, is decoded by the first decoding unit 101. Since the instruction 401 is a branch instruction, the signal S115 indicating the branch condition is
3 is output. In the condition determination unit 103, the signal S1
15, the correct address (the address of the instruction 403) as the instruction address to be executed next to the conditional branch instruction 401 based on the acquired condition code S119.
Is instructed to generate the prefetch address generation unit 100. Thus, the prefetch of the instruction 403 is performed based on the prefetch address generated at the timing t5.

When comparing FIG. 3, which is a timing chart, with FIG. 9, which is a timing chart when a device according to the related art is used, FIG. Is output, whereas the chart of FIG. 3 according to the first embodiment shows that the address of the instruction 403 is output at the timing t5. In the first embodiment, instead of prediction, It can be seen that the processing can be quickly performed by using the confirmation condition.

FIG. 4 is a diagram for explaining prefetch processing according to the first embodiment in pipeline processing. FIG. 7A shows a case according to the prior art, in which the instruction A
Is a condition generation instruction, it means that it is not possible to prefetch the next instruction based on the determined condition unless the instruction A is executed at the timing CLn + 2. On the other hand, in the case of the first embodiment shown in FIG. 6B, at the time of decoding the instruction A at the timing CL + 1, it is determined that the instruction A is a condition generation instruction, and the determined condition is determined. Since preparation for acquisition is performed, if the condition is determined by executing the instruction A at the timing CLn + 2, the instruction B can be prefetched based on the determined condition.

As described above, according to the instruction prefetch device of the first embodiment of the present invention, the condition determination signal generation means 12
0 and a condition determination unit 103, and the first decoding unit 1
01, when decoding a prefetched instruction, determines not only whether it is a branch instruction but also whether it is a condition generation instruction and outputs a signal indicating that. When the condition is determined, a signal S118 indicating the determination is input to the condition determination unit 103. Therefore, if the condition is already determined when the conditional branch instruction is prefetched, the branch prediction is not performed. A correct prefetch address is generated, and a delay time at the time of execution of a branch instruction due to a prediction mistake is eliminated, so that efficient processing can be performed.

Embodiment 2 The instruction prefetch device according to the second embodiment of the present invention determines whether or not a branch condition is determined in an instruction execution process, and when a condition is determined, prefetches an instruction corresponding to the condition. . FIG. 5 is a block diagram showing a configuration of the instruction prefetch device according to the second embodiment. As shown
The instruction prefetch device according to the second embodiment includes a prefetch address generation unit 200, a first decode unit 201,
The configuration includes a condition determination unit 202, an instruction buffer 202, a second decoding unit 204, a condition code holding unit 206, and an operation execution unit 205. In comparison with FIG. 1, the instruction prefetch device according to the second embodiment has a configuration that does not include the condition determination signal generation unit 120 that the device according to the first embodiment has.

The first decoding unit 201 performs a decoding process on the prefetched instruction S 209, acquires information indicating the content of the instruction, and outputs the information to the instruction buffer 203. Also, the first decoding unit 201
It is determined whether or not the instruction is a branch instruction. If the instruction is a branch instruction, it functions as a branch determination unit that outputs a branch signal. If the instruction S209 is a branch instruction, the conditional branch is performed. A signal S208 indicating a branch destination address in the instruction and a signal S211 indicating a branch condition in the branch instruction are output. Signals S208 and S22
1 is also handled as a branch signal indicating that it is a branch instruction.

The operation execution unit 205 outputs the condition determination signal S21
2, which functions as a condition determination signal generating means for generating the instruction code 2. When the instruction is executed, the instruction is an instruction for changing a condition code, that is, a condition generation instruction, and the changed condition code is If the instruction has an effect on a conditional branch instruction subsequent to the condition generation instruction, the condition determination signal S2 is output when the execution of the instruction is completed.
12 is output to the condition determination unit 202.

Therefore, in the program to be processed by the instruction prefetch device according to the second embodiment,
For an instruction that satisfies the above condition, information indicating that fact is provided in the instruction itself. Such a setting is, for example, in a process of creating an executable program such as a compilation, an instruction is analyzed, and for a condition generation instruction which affects a subsequent conditional branch instruction, information indicating the fact is added. This can be achieved by doing Therefore, in the second embodiment,
By giving the effect in the instruction, a condition determination signal 212 is sent to the condition determination determining unit 202 when the execution of the condition generation instruction is completed.

The prefetch address generation unit 200, the instruction buffer 203, the second decoding unit 204, and the condition code holding unit 206 are the same as those of the first embodiment.
0, 104, 105, and 106, so
Description is omitted.

The operation of the thus configured instruction prefetch apparatus according to the second embodiment will be outlined below. At a certain timing, the address of the instruction to be fetched next is generated in the prefetch address generation unit 200, and the prefetch address signal S20
7 is output. In the processor using the instruction prefetch device, an instruction is fetched using the prefetch address signal S207, and the instruction S2
09 is input to the instruction prefetch device. At the next timing, the prefetched instruction S209
The data is input to the decoding unit 201 and subjected to decoding processing.

In the first decoding unit 201, the instruction S209
Is a conditional branch instruction. Instruction S20
9 is a conditional branch instruction, the first decoding unit 201
Outputs a signal S208 indicating the branch destination address in the conditional branch instruction to the prefetch address unit 200,
At the same time, a signal S211 indicating the branch condition in the branch instruction is output to the condition determination unit 202. Also,
The signal indicating the content of the instruction S209 is output to the instruction buffer 104 regardless of whether the instruction S209 is a conditional branch instruction or not.

The signal indicating the content of the instruction temporarily stored in the instruction buffer 203 is then transmitted to the second decoding unit 20.
4, the contents of the instruction are interpreted by being decoded. Second decoding unit 204
Sends an instruction in accordance with the content of the interpreted instruction to the arithmetic execution unit 20
5, and the arithmetic execution unit 205 executes arithmetic processing based on the input instruction. The result of the arithmetic processing is processed by the processor including the instruction prefetch device, and when the result of the arithmetic processing affects the condition code, the result is output to the condition code holding unit 206 and held. .

In the instruction prefetch device according to the second embodiment, the operation execution unit 205 outputs a condition determination signal S212 to the condition determination determination unit 202 along with the output of a condition code in the following cases. That is, when the instruction S209 is a condition generation instruction and the condition code obtained as an execution result is used in a subsequent conditional branch instruction, the condition determination signal S212 is output as described above. As a result, in the apparatus according to the second embodiment, to generate the prefetch address, the fact that the condition code held in the condition code holding unit 206 can be used is transmitted to the condition determination determination unit 202.

A signal S211 indicating a branch condition is input to the condition determination
When 212 is input, a condition code is acquired from the condition code holding unit 206, and this is output to the prefetch address unit 200 as prefetch address information S210. On the other hand, when the signal S211 indicating the branch condition is input but the condition determination signal S212 is not input, the condition determination determining unit 202 does not operate and the first embodiment is performed.
Similarly to the above, the prediction by the branch prediction unit (not shown) is input to the prefetch address generation unit 200 and used. Thereafter, the prefetch address generation unit 200
Are the same as those in the first embodiment, and a prefetch address signal S207 is output as a device output of the instruction prefetch device according to the second embodiment.

Next, the operation when the program shown in FIG. 8 is executed will be described similarly to the case of the device according to the prior art and the device according to the first embodiment. Since the relationship between the operation and the operation is the same as that in the first embodiment, the first embodiment
3 will be described below with reference to the timing chart of FIG. At the timing t1 shown in the chart of FIG. 3, the address of the instruction 400 is generated in the prefetch address generation unit 200, and is output as the prefetch address signal S207. The processor using the instruction prefetch device fetches the instruction 400 using the prefetch address signal S207 and inputs the instruction 400 to the instruction prefetch device. At the next timing t2, the prefetched instruction 400 is input to the first decoding unit 201 and is decoded.

Since instruction 400 is not a conditional branch instruction,
The signal S208 indicating the branch address and the signal S211 indicating the branch condition are not output.

A signal indicating the content of the instruction 400 is output to the instruction buffer 203. The second decoding unit 204 extracts the instruction 400 from the instruction buffer 203 and decodes the instruction 400, interprets that the instruction 400 is an addition instruction, and transmits the result of the decoding processing to the arithmetic execution unit 205 by signal output. The instruction 400 is a condition generation instruction, and the execution result is the immediately following conditional branch instruction 401.
Is to affect. This fact is obtained from the information given at the time of compiling to the instruction 400. Here, the instruction 400 is interpreted by the second decoding unit 204 and transmitted to the arithmetic execution unit 205.

The operation execution unit 205 executes the addition process indicated by the instruction 400, and since the result of the addition process can affect the condition code, the result of the addition process is stored in the condition code holding unit 206. The condition code is output, and the condition code holding unit 206 holds the changed condition code. At timing t3 in FIG. 3, the condition flag is determined. And
The operation execution unit 205 according to the second embodiment outputs the condition determination signal S212 based on the information about the instruction 400 transmitted from the second decoding unit 204, to the condition determination unit 2
02 is output. The condition determination determining unit 202 that has received the condition determination signal S212 acquires the condition code S213 from the condition code holding unit 206.

At a timing t4, the instruction 401, which is a conditional branch instruction, is decoded by the first decoding unit 201. Since the instruction 401 is a branch instruction, the signal S211 indicating the branch condition is
2 is output. In the condition determination unit 202, the signal S2
In response to the input of No. 11, the correct address (the address of the instruction 403) is determined as the instruction address to be executed next to the conditional branch instruction 401 based on the acquired condition code S213.
Is instructed to generate the prefetch address generation unit 200. Thus, the prefetch of the instruction 403 is performed based on the prefetch address generated at the timing t5.

As described above, according to the instruction prefetch device of the second embodiment, for a condition generation instruction that affects a subsequent conditional branch instruction, the instruction itself has information to that effect, and the instruction At the time of execution, the arithmetic execution unit 205 generates the condition confirmation signal,
As in the first embodiment, if the condition is already determined when the conditional branch instruction is prefetched, a correct prefetch address is generated without performing branch prediction, and the delay time at the time of execution of the branch instruction due to a prediction error is reduced. And efficient processing can be performed.

In the second embodiment, it is necessary to perform the above-described processing at the time of compiling a program, and a program corresponding to the apparatus of the second embodiment which has been subjected to such processing must be used. Along with the execution of the arithmetic processing, the condition determination can be confirmed and a condition determination signal can be generated, and in the instruction prefetch device, the configuration of the device can be simplified and the processing can be simplified.

[0076]

According to the present invention, in a computer for executing an instruction, the instruction prefetch apparatus prefetches from a storage device storing the instruction, wherein the prefetched instruction instructs a branch. A branch decision means for outputting a branch signal if the instruction is a branch instruction, and a condition for determining a branch in the branch instruction when the branch signal is output. It is determined whether or not the fixed condition information has been set. If the fixed condition information has been set, fixed condition information generating means for outputting fixed condition information corresponding to the condition to a prefetch address generating means described later; A prefetch address generating means for generating an address to be prefetched based on the fixed condition information when the fixed condition information is input from the generating means; In prefetching an instruction following a branch instruction, if a condition is determined, an address of an instruction corresponding to the determined condition is generated, so that delay due to a branch prediction error is reduced. ,
Processing efficiency can be improved by utilizing device resources.

According to the instruction prefetch apparatus of the second aspect, in the apparatus of the first aspect, the determination condition information generating means determines whether a condition for determining a branch in the branch instruction is determined, and A condition determination signal generating means for outputting a condition determination signal when the condition determination signal has been output; and when the condition determination signal has been output, obtaining the determined condition and obtaining the determined condition information based on the obtained condition. And a condition determination signal for generating a prefetch address corresponding to the determined condition by transmitting a condition determination signal as to whether or not the condition has been determined. , And the efficiency of processing utilizing device resources can be increased.

According to a third aspect of the present invention, in the second aspect of the present invention, the condition determination signal generating means includes: a first instruction address holding means for holding an address output from the branch determination means; A second instruction address holding unit that holds the address of the instruction being executed at that time, the first instruction address holding unit, and a comparison process of the addresses held by the second instruction address holding unit are performed. A comparison unit that outputs the condition determination signal to the condition determination determination unit when it is determined that the conditions match in the comparison, and determines whether or not the condition is determined. Execution is performed by comparing the address of the instruction to be determined with the address of the instruction being executed, thereby determining whether or not the condition has been determined. Hesi in, it is possible to streamline the process utilizing device resources.

According to a fourth aspect of the present invention, in the device of the third aspect, the branch determination means determines whether the prefetched instruction is a condition generation instruction, and determines whether the instruction is a condition generation instruction. In this case, the address of the condition generating instruction is output to the first instruction address holding means, and a condition undetermined signal is output to the condition determination determining means. As information indicating a branch condition in the branch instruction,
It outputs to the prefetch address generation means, and outputs information indicating a branch destination address in the branch instruction to the condition determination determination means, and executes a determination process for the condition generation instruction. Holds, the determination about the condition determination by the address comparison is executed. If the condition is determined, the condition is used to reduce the delay due to the branch prediction error, and the processing using the device resources is performed. Can be made more efficient.

According to a fifth aspect of the present invention, in the apparatus of the fourth aspect, when the condition determination signal is input, the condition determination determining means may receive the next address of the branch instruction or the branch destination. The prefetch address generation means outputs condition determination information indicating that an address is to be used, and generates an address of an instruction corresponding to the determined condition. It is possible to increase the efficiency of processing using resources.

According to the instruction prefetch apparatus of claim 6, in the apparatus of claim 1, the determination condition information generating means determines whether the prefetched instruction is a condition generation instruction for determining a condition for determining the branch. If the instruction is a condition generation instruction, an operation is performed in accordance with the condition generation instruction, and the result is used to generate the above-described final condition information. When the condition is determined, by using the condition, it is possible to reduce the delay due to a branch prediction error and to increase the efficiency of the process using the device resources.

According to the instruction prefetch device of claim 7, in the device of claim 6, the condition generation instruction includes information indicating that the instruction is a condition generation instruction, and is accompanied by an arithmetic operation. The effect described above can be obtained by executing the analysis of the instruction.

According to an eighth aspect of the present invention, there is provided an instruction prefetching method for prefetching from a storage device for storing the instruction, wherein the prefetched instruction is a branch instruction for instructing a branch. It is determined whether or not the instruction is a branch instruction. If the instruction is a branch instruction, a branch determination step of outputting a branch signal, and if the branch signal is output, a condition for determining a branch in the branch instruction is determined. It is determined whether or not the fixed condition information is generated. If the fixed condition information is determined, the fixed condition information generating step of outputting the fixed condition information corresponding to the condition so as to be used in a prefetch address generating step described later; In the generation step, when the fixed condition information is output, an address to be prefetched is generated based on the fixed condition information. A prefetch address generating step for prefetching an instruction following the branch instruction. If the condition is determined, an address of the instruction corresponding to the determined condition is generated. The delay can be reduced, and the efficiency of the process using the device resources can be increased.

According to a ninth aspect of the present invention, in the method of the eighth aspect, the determining condition information generating step determines whether or not a condition for determining a branch in the branch instruction has been determined. A condition determination signal generating step of outputting a condition determination signal when the condition determination signal has been output; and, when the condition determination signal has been output, acquiring the determined condition and obtaining the determined condition information based on the acquired condition. Is generated, and the above effect is obtained by transmitting whether or not the condition is determined in the condition determination signal.

According to a tenth aspect of the present invention, in the method of the eighth aspect, in the determining condition information generating step, it is determined whether or not the prefetched instruction is a condition generating instruction for determining a condition for determining the branch. If the instruction is a condition generation instruction, an operation is performed in accordance with the condition generation instruction, and the result is used to generate the above-described final condition information. The above effect can be obtained by executing the above.

According to the instruction prefetch method of claim 11, in the method of claim 10, the condition generating instruction is:
The instruction includes information indicating that the instruction is a condition generation instruction, and the above-described effect is obtained by executing the analysis of the instruction along with the arithmetic processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an instruction prefetch device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a main configuration for explaining a function of a prefetch address generation unit of the embodiment.

FIG. 3 is a timing chart showing a schematic operation of a process in the embodiment.

FIG. 4 is a diagram for explaining a processing flow in the embodiment in comparison with the case of the related art;

FIG. 5 is a block diagram showing a configuration of an instruction prefetch device according to a second embodiment of the present invention.

FIG. 6 is a diagram for explaining processing by a processor of a computer.

FIG. 7 is a block diagram showing a configuration of an instruction prefetch device according to a conventional technique.

FIG. 8 is a diagram showing an example of a program to be processed.

FIG. 9 is a timing chart illustrating a schematic operation of a process according to a conventional technique.

[Explanation of symbols]

100, 200, 300 prefetch address generation units 101, 201, 303 first decoding unit 102 condition generation instruction address holding unit 103, 202 condition determination determination unit 104, 203, 305 instruction buffer 105, 204, 306 second decoding unit 106, 206, 308 Condition code holding unit 107, 205, 307 Arithmetic execution unit 108 Program counter 109 Comparator 120 Condition determination signal generation means

Claims (11)

[Claims] 1. A computer for executing an instruction, comprising: an instruction prefetch device for prefetching from a storage device for storing the instruction, wherein it is determined whether or not the prefetched instruction is a branch instruction for instructing a branch. If the instruction is a branch instruction, branch determination means for outputting a branch signal; and, when the branch signal is output, determine whether a condition for determining a branch in the branch instruction is determined,
When it is determined, the fixed condition information generating means for outputting the fixed condition information corresponding to the condition to a prefetch address generating means, which will be described later, and the fixed condition information generating means from the fixed condition information generating means. And a prefetch address generating means for generating an address to be prefetched based on the fixed condition information. 2. The instruction prefetch apparatus according to claim 1, wherein the determination condition information generating unit determines whether a condition for determining a branch in the branch instruction is determined, and determines whether a condition for branching is determined. Is a condition determination signal generating means for outputting a condition determination signal; and, when the condition determination signal is output, acquiring the determined condition and generating the determination condition information based on the acquired condition. An instruction prefetch device, comprising: a determination unit. 3. The instruction prefetch device according to claim 2, wherein said condition determination signal generation means includes: first instruction address holding means for holding an address of an instruction output from said branch determination means; The second instruction address holding means for holding the address of the instruction being executed, the first instruction address holding means, and the second instruction address holding means perform a comparison process on the addresses held by the second instruction address holding means. When it is determined that they match,
An instruction prefetch device comprising: a comparison unit that outputs the condition determination signal to the condition determination determination unit. 4. The instruction prefetch device according to claim 3, wherein the branch determination unit determines whether the prefetched instruction is a condition generation instruction, and if the prefetched instruction is a condition generation instruction, the branch determination unit determines whether the instruction is a condition generation instruction. The address of the generated instruction is output to the first instruction address holding means, and a condition undetermined signal is output to the condition determination determining means. And the information indicating the branch destination address in the branch instruction is output to the prefetch address generating means. Instruction prefetch unit. 5. The instruction prefetch device according to claim 4, wherein the condition determination determining means should use the next address of the branch instruction or the branch destination address when the condition determination signal is input. An instruction prefetch apparatus for outputting condition determination information indicating the above to the prefetch address generation means. 6. The instruction prefetch apparatus according to claim 1, wherein the determination condition information generation unit determines whether the prefetched instruction is a condition generation instruction that determines a condition for determining the branch. If the instruction is a condition generation instruction, the instruction prefetch device executes an arithmetic process in accordance with the condition generation instruction, and generates the above-mentioned fixed condition information using the result. 7. The instruction prefetch apparatus according to claim 6, wherein the condition generation instruction includes information indicating that the instruction is a condition generation instruction. 8. A method for prefetching an instruction from a storage device for storing an instruction in a computer that executes the instruction, comprising: determining whether the prefetched instruction is a branch instruction for instructing a branch. If the instruction is a branch instruction, a branch determining step of outputting a branch signal; and, when the branch signal is output, determining whether a condition for determining a branch in the branch instruction is determined,
When it is determined, the fixed condition information generating step of outputting the fixed condition information corresponding to the condition so as to be used in the prefetch address generating step described later; A prefetch address generating step of generating an address to be prefetched based on the determined condition information when the instruction is output. 9. The instruction prefetch method according to claim 8, wherein the determining condition information generating step determines whether or not a condition for determining a branch in the branch instruction has been determined. Is a condition determination signal generating step of outputting a condition determination signal; and, when the condition determination signal is output, acquiring the determined condition and generating the determination condition information based on the acquired condition. And a determining step. 10. The instruction prefetch method according to claim 8, wherein in the determining condition information generating step, it is determined whether the prefetched instruction is a condition generating instruction for determining a condition for determining the branch. If the instruction is a condition generation instruction, the instruction prefetch method is characterized in that an arithmetic process is executed in accordance with the condition generation instruction, and the result is used to generate the fixed condition information. 11. The instruction prefetch method according to claim 10, wherein the condition generation instruction includes information indicating that the instruction is a condition generation instruction.