JPH10186006A - Test methods for printed circuit boards - Google Patents

Abstract

(57) [Summary] The present invention relates to a memory module connector and an L connector.
An object of the present invention is to provide a method for testing a printed circuit board, which can test the connection of a wiring network to an SI. SOLUTION: A test resistance module provided with a plurality of terminating resistors is mounted on the memory module connector, each terminal of the connector is terminated, and a probe of a measuring instrument is connected to each terminal of the memory module connector. Test by measuring current / voltage characteristics. As described above, a connection failure or short circuit of the wiring network connected to each terminal of the memory module connector can be detected from the current / voltage characteristics, and a connection state test of the wiring network can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a printed circuit board, and more particularly to a connector for a memory module and an LSI.
The present invention relates to a method for testing a printed circuit board on which a (semiconductor integrated circuit) is mounted.

[0002]

2. Description of the Related Art There are roughly two methods for testing the quality of manufacture of a printed circuit board on which electronic components including an LSI are mounted. A first method is to input a test signal from an input terminal of a printed circuit board, measure an output signal at an output terminal of the printed circuit board, and compare the measured output signal with an expected value to determine pass / fail. Test.

In a second method, a measurement point is provided at a required portion of a wiring of a printed circuit board, a probe capable of inputting / outputting a signal is brought into contact with the measurement point, and a current-voltage characteristic test or the like between the contact points is performed. This is an in-circuit test for determining good or bad by comparing with an expected value. Here, a probe and a cable for electrically connecting the printed circuit board and the test apparatus and a mechanism for holding the probe and the cable are called a fixture. However, if a fixture is prepared for each type of printed circuit board to be tested, the cost is high. And the labor is increased. For this reason, a flying probe-type in-circuit tester for performing a test by moving several probes at high speed according to a program and bringing them into contact with a measurement point has been conventionally developed and used.

[0004] Incidentally, large computers have many printed circuit boards. Some of these printed circuits have a connector for a RAM module mounted thereon. Here, the RAM module is a memory (RAM)
A chip is mounted on a small board in units of several to several tens. In order to make the memory capacity of the computer optional, a plurality of RAM module connectors (memory module connectors) are mounted on the printed circuit board which is the main board, and expansion or reduction of the memory in RAM module units is requested by the user. It is possible.

Conventionally, when assembling and testing a printed circuit board on which the above-described RAM module connector is mounted, the entire printed circuit board is tested by performing a function test after mounting all the RAM modules.

[0006]

In order to test the connectivity between an LSI and a printed circuit board, a conventional function test or in-circuit test supplies a test signal to the LSI, operates the LSI, and outputs a signal to the outside. Since the signal is propagated to the terminal, it is difficult to generate a test signal due to high integration and ASIC of the LSI. Therefore, actual function tests for embedding printed circuit boards in actual equipment and performing typical operations to determine whether or not they are good have come to be used. , And it is difficult to identify defective parts.

For this reason, in many cases, the electrical test of the connectivity between the LSI and the printed circuit board is not performed, but is performed by the appearance test. However, when the package of the LSI is a QFP (quad flat package), it is not easy to observe the floating of the solder and the like because the terminal pitch is fine. Further, when the package of the LSI is a BGA (ball grid array), there is a problem that the solder joint is hidden on the lower surface of the LSI and cannot be observed.

As described above, the function test of the entire printed circuit board has become difficult due to the high integration of the LSI mounted on the printed circuit board and the mounting of the microprocessor on the printed circuit board. A method for testing only the normality of the connection between the LSIs of the printed circuit board or between the LSI and the connector has been used on the premise that it is guaranteed by the unit test.

The most common of the methods is an IEEE standard test method called a boundary scan. Boundary scan means that a standard test circuit is embedded in the outermost periphery of the LSI in advance, and this circuit is operated by a control signal from the tester during the test to simplify the test of the connection between the LSIs or the connection between the LSI and the tester. How to

However, even on a board in which a boundary scan circuit is embedded, the connector for the RAM module existing inside the board is usually open in terms of a circuit, so the connection of the wiring network connected to this connector is not possible. The test was difficult. The present invention has been made in view of the above points, and has as its object to provide a printed circuit board test method capable of testing a connection of a wiring network between a memory module connector and an LSI.

Still another object of the present invention is to provide a method of testing a printed circuit board which enables a test of connectivity between an integrated circuit and a printed circuit board to be performed in a short time and facilitates generation of a test signal. And

[0012]

According to a first aspect of the present invention, there is provided a method for testing a printed circuit board provided with a memory module connector on which a memory module on which a memory chip is mounted is mounted. The provided test resistor module is mounted on the memory module connector, each terminal of the connector is terminated, and a probe of a measuring instrument is connected to each terminal of the memory module connector to measure current / voltage characteristics. Perform the test.

As described above, the connection failure of the wiring network connected to each terminal of the connector for the memory module can be detected from the current / voltage characteristics, and the connection state of the wiring network can be tested. According to a second aspect of the present invention, there is provided a method for testing a printed circuit board provided with a memory module connector on which a memory module on which a memory chip is mounted is mounted, wherein a wiring network is provided to the memory module connector on the printed circuit board. The integrated circuit connected by the above has a boundary scan circuit, a probe of a measuring instrument is connected to each terminal of the connector for the memory module, and a test signal is outputted from the boundary scan circuit and received by the measuring instrument. And conduct the test.

As described above, by connecting the boundary scan circuit and the measuring device to both ends of the wiring network connected to each terminal of the memory module connector, the test signal output from the boundary scan circuit can be measured. To test the connection state of the wiring network. According to a third aspect of the present invention, in the method for testing a printed circuit board provided with a memory module connector on which a memory module having a memory chip mounted thereon is mounted, a wiring network is provided on the printed circuit board to connect the memory module connector. Has a boundary scan circuit, connects between the two terminals of the memory module connector, and performs a test using the boundary scan circuits connected to both ends of the wiring network.

As described above, by connecting and folding between the two terminals of the memory module connector, the wiring network connected by the folding is connected to the boundary scan circuit at both ends thereof. A test signal is output from the scan circuit, and the test signal is received by the other boundary scan circuit, so that the connection state of the wiring network can be tested.

According to a fourth aspect of the present invention, in the method for testing a printed circuit board according to the third aspect, a folded card for connecting the two terminals of the memory module connector is inserted into the memory module connector. The two terminals of the connector are connected.

[0017] Thus, it is possible to make a return with a normal memory module connector in which each terminal is open when the card is not inserted. The invention according to claim 5 is
4. The method for testing a printed circuit board according to claim 3, wherein the memory module connector is of a self-folding type that connects between two terminals when the memory module is not mounted.

For this reason, the memory module can be folded back by the connector for the memory module in a non-mounted state, and the number of test steps can be greatly reduced. According to a sixth aspect of the present invention, there is provided a method for testing a printed circuit board provided with a memory module connector on which a memory module on which a memory chip is mounted is mounted, wherein a wiring network is provided to the memory module connector on the printed circuit board. Integrated circuit having a boundary scan circuit, a boundary scan circuit provided with the boundary scan circuit mounted on the connector for the memory module, and a boundary scan circuit connected to both ends of the wiring network Perform the test using.

Therefore, a boundary scan circuit is connected to both ends of the wiring network connected to each terminal of the connector for the memory module, and a test signal is output from the boundary scan circuit of the integrated circuit, and the boundary scan circuit is connected to the boundary scan circuit. A test signal can be received by the Dally scan circuit to test the connection state of the wiring network. 8. A method for testing a printed circuit board on which an integrated circuit having a boundary scan circuit is mounted, wherein the printed circuit board is connected to a terminal connected to each of a plurality of boundary scan cells of the integrated circuit. A test signal supplied to the integrated circuit from the input probe by moving the input and output probes to and from the plurality of wires;
A test is performed by comparing with a test result signal measured by the output probe.

As described above, by using the boundary scan circuit in the integrated circuit, the connectivity test between the lead terminals of the integrated circuit and the wiring of the printed circuit board can be performed without operating the internal logic circuit of the integrated circuit. Can be performed in a short time by moving the probe, and the test signal can be easily generated because the internal logic circuit is not operated. Claim 8
In the printed circuit board testing method according to the present invention, the timing at which the output probe is moved and brought into contact with a plurality of wirings of the printed circuit board to perform the measurement is defined by the boundary lease cancellation. Synchronize with the signal output timing.

[0021] Thus, by sequentially moving the output probe and making contact with the wiring of the printed circuit board for measurement, the connectivity test between the plurality of terminals of the integrated circuit and the plurality of wirings of the printed circuit board is performed. It can be performed. According to a ninth aspect of the present invention, in the printed circuit board testing method according to the seventh aspect, the timing of supplying the test signal by moving the input probe to contact the plurality of wirings of the printed circuit board, The timing is synchronized with the signal fetch timing to the boundary lease cancel.

Thus, by sequentially moving the input probe and making contact with the wiring of the printed circuit board to supply the test signal, the connection between the plurality of terminals of the integrated circuit and the plurality of wirings of the printed circuit board is established. Sex tests can be performed.
According to a tenth aspect of the present invention, in the printed circuit board testing method according to any one of the seventh to ninth aspects, the test signal includes only a boundary lease cancel corresponding to a wiring connected to the output probe. At one of the high level and the low level, the other pluralities of the boundary lease cancel are set to the other level, and then the boundary lease cancel corresponding to the wiring connected to the output probe is performed. Only at the other level,
Other multiple boundary lease cancellations are set to one level.

As described above, a test signal of a different level from that of the other boundary lease cancels is set only for the boundary lease cancel corresponding to the wiring to which the output probe is connected. It is possible to easily test the connection state of the wiring connected to the probe from the test result signal.

[0024]

FIG. 1 is a schematic structural view of a first embodiment of the present invention. In the figure, LS is printed on the printed circuit board 10.
I12 and 14 and a RAM module connector (memory module connector) 16 are mounted. This R
The AM module connector 16 and the LSIs 12 and 14 are connected by wiring networks 18 and 20, respectively. RA
A test resistor module 22 is inserted and mounted in the M module connector 16. This test resistor module 2
2 is a RAM module connector 1 with one end of the resistance element R
6 and the other end of the resistance element R is grounded. The measuring device 24 is, for example, a prober 26 by computer control.
Is moved to an arbitrary XY coordinate position on the printed circuit board 10.

As shown in the circuit diagram of FIG. 2, the probe 26 is brought into contact with the terminal p ₁ of the RAM module connector 16 to be electrically connected. A current source 28 in the measuring instrument 24 supplies a current from the probe 26 to the ground through the resistance R of the test resistance module 22. Then, the voltmeter in the measuring instrument 24 measures the voltage when the current is varied and flows, and observes the current / voltage characteristics.

Terminal p of RAM module connector 16
If wiring network 12 _first printed circuit board 10 to be connected ₁ LSI12 the terminal q ₁ of a normal, current / voltage characteristic current value exceeds the threshold voltage Vth as shown by the solid line Ia in Fig. 3 It is almost constant. This is because the LSI 12 has the parasitic diode D ₁ , and the characteristic obtained by combining the resistance value R and the diode characteristic of the parasitic diode D ₁ is observed by the measuring device 24.

If the connection between the terminal p ₁ or the terminal q ₁ and the wiring network is defective and the circuit is open, the LSI 12
3 cannot be observed, the broken line Ib in FIG.
Are observed. Further, if there is a connection failure between the RAM module connector 16 and the test resistor module 22, the resistor R is not connected to the measuring device 24.
Only the diode characteristics shown in FIG. Furthermore,
A wiring network 18 _1, characteristic as indicated by a broken line Id the resistance value becomes 1/2 resistor R becomes the parallel connection state is observed when the wiring network 18 ₂ adjacent thereto are short-circuited You.

In this way, by observing the current / voltage characteristics with the measuring device 24, it becomes possible to test the wiring network connected to the RAM module connector 16. FIG. 4 is a schematic configuration diagram of a second embodiment of the present invention. In FIG. 1, LSIs 32 and 34 and a connector 16 for a RAM module are mounted on a printed circuit board 10. The RAM module connector 16 and the LSIs 32 and 34 are connected by wiring networks 18 and 20, respectively. LSI32,
A plurality of cascade-connected boundary lease scans (boundary scan circuits) 33 and 35, which are standard test circuits, are embedded in the outermost periphery of the LSI circuit. The tester 36 has a function of moving the prober 26 to an arbitrary XY coordinate position on the printed circuit board 10 under the control of a computer, for example.

As shown in the circuit diagram of FIG. 5, the probe 26 is brought into contact with the terminal p ₁ of the RAM module connector 16 to be connected. Then, the boundary lease cancel 33 ₁ to 33 3 of the LSI 32 from the measuring device 36 through the wiring network 18 _1.
3 Control signal is supplied to _n , and boundary lease cancel 3
3 ₁ ~ 33 _n respectively to thereby output a test signal pattern as shown in FIG. 6, RAM probe 26 every two pattern
This pattern is observed by contacting the terminals p _{1 to pn} of the module connector 16.

The pattern shown in FIG.
Is Boundary Lease Cancellation 33₁Only high level output
The remaining Boundary Lease Cancellation 33_Two~ 33_nIs
-Level output, pattern number 2
Cancel 33₁Only low level output at rest boundary
Scancell 33_Two~ 33_nIs a high level output,
One terminal (wiring network) with these two patterns as one set
Test for In the same way,
Cancel 33_Two~ 33_nRemaining boundary for each
Performs two different levels of output with scan cells
I'm making it. In pattern numbers 1 and 2, probe 26
Terminal p₁The signal level read from the
Cancel 33₁If the output level is the same,₁
Is determined to be normal, and if different, it is determined to be abnormal
Is done. Other wiring network 18_Two~ 18 _nSame for each
It is.

As described above, by connecting the boundary scan circuit and the measuring instrument to both ends of the wiring network connected to each terminal of the memory module connector, the test signal output from the boundary scan circuit can be measured. To test the connection state of the wiring network. FIG. 7 is a schematic configuration diagram of a third embodiment of the present invention. In FIG. 1, LSIs 32 and 34 and a connector 16 for a RAM module are mounted on a printed circuit board 10. A wiring network 1 is provided between the RAM module connector 16 and each of the LSIs 32 and 34.
8, 20 are connected. In each of the LSIs 32 and 34, a plurality of cascade-connected boundary lease scans (boundary scan circuits) 33 and 35, which are standard test circuits, are embedded at the outermost periphery of the LSI circuit.

The return card 40 is inserted in the RAM module connector 16. The return card 40 connects the terminal of the wiring network 18 connected to, for example, the LSI 32 in the connector 16 and the terminal of the wiring network 20 connected to the LSI 34. The test of the wiring networks 18 and 20 will be described with reference to the circuit diagram of FIG. The terminal u of the RAM module connector 16 is determined by the folded card 40.
₁ and w ₁ are interconnected. As a result, the wiring network 18 ₁
When 20 ₁ and is connected, LSI by integrated wiring network
32 terminals u ₁ Boundary-Scan 33 ₁ as the starting point of, v _1, w _1, circuit leading to boundary scan 35 ₁ of LSI34 via x ₁ is formed.
The other wiring networks 18 ₂ to 18 _n are also connected to the wiring networks 20 _{2 to} 20 _n
Are integrated with each, Boundary-Scan 33 _2-3
A wiring network is formed which is terminated by 3 _n and 35 _{2 to} 35 _{n respectively} . This makes it possible to test the normality of each of the integrated wiring networks by an interconnection test method using a general boundary scan.

For example, boundary lease cancellation on the output side
33₁~ 33_nFrom the test signal of the pattern shown in FIG.
Output and use this pattern as the boundary scan on the input side.
Cancel 35₁~ 35_nTo receive. This test signal
Under lease cancellation 33 ₁From 33_nHigh in order
This is a pattern in which the level shifts.
Cancel 35₁~ 35_nHigh level received sequentially at
When completed, the normality of the wiring network connection can be confirmed.

[0034] Incidentally, the folded card 40 terminals v ₁ and v ₂ adjacent in the same plane as shown in FIG. 10, ... v _n-1 and v _n may be used to connect the short-circuit pattern 42. Wiring network 18 ₁ and 18 ₂ in this case, ... 18 _n-1
When 18 _n are respectively integrated, the output side of the odd-numbered boundary scan 18 ₁ ... 18 _n-1 of the test signal LSI 32, the even-numbered boundary scan 18 ₂ of LSI 32, a ... 18 _n of the test signal Test as input side.

As described above, by connecting and folding between the two terminals of the memory module connector, the wiring network connected by the folding is connected to the boundary scan circuit at both ends thereof. A test signal is output from the scan circuit, and the test signal is received by the other boundary scan circuit, so that the connection state of the wiring network can be tested.

FIG. 11 is a schematic structural view of a fourth embodiment of the present invention. In the figure, an LSI 3 is provided on a printed circuit board 10.
2, 34 and a self-folding type RAM module connector 46 are mounted. A wiring network 18 is provided between the RAM module connector 16 and the LSIs 32 and 34, respectively.
20. In each of the LSIs 32 and 34, a plurality of cascade-connected boundary lease cells 33 and 35, which are standard test circuits, are embedded at the outermost periphery of the LSI circuit.

As shown in FIG. 12, the self-folding type RAM module connector 46 connects the contact members 50 and 52 to the terminals (edges) of the printed board 48 in a state where the printed board 48 of the RAM module is inserted as in the case of a normal connector. (Connectors) 54 and 56 are pressed against each other and interconnected.
However, as shown in FIG. 13, when the printed board 48 is pulled out, the contact members 50 and 52 facing each other are brought into contact by elasticity to conduct.

Note that the printed board 48 is drawn in FIG.
Self-folding RAM module
14B and 14C are plan views of the connector 46, and FIG.
Front view, side, with joule printed board 48 inserted
Each of the plan views is shown. FIG. 14D shows the oblique view of the RAM module.
FIG. According to the circuit diagram of FIG.
Tests 8 and 20 will be described. Self-folding R
AM module connectors 16 and 46 are printed
Terminal u₁And w₁And are interconnected.
Thereby, the wiring network 18₁And 20₁And connected and integrated
LSI 32 boundary scan cell
Le 33 ₁From the terminal u₁, V₁, W₁, X₁Through
As a result, the boundary lease cancellation 35 of the LSI 34₁To
The resulting circuit is formed. Other wiring network 18_Two~ 18_nRespectively
Also wiring network 20_Two~ 20_nEach integrated and boundary
Scancell 33_Two~ 33_n35 with each_Two~ 35_nRespectively
A wiring network terminated by the above is formed. by this
Interconnect test method using general boundary scan
Can test the normality of each of the integrated wiring networks.

For example, boundary lease cancellation on the output side
33₁~ 33_nFrom the test signal of the pattern shown in FIG.
Output and use this pattern as the boundary scan on the input side.
Cancel 35₁~ 35_nTo receive. This test signal
Under lease cancellation 33 ₁From 33_nHigh in order
This is a pattern in which the level shifts.
Cancel 35₁~ 35_nHigh level received sequentially at
When completed, the normality of the wiring network connection can be confirmed.

In this embodiment, it is not necessary to insert a test pseudo circuit such as a folded card into the RAM module connector 46 at the time of testing, so that the number of test steps can be greatly reduced. This is because a personal computer or the like is provided with only a few RAM module connectors, but a supercomputer or the like may be provided with several tens to more than one hundred connectors.

FIG. 16 is a schematic structural view of a fifth embodiment of the present invention. In the figure, an LSI 3 is provided on a printed circuit board 10.
2 and 34 and a self-folding type RAM module connector 16 are mounted. A wiring network 18 is provided between the RAM module connector 16 and the LSIs 32 and 34, respectively.
20. In each of the LSIs 32 and 34, a plurality of cascade-connected boundary lease cells 33 and 35, which are standard test circuits, are embedded at the outermost periphery of the LSI circuit.

A test boundary scan card 60 is inserted into the RAM module connector 16. The test boundary scan card 60 is equipped with a test LSI 62 incorporating a plurality of cascade-connected boundary lease cancels 64, and the boundary lease scans 64 are connected to the wiring networks 18 and 20, respectively.

The test of the wiring network 18 will be described with reference to the circuit diagram of FIG. Test boundary scan card 6
0 is inserted into the RAM module connector 16 so that both ends of the wiring networks 18 ₁ to 18 _n
It is terminated at the boundary scan 33 ₁ ~ 33 _n and Boundary-Scan 64 ₁ to 64 _n of the test boundary scan card 60. This makes it possible to test the normality of each of the integrated wiring networks by an interconnection test method using a general boundary scan.

For example, boundary lease cancellation on the output side
33₁~ 33_nFrom the test signal of the pattern shown in FIG.
Output and use this pattern as the boundary scan on the input side.
Cancel 64₁~ 64_nTo receive. This test signal
Under lease cancellation 33 ₁From 33_nHigh in order
This is a pattern in which the level shifts.
Cancel 64₁~ 64_nHigh level received sequentially at
When completed, the normality of the wiring network connection can be confirmed.

For this reason, a boundary scan circuit is connected to both ends of the wiring network connected to each terminal of the connector for the memory module, a test signal is output from the boundary scan circuit of the integrated circuit, and a boundary scan circuit of the boundary scan card is connected. A test signal can be received by the Dally scan circuit to test the connection state of the wiring network. A connection method of the scan signal of the test boundary scan card 60 will be described. FIG. 18 shows a first example of the RAM module card.
FIG. 3 shows a plan view of the embodiment. In the figure, a terminal (edge connector) 74 in addition to a terminal (edge connector) 72 is provided on one side of the board 70 inserted into the connector. Substrate 7
A RAM chip 76 is attached to 0, and a plurality of terminals of the RAM chip 76 are connected to the terminals 72, respectively. The terminal 74 is an empty terminal.

FIG. 19 is a plan view of a first embodiment of the test boundary scan card. In the figure, a terminal (edge connector) 8 is provided on one side of the board 78 inserted into the connector.
In addition to 0, a terminal (edge connector) 82 is provided. The arrangement of the terminals 80 and 82 corresponds to the terminal 7 in FIG.
2, 74 sequences. A test LSI 62 is mounted on the substrate 78, and the cascade-connected boundary lease cancelers 64 _{1 to} 64 in the test LSI 62 are mounted.
4 _n are respectively connected to the terminals 80. Also, test signals TCK, TMS, T for scan control during a test
The terminal 82 to which DI and TDO are transmitted is connected to the test LSI 62
TAP (test access port) 65 in the inside.

FIG. 20 is a circuit diagram of a printed circuit board on which the above-described RAM module card or test boundary scan card is mounted. In the figure, a plurality of RAM module connectors 86 _{1 to} 86 _m are mounted on a substrate 84, and a control circuit 88 for controlling RAM access and the like is mounted.
Each of the M module connectors 86 _{1 to} 86 _m is interconnected by a bus 90.
R to be inserted into M module connectors 86 _{1 to} 86 _m
It is connected to the terminal 72 of the AM module card and the terminal 80 of the boundary scan card. A signal line 92 for test signals TCK, TSM, TDI, and TDO is provided independently of the bus 90, and the RAM module connector 8
It is connected to the 6 ₁ -86 _m and the control circuit 88. The signal line 92 extends to an end of the substrate 84 and is connected to an external connector 94 to which a tester (not shown) is connected during a test.

FIG. 21 is a plan view of a second embodiment of the RAM module card. In the figure, a terminal (edge connector) 102 is provided on one side of the board 100 inserted into the connector. A RAM chip 104 is attached to the substrate 70, and a plurality of terminals of the RAM chip 104 are connected to the terminals 102, respectively. FIG. 22 is a plan view of a second embodiment of the test boundary scan card. In the figure,
A terminal (edge connector) 108 is provided on one side of the board 106 to be inserted into the connector, and a test signal connector 110 is provided on one side facing the terminal. The arrangement of the terminals 108 is the same as the arrangement of the terminals 102 in FIG. A test LSI 112 is mounted on the board 78, and each of the cascade-connected boundary lease cancelers 114 _{1 to} 114 _n in the test LSI 112 is connected to a terminal 108. At the time of test, test signals TCK, TMS, TDI,
The connector 110 to which TDO is transmitted is the test LSI 11
2 is connected to a TAP (test access port) 115 in the STA 2.

FIG. 23 is a side view of a printed circuit board on which the above-described test boundary scan card is mounted. In the figure, a plurality of RAM module connectors 116 _{1 to} 116 _m are mounted on a
A control circuit 118 and the like for controlling the access of M and the like are attached, and the control circuit 118 and each of the RAM module connectors 116 _{1 to} 116 _m are interconnected by a bus. During the test, test boundary scan cards 120 _{1 to} 120 _m having the structure shown in FIG. 22 are inserted and connected to the RAM module connectors 116 _{1 to} 116 _{m, respectively} . The test signal connectors 110 of the test boundary scan cards 120 _{1 to} 120 _m are connected in cascade by a test cable 122 and connected to a tester (not shown). Further, a tester is connected to an external connector 124 provided on the board 114, and is connected to the control circuit 118 via the external connector 124.

In this embodiment, a RAM module card,
It is not necessary to provide a terminal for use only during a test in each of the RAM module connectors, and it is not necessary to provide a signal line for a test signal on the printed circuit board. FIG.
FIG. 4 shows a schematic configuration diagram of a sixth embodiment of the present invention. In the figure,
An LSI 32 and a RAM module connector 16 are mounted on the printed circuit board 10. The wiring network 1 is provided between the RAM module connector 16 and the LSI 32.
8, 20 are connected. LSI32 has LS
A plurality of cascade-connected boundary lease cells 33, which are standard test circuits, are embedded in the outermost periphery of the I circuit.

The tester connection card 130 is inserted into the RAM module connector 16. The tester connection card 130 connects terminals of the wiring network 18 connected to the LSI 32 and the like in the connector 16 to a tester (not shown) via a cable 132. According to the circuit diagram of FIG.
The test of the wiring network 18 will be described. The wiring networks 18 ₁ to 18 _n are connected to the tester 140 via the RAM module connector 16, the tester connection card 130, and the cable 132 by the tester connection card 40.
0 by can be tested for wiring network 18 ₁ ~ 18 _n respectively health. Boundary lease cancel 33 _{1 to} 3 in this case
Test signal to be output from the 3 _n is the same as that shown in FIG.

In the above embodiment, the tester connection card 130 is inserted into the plurality of RAM module connectors 16 provided on the printed circuit board and connected to the tester 140 by the cables 132. Cable lines are required,
And the workability deteriorates. In such a case,
Instead of the tester connection card 130, a test multiplexer card as shown in a plan view in FIG. 26 is used. FIG.
6, a terminal (edge connector) 142 is provided on one side of the board 141 inserted into the connector, and the connector 1 to which the cable 132 is connected is provided on one side opposite to the terminal 142.
44 are provided. Each terminal 142 is connected to an input terminal of the multiplexer 146. Multiplexer 1
42 is supplied with an address signal for selection from the tester 140 through the connector 144, outputs a signal supplied to a single input terminal designated by the address signal from its output terminal, and outputs this signal from the connector 144 to the cable. It is supplied to the tester 140 through 132. By using the multiplexer 146 in this manner, the number of signal lines of the cable 132 can be significantly reduced.

FIG. 27 is a block diagram showing a seventh embodiment of the present invention. In this embodiment, an electrical connection test between an LSI and a printed circuit board is performed using a flying probe type in-circuit tester. In the figure, an LSI 200 has lead terminals 202 _{1 to} 202 _N and test terminals TDI and TD.
O, TCK, and TMS are lands 204 _{1 to} 204 which are connection terminals formed on a wiring network of a printed circuit board.
_N and 205 ₁ to 205 ₄ are soldered, respectively. This LSI is an LSI compatible with boundary scan.
And the lead terminals 202 _{1 to} 202 _N are provided with corresponding boundary cancel cells 206 ₁ to 206 _N.
06 _N is connected to the internal logic circuit 208.

Boundary cancel cells 206 _{1 to} 20
6 _N constitute a cascade-connected to the shift register within the LSI 200, the boundary at both ends of the shift register - scan test pins TDI (test data in), the bypass is connected to the TDO (Test Data Out) It is connected to both ends of the register 210.
Each of the test terminals TDI and TDO is connected to an input terminal and an output terminal of the instruction register 212, and each of the test terminals TCK (test clock) and TMS (test mode select) is connected to a TAP (test access port) controller 214. Have been. At the time of the test, the instruction supplied from the test terminal TDI to the instruction register 212 is decoded by the TAP controller 214, and scan control of the boundary scan cells 206 _{1 to} 206 _N is performed.

Tester probe (flying probe)
_{220 A, 220 I, 220 O} , 220 K, 220 S , respectively, the stage 222 _A which moves in the XYZ-axis direction by a motor _{drive, 222 I, 222 O, 222} K, 222 S
, Is moved to an arbitrary position on the printed circuit board, and the tip of the probe is connected to the lands 204 ₁ to 204 ₁ of the printed circuit board.
204 is contactable to the measurement points in such lands provided in the middle of the _N and 205 ₁ to 205 ₄ and wiring network. These probes input and output signals to and from the contacted measurement points.

The system control unit 224 controls the entire tester.
I do. The drive control unit 226 controls the system control unit 224.
The drive unit 228 of each probe according to control_A, 228_I, 2
28 _O, 228_K, 228_STo control the stage 22
2_A, 222_I, 222_O, 222_K, 222_SEach
Move them in any direction. The BS control unit 230
Supply to the terminal TCK according to the control of the system control unit 224.
A test clock is generated and supplied to terminal TMS.
Generates the mode selection signal for the test
The signal is supplied to the measurement / input control unit 232.

The input data storage section 234 stores a test signal in advance, reads out a test signal to be supplied to the terminal TDI under the control of the system control section 224, and supplies it to the measurement / input control section 232. The measurement / input control unit 232 controls each probe 22 according to the control of the system control unit 224.
_{0 A, 220 I, 220 O} , 220 K, 220 S connected to the measurement / input section _{236 A, 236 I, 236 O} , 2
The input and output of each of 36 _K and 236 _S are switched.

Thus, a test signal is supplied from the input data storage unit 234 to the input probe via the measurement / input control unit 232 and the input measurement / input unit, and the output probe is output from the output measurement / input unit. The signal of the test result is supplied to the measurement data storage unit 238 via the measurement / input control unit 232 and stored therein. The test result signal stored in the measurement data storage unit 238 is input to the input data storage unit 234.
The comparison result is compared with the test signal stored in the output unit 242, and the comparison result is output from the output unit 242 for display or printout.

[0059] When performing electrical connection test between the LSI and the printed circuit board, the probe 220 _I soldered connected in contact with the land 205 ₁ to the test terminal TDI of the LSI of the test terminal TD of LSI200 probe 220 _O
O to contacting the land 205 ₂ soldered connections,
Probe 220 _K is brought into contact with the land 205 ₃ soldered connection to the test terminal TCK of LSI, the probe 2
20 _S is brought into contact with the land 205 ₄ soldered connection to the test terminal TMS of LSI, and supplies a test signal from the test terminal TDI. In addition, the probe 220 _A
Each of the lands 204 ₁ to 204 ₁ of the printed circuit board to which the lead terminals 202 _{1 to} 202 _{N of the} I200 are connected by soldering.
204 is contacted sequentially _N, read the test result signal from the probe 220 _A.

This will be described in detail with reference to FIG. As shown in FIGS. 28A and 28B, the probe 22
0 _I and 220 _S are moved to lands 205 ₁ and 205 _4.
Similarly, the probes 220 _O and 220 _K are also brought into contact with the lands 205 ₂ and 205 ₃ . Then, FIG.
As shown in (A), a test signal is input from a test terminal TDI to shift the boundary cancel cells 206 _{1 to} 206 _N. When the test signal is shifted to the last boundary scan cell, an update is instructed from the test terminal TMS as shown in FIG. 28B, and output of all boundary scan cells 206 _{1 to} 206 _N is instructed. Also, as shown in FIGS. 28 (B) and (E), the probes 220 _A and 220 _O are also moved and the lands 204 ₁ and 20 _O are moved.
5 is ₂ to contact. Then, after the update, read the test result signal output from the lands 204 ₁ probe 220 _A.

Next, as shown in FIG.
220_ATo move the land 204 _TwoContact. This
At the same time, as shown in FIG.
And a test signal is input thereto.
₁~ 206_NIs shifted to the up position shown in FIG.
After date, probe 220_ALand 204_TwoOutput
Read the test result signal. This test signal input and
Boundary cancel 206₁~ 206_NShift
Sometimes, as shown in FIG. _OOrchid
C 205_FourRead test signal shifted out of
You. This probe 220_AMove and read
Bu 220_ABut land 204_NIs repeated until.
If this test result signal matches the input test signal
The connection between the LSI terminal and the land of the printed circuit board is good.
It is confirmed that there is.

As described above, by using the boundary scan circuit composed of the boundary scan cells 206 _{1 to} 206 _N and the TAP controller 214 in the LSI 200, the internal logic circuit 20 of the LSI 200 can be used.
By operating the probe and bringing it into contact with the terminal without operating the device 8, the test of the connectivity between the lead terminal of the LSI and the land of the wiring of the printed circuit board can be performed in a short time, and the internal logic circuit 208 can be operated. Since the operation is not performed, the test signal can be easily generated. Further, in this embodiment, the connectivity test between the plurality of terminals of the integrated circuit and the plurality of wirings of the printed circuit board is performed by sequentially moving the output probe and making contact with the wiring of the printed circuit board to perform measurement. It can be performed.

In this embodiment, a test signal having the pattern shown in FIG. 6 can be used. Pattern shown in Figure 6, the test signal P ₁ to P _n of the pattern number 1 Boundary - when shifted to scan 206 ₁ -206 _N, the remaining boundary scan at a high level output only Boundary-Scan 206 ₁ 206 ₂ -20
6 _N is a low level output. When shifted similarly test signals P ₁ to P _n of the pattern No. 2, the remaining boundary scan 206 ₂ -206 _N at the low-level output only Boundary-Scan ₂₀₆₁ is a high-level output, the two patterns Is set as one set, and a test for one terminal (wiring network) is performed. Similarly, for each of the boundary lease cancellations 206 _{2 to} 206 _N , two different levels of output are output from the remaining boundary lease cancellation.

If the test result signal level read by the probe 220 _A at the time of setting the test signal of the pattern number 1 is the same high level as the set level of the boundary lease cancel 206 ₁ , the lead terminal 202 of the LSI 200
Interconnection between ₁ and the land 204 ₁ is determined to be normal, it is determined as abnormal if different. If it is determined that the abnormal pattern number 2 of the test signal setting probe 220 _A at the read test result signal level boundary scan 206 ₁ set level and the same low level if it lead terminal 202 ₁ and the land at the time 204 ₁ connected to the defective lead terminals 202 ₁ if contrary to the test result signal level is a high level, it is determined that the lands 204 ₁ is short-circuited with other lead terminal. Other land 204 ₂
The same applies to ２０４204 _N.

As described above, a test signal of a different level from that of the other boundary lease cancels is set only for the boundary lease cancel corresponding to the wiring to which the output probe is connected. It is possible to easily test the connection state of the wiring connected to the probe from the test result signal. When the test signal of the pattern shown in FIG. 6 is used, FIGS. 29 (A) and (B)
As shown in, by moving the probe 220 _I, 220 _S into contact with the land 205 _1, 205 _4, similarly probe 220 _O, 220 _K also brought into contact with the land 205 _2, 205 _3. Then, enter the test signal P ₁ to P _n of the pattern number 1 from the test terminal TDI as shown in FIG. 29 (A) Boundary - shifting the scan 206 ₁ -206 _N. When the test signal is shifted to the last boundary scan cell, an update is instructed from the test terminal TMS as shown in FIG. 29B, and an output of all the boundary scan cells 206 _{1 to} 206 _N is specified. Further, as shown in FIGS. 29B and 29D, the probes 220 _A and 220 _O are also moved so that the lands 204 ₁ and 20 _O are moved.
5 is ₂ to contact. Then, after the update, read the test result signal output from the lands 204 ₁ probe 220 _A.

Next, enter the test signal P ₁ to P _n of the pattern number 2 from the test terminal TDI boundary as shown in FIG. 29 (A) - to shift the scan 206 ₁ -206 _N. When the test signal is shifted to the last boundary scan cell, an update is instructed from the test terminal TMS to output all the boundary scan cells 206 _{1 to} 206 _N as shown in FIG. 220 _a, 220 _O also read the test result signal output from the lands 204 ₁ probe 220 _a without moving.

[0067] Then, by moving the probe 220 _A is brought into contact with the land 204 _2, and inputs the test signal from the test terminal TDI Boundary - scan 206 20 ₁ to 20
Shift 6 _N and proceed to test land 204 ₂ . The probe for measurement is the probe 22 in the above embodiment.
Although it is only 0 _A , a plurality of measurement probes may be provided.

Next, another embodiment of the electrical connection test between the LSI and the printed circuit board will be described with reference to FIG. In this embodiment switch to enter the measurement / input unit 236 _A is used for input probe 220 _A. First, FIG.
As shown in FIGS. 0 (A) and (E), the probes 220 _A and 22A
0 _S is moved into contact with the land 204 _1, 205 _4, respectively, enter the test signal from the land 204 ₁ (e.g., high level) as shown in FIG. 30 (A), FIG. 30
By performing the update shown in FIG.
Boundary cancel 206 as shown in FIG.
_1. Boundary cancel 206 ₁ to 2
06 _N is shifted. In addition, FIG.
And probe 220 _O also moved as shown in (F) placed in contact on the land 205 _2.

Further, as shown in FIG.
Input a test signal (for example, low level) from 04 ₁
The update shown in FIG. 30E is performed, and this is
Boundary cancel 206 as shown in FIG.
_1. Boundary cancel 206 ₁ to 2
06 _N is shifted. During this shift, the test terminal TD
Signal previously entered as shown in FIG. 30 (F) from O is shifted out, reading it as a test result signal in the probe 220 _O.

Along with the second shift, FIG.
Moving the probe 220 _A as shown in (C) is brought into contact with the land 204 _2, and inputs the test signal from the land 204 ₂ (e.g., high level), by performing the update shown in FIG. 30 (E), this boundary as shown in FIG. 30 (D) - to capture scan 206 _2, boundary - shifting the scan 206 ₁ -206 _N.

Further, as shown in FIG.
Input a test signal (for example, low level) from 04 ₂
The update shown in FIG. 30E is performed, and this is
Boundary cancel 206 as shown in FIG.
_2. Boundary cancel 206 ₁ to 2
06 _N is shifted. During this shift, the test terminal TD
Signal previously entered as shown in FIG. 30 (F) from O is shifted out, reading it as a test result signal in the probe 220 _O. Reading of moving the test result signal of the probe 220 _A, the probe 220 _A is repeated up to the lands 204 _N. If this test result signal matches the input test signal, it is confirmed that the connection between the terminal of the LSI and the land of the printed circuit board is good.

In this embodiment, the input probe is sequentially moved and brought into contact with the wiring of the printed circuit board to supply a test signal, so that a plurality of terminals of the integrated circuit and a plurality of wirings of the printed circuit board are connected. A connectivity test can be performed.

[0073]

According to the first aspect of the present invention, there is provided a method for testing a printed circuit board provided with a connector for a memory module on which a memory module on which a memory chip is mounted is mounted. A resistance module is mounted on the memory module connector, each terminal of the connector is terminated, a probe of a measuring instrument is connected to each terminal of the memory module connector, and current / voltage characteristics are measured to perform a test.

As described above, a connection failure or short circuit of the wiring network connected to each terminal of the memory module connector can be detected from the current / voltage characteristics, and the connection state test of the wiring network can be performed. According to a second aspect of the present invention, there is provided a method for testing a printed circuit board provided with a memory module connector on which a memory module on which a memory chip is mounted is mounted, wherein a wiring network is provided to the memory module connector on the printed circuit board. The integrated circuit connected by the above has a boundary scan circuit, a probe of a measuring instrument is connected to each terminal of the connector for the memory module, and a test signal is outputted from the boundary scan circuit and received by the measuring instrument. And conduct the test.

As described above, by connecting the boundary scan circuit and the measuring device to both ends of the wiring network connected to each terminal of the memory module connector, the test signal output from the boundary scan circuit can be measured. To test the connection state of the wiring network. According to a third aspect of the present invention, in the method for testing a printed circuit board provided with a memory module connector on which a memory module having a memory chip mounted thereon is mounted, a wiring network is provided on the printed circuit board to connect the memory module connector. Has a boundary scan circuit, connects between the two terminals of the memory module connector, and performs a test using the boundary scan circuits connected to both ends of the wiring network.

As described above, by connecting and folding between the two terminals of the memory module connector, the wiring network connected by the folding is connected to the boundary scan circuit at both ends thereof. A test signal is output from the scan circuit, and the test signal is received by the other boundary scan circuit, so that the connection state of the wiring network can be tested.

According to a fourth aspect of the present invention, in the method for testing a printed circuit board according to the third aspect, a folded card for connecting each of the two terminals of the memory module connector is inserted into the memory module connector. The two terminals of the connector are connected.

As a result, it is possible to fold the terminal with a normal connector for a memory module in which each terminal is open when the card is not inserted. The invention according to claim 5 is
4. The method for testing a printed circuit board according to claim 3, wherein the memory module connector is of a self-folding type that connects between two terminals when the memory module is not mounted.

For this reason, the memory module can be folded back by the connector for the memory module in a non-mounted state, and the number of test steps can be greatly reduced. According to a sixth aspect of the present invention, there is provided a method for testing a printed circuit board provided with a memory module connector on which a memory module on which a memory chip is mounted is mounted, wherein a wiring network is provided to the memory module connector on the printed circuit board. Integrated circuit having a boundary scan circuit, a boundary scan circuit provided with the boundary scan circuit mounted on the connector for the memory module, and a boundary scan circuit connected to both ends of the wiring network Perform the test using.

For this reason, the boundary scan circuit is connected to both ends of the wiring network connected to each terminal of the connector for the memory module, a test signal is output from the boundary scan circuit of the integrated circuit, and the boundary scan circuit is connected to the boundary scan circuit. A test signal can be received by the Dally scan circuit to test the connection state of the wiring network. 8. A method for testing a printed circuit board on which an integrated circuit having a boundary scan circuit is mounted, wherein the printed circuit board is connected to a terminal connected to each of a plurality of boundary scan cells of the integrated circuit. A test signal supplied to the integrated circuit from the input probe by moving the input and output probes to and from the plurality of wires;
A test is performed by comparing with a test result signal measured by the output probe.

As described above, by using the boundary scan circuit in the integrated circuit, it is possible to test the connectivity between the lead terminals of the integrated circuit and the wiring of the printed circuit board without operating the internal logic circuit of the integrated circuit. Can be performed in a short time by moving the probe, and the test signal can be easily generated because the internal logic circuit is not operated. Claim 8
In the printed circuit board testing method according to the present invention, the timing at which the output probe is moved and brought into contact with a plurality of wirings of the printed circuit board to perform the measurement is defined by the boundary lease cancellation. Synchronize with the signal output timing.

Thus, by sequentially moving the output probe and bringing the output probe into contact with the wiring of the printed circuit board to perform the measurement, the connectivity test between the plurality of terminals of the integrated circuit and the plurality of wirings of the printed circuit board is performed. It can be performed. According to a ninth aspect of the present invention, in the printed circuit board testing method according to the seventh aspect, the timing of supplying the test signal by moving the input probe to contact the plurality of wirings of the printed circuit board, The timing is synchronized with the signal fetch timing to the boundary lease cancel.

Thus, by sequentially moving the input probe and making contact with the wiring of the printed circuit board to supply the test signal, the connection between the plurality of terminals of the integrated circuit and the plurality of wirings of the printed circuit board is established. Sex tests can be performed.
According to a tenth aspect of the present invention, in the printed circuit board testing method according to any one of the seventh to ninth aspects, the test signal includes only a boundary lease cancel corresponding to a wiring connected to the output probe. At one of the high level and the low level, the other pluralities of the boundary lease cancel are set to the other level, and then the boundary lease cancel corresponding to the wiring connected to the output probe is performed. Only at the other level,
Other multiple boundary lease cancellations are set to one level.

As described above, since a test signal of a different level from that of the other boundary lease cancels is set only for the boundary lease cancel corresponding to the wiring to which the output probe is connected, the measurement is performed by the output probe. It is possible to easily test the connection state of the wiring connected to the probe from the test result signal.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of the present invention.

FIG. 2 is a circuit diagram of the present invention.

FIG. 3 is a characteristic diagram for explaining the present invention.

FIG. 4 is a schematic configuration diagram of the present invention.

FIG. 5 is a circuit diagram of the present invention.

FIG. 6 is a signal waveform diagram for explaining the present invention.

FIG. 7 is a schematic configuration diagram of the present invention.

FIG. 8 is a circuit diagram of the present invention.

FIG. 9 is a signal waveform diagram for explaining the present invention.

FIG. 10 is a plan view of a folded card.

FIG. 11 is a schematic configuration diagram of the present invention.

FIG. 12 is a diagram illustrating a connector.

FIG. 13 is a diagram illustrating a connector.

FIG. 14 is a diagram illustrating a connector.

FIG. 15 is a circuit diagram of the present invention.

FIG. 16 is a schematic configuration diagram of the present invention.

FIG. 17 is a circuit diagram of the present invention.

FIG. 18 is a plan view of a RAM module card.

FIG. 19 is a plan view of a test boundary scan card.

FIG. 20 is a circuit configuration diagram of a printed circuit board.

FIG. 21 is a plan view of a RAM module card.

FIG. 22 is a plan view of a test boundary scan card.

FIG. 23 is a side view of a printed circuit board.

FIG. 24 is a schematic configuration diagram of the present invention.

FIG. 25 is a circuit diagram of the present invention.

FIG. 26 is a plan view of a multiplexer card.

FIG. 27 is a configuration diagram of an embodiment of the present invention.

FIG. 28 is a control timing chart of the present invention.

FIG. 29 is a control timing chart of the present invention.

FIG. 30 is a control timing chart of the present invention.

[Explanation of symbols]

10 printed circuit board 12,14,32,34 LSI 16,46 RAM module connectors 18, 20 interconnect network 22 test resistor module 24 meter _{26,220 A, 220 I, 220 O} , 220 K, 22
0 _S probe 33, 35, 206 _{1 to} 206 _N Boundary lease cancel 36 Tester 60 Boundary scan card for test 62 LSI for test 65 TAP 70, 78 Substrate 76 RAM chip 200 LSI 202 _{1 to} 202 _N lead terminal 204 ₁ to 204 _N , 205 _{1 to} 205 ₄ lands 208 Internal logic circuit 210 Bypass register 212 Instruction register 212 214 TAP controller 222 _A , 222 _I , 222 _O , 222 _K , 222 _S
Stage 224 system control section 226 the drive control unit _{228 A, 228 I, 228 O} , 228 K, 228 S
Drive unit 230 BS control unit 232 Measurement / input control unit 234 Input data storage unit 236 _A , 236 _I , 236 _O , 236 _K , 236 _S
Measurement / input section 238 Measurement data storage section 240 Comparison section 240 242 Output section TDI, TDO, TCK, TMS Test terminal

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI G01R 31/28 V

Claims (10)

[Claims] 1. A method for testing a printed circuit board provided with a memory module connector on which a memory module having a memory chip mounted thereon is mounted, wherein a test resistor module provided with a plurality of terminating resistors is connected to the memory module connector. A printed circuit board test characterized by mounting and terminating each terminal of the connector, connecting a probe of a measuring instrument to each terminal of the memory module connector, measuring current / voltage characteristics, and performing a test. Method. 2. A method for testing a printed circuit board provided with a memory module connector on which a memory module on which a memory chip having a memory chip is mounted is mounted, wherein the memory module is connected to the memory module connector on the printed circuit board by a wiring network. The integrated circuit has a boundary scan circuit, connects a probe of a measuring instrument to each terminal of the connector for the memory module, outputs a test signal from the boundary scan circuit, receives the test signal from the measuring instrument, and performs a test. A test method for a printed circuit board, characterized in that it is performed. 3. A method for testing a printed circuit board provided with a memory module connector on which a memory module on which a memory chip having a memory chip is mounted is mounted, wherein the memory module connector is connected to the memory module connector on the printed circuit board by a wiring network. The integrated circuit has a boundary scan circuit, connects two terminals of the memory module connector, and performs a test using the boundary scan circuit connected to both ends of the wiring network. Test method for printed circuit boards. 4. The method for testing a printed circuit board according to claim 3, wherein a folded card for connecting between the two terminals of the connector for the memory module is inserted into the connector for the memory module and between the two terminals of the connector. A method for testing a printed circuit board, comprising: 5. The printed circuit board test method according to claim 3, wherein the memory module connector is of a self-folding type that connects between two terminals when the memory module is not mounted. Test method. 6. A method for testing a printed circuit board provided with a memory module connector on which a memory module on which a memory chip having a memory chip is mounted is mounted, wherein the memory module is connected to the memory module connector on the printed circuit board by a wiring network. The integrated circuit has a boundary scan circuit, a boundary scan card provided with the boundary scan circuit is mounted on the memory module connector, and a test is performed using the boundary scan circuit connected to both ends of the wiring network. A test method for a printed circuit board. 7. A method of testing a printed circuit board on which an integrated circuit having a boundary scan circuit is mounted, wherein a plurality of wirings of the printed circuit board are connected to terminals communicating with a plurality of boundary scan cells of the integrated circuit. The input and output probes are moved until they come into contact with each other, and the test is performed by comparing the test signal supplied from the input probe to the integrated circuit with the test result signal measured by the output probe. A test method for a printed circuit board, characterized in that: 8. The method for testing a printed circuit board according to claim 7, wherein a timing at which the output probe is moved and brought into contact with the plurality of wirings of the printed circuit board to perform measurement is determined from the boundary lease cancellation. A method for testing a printed circuit board, wherein the method is synchronized with the signal output timing of the printed circuit board. 9. The test method for a printed circuit board according to claim 7, wherein the timing of supplying the test signal by moving and contacting the input probe with a plurality of wirings of the printed circuit board is determined. A method for testing a printed circuit board, wherein the method is synchronized with the timing of taking in a signal to cancel. 10. The test method for a printed circuit board according to claim 7, wherein the test signal is at a high level and a low level only for a boundary scan cell corresponding to a wiring connected to the output probe. One of the levels is set to be the other level for the other plurality of boundary lease cancellations, and then only the boundary lease cancellation corresponding to the wiring connected to the output probe is set to the other level. A method for testing a printed circuit board, wherein the level is set to one level in a plurality of other boundary lease cancellations.