JPH10178785A - Null-voltage circuit and inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the number of components and power loss as small as possible in a null-voltage circuit, which temporarily makes the output voltage null and thereby lower the cost and size of the device. SOLUTION: In a null-voltage switching PWM inverter 13, a null-voltage circuit 2 has a first and a second switching means 11, 12 which are composed of semiconductor switches S1 , S2 and diodes D1 , D2 , which are antiparallelly connected to the semiconductor switches S1 , S2 respectively, and a capacitor C2 for resonance is connected across a DC power supply 1 through the first switching means 11. On the other hand between a connection between the first switching means 11 and the capacitor C2 for resonance and a mid-point M of the DC power supply 1, a reactor L1 for resonance is connected through the second switching means 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a zero voltage circuit for temporarily converting a DC voltage to zero voltage and outputting the zero voltage, and an inverter provided with the zero voltage circuit.

[0002]

2. Description of the Related Art In recent years, a distributed power source and a commercial power source using photovoltaic power have been interconnected, and when the power cannot be provided by the distributed power source alone, the power is supplied from the grid side. A photovoltaic power generation system has been developed which allows reverse power flow to commercial power when the amount of power generated by photovoltaic power generation is excessive.

In such a photovoltaic power generation system, in order to convert DC power from a solar cell disposed on a roof of a house or the like into AC power synchronized with a commercial power supply, the output is changed by changing a pulse width. Is used. In this PWM inverter, for example, 20 k
Since switching is performed at a high frequency such as Hz, switching noise (radiation noise) is generated, and there is a possibility that another device may be damaged.

[0004] As a method of reducing such switching noise and switching loss, a so-called PWM inverter using so-called zero-voltage switching, which performs switching of a PWM inverter in a state where an input voltage is set to zero volt, has been studied.

FIG. 7 is a configuration diagram of such a zero voltage switching PWM inverter.

[0006] In the figure, the DC power source 1 is composed of a solar cell, 2 ₀ parallel resonance DC link (Pararell Resonant D
C Link) zero voltage circuit composed of the circuit, 3 is an inverter circuit for converting the synchronized AC power and system power supply 4, 5 ₀
Is a control circuit for controlling the zero-voltage circuit 2 ₀ and the inverter circuit 3.

[0007] Zero-voltage circuit 2 ₀ is resonant reactor L _1, resonance capacitor C _1, C _2, diodes D ₁ to D ₄
And a semiconductor switch S _{1 to} S ₃ for temporarily reducing the input voltage of the inverter circuit 3 to zero volts by resonance operation. When the inverter circuit 3 is switched, the input voltage of the inverter circuit 3 becomes zero voltage. the semiconductor switch S ₁ to S ₃ is controlled by the control circuit 5 ₀ as.

The inverter circuit 3 is a PWM control type inverter circuit for controlling the output by changing the pulse width. The inverter circuit 3 is connected in parallel with _four semiconductor switches S _{4 to} S ₇ and the respective semiconductor switches S _{4 to} S _7. and a diode D ₅ to D _8, includes a reactor L _2, L ₃ for smoothing the output current,
Each semiconductor switch S ₄ to S ₇ is intended to be on-off controlled by a switching pulse from the control circuit 5 _0.

[0009] The control circuit 5 ₀ has, for example, a CPU and a logic circuit, feeds back the output current of the inverter circuit 3, a sine wave and the semiconductor switch S ₄ of the inverter circuit 3 and a reference triangular wave ~S based thereon to form a PWM pulse for controlling the _7, and outputs the each semiconductor switch S ₄ to S ₇ of the delayed PWM pulses the PWM pulse by a predetermined time delay as a switching pulse, also, rising and falling of the PWM pulse as a zero volt input voltage of the inverter circuit 3 starts a resonance operation in response to the falling, and outputs a switching signal for controlling the semiconductor switches S ₁ to S ₃ of the zero voltage circuit 2 _0, thereby, At the time of switching of the inverter circuit 3, that is, at the time of rising and falling of the switching pulse In addition, the input voltage of the inverter circuit 3 is set to zero volt.

[0010]

[SUMMARY OF THE INVENTION However, such a zero voltage circuit 2 ₀ in the prior art requires at least three semiconductor switches S _1, S _2, S _3, components and power loss is increased, There are disadvantages that the cost is high and the size is large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to reduce the number of parts and power loss as much as possible, to reduce the cost, and to further reduce the size. .

[0012]

In order to achieve the above-mentioned object, the present invention is configured as follows.

That is, the zero voltage circuit of the present invention has first and second switch means in which rectifier elements are connected in anti-parallel to the switch element, and the first switch means is provided between both ends of the power supply means. A resonance reactor is connected via a second switch between a connection point between the first switch and the resonance capacitor and a midpoint of the power supply. I have.

The power supply means may be constituted by connecting a plurality of power supplies, and a connection portion of the power supply may be provided at the midpoint of the power supply. Alternatively, the power supply means may be connected in parallel to a plurality of voltage dividing elements such as capacitors. A power supply may be connected, and a connection portion of the voltage dividing element may be the midpoint of the power supply.

An inverter according to the present invention includes a zero-voltage circuit according to the present invention and an inverter circuit that converts a direct current from the zero-voltage circuit into an alternating current. The zero-voltage circuit operates when the inverter circuit switches. Is set to zero voltage.

According to the zero voltage circuit of the present invention, the resonance reactor is connected via the second switch between the connection point between the first switch and the resonance capacitor and the midpoint of the power supply. That is, one end of the resonance reactor is connected to a semiconductor switch as in the conventional example of FIG.
Since one end of the resonance reactor is connected to the midpoint of the power supply of the power supply instead of being connected to the negative electrode of the DC power supply through a parallel circuit of a diode and a capacitor, the semiconductor switch and the semiconductor switch that were conventionally required The number of capacitors and diodes in parallel with each other can be reduced, the cost can be reduced, the power loss can be reduced, and the size can be further reduced.

Further, according to the inverter of the present invention, since the zero voltage circuit of the present invention is provided, the power loss can be reduced, the efficiency can be improved, and the cost and size can be reduced. it can.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a configuration diagram of a main part of a photovoltaic power generation system provided with a zero voltage circuit according to one embodiment of the present invention. Assign a sign.

The photovoltaic power generation system of this embodiment
A DC power supply 1 composed of a solar cell and a zero-voltage switching PWM inverter 13 are provided.
Inverter circuit 3 for converting to AC power synchronized with
And a zero voltage circuit 2 for setting the input voltage of the inverter circuit 3 to zero voltage when the inverter circuit 3 is switched.
And a control circuit 5 for controlling the inverter circuit 3 and the zero voltage circuit 2.

The inverter circuit 3 is a PWM control type inverter circuit for controlling the output by changing the pulse width. The inverter circuit 3 is connected in parallel with _four semiconductor switches S _{4 to} S ₇ and the respective semiconductor switches S _{4 to} S _7. and a diode D ₅ to D _8, includes a reactor L _2, L ₃ for smoothing the output current,
Each of the semiconductor switches S _{4 to} S ₇ is controlled to be turned on / off by a switching pulse from the control circuit 5.

In this embodiment, in order to reduce the number of components and the power loss of the zero voltage circuit 2 as much as possible, to reduce the cost and to further reduce the size, the zero voltage circuit 2 is constructed as follows. Make up.

That is, the zero voltage circuit 2 of this embodiment is formed by connecting the _first and _second diodes D ₁ and D ₂ in antiparallel to the first and _second semiconductor switches S ₁ and S _2. Having first and second switch means 11 and 12,
A resonance capacitor C2 is connected between both ends of the DC power supply 1 constituting the power supply means via the first switch means 11, and a first and a _second voltage dividing element are connected in parallel with the DC power supply 1. The capacitors C ₃ and C ₄ are connected to each other, and the connection between the two capacitors C ₃ and C ₄ is set as the power supply midpoint M. The connection between the first switch means 11 and the resonance capacitor C ₂ and the power supply midpoint M between, connecting the resonant reactor L ₁ through the second switching means 12.

Here, the first and second capacitors C ₃ and C ₄
Is sufficiently large, and the voltage at the power supply midpoint M, which is the connection portion, is maintained at に of the voltage of the DC power supply 1.

The conventional zero voltage circuit 2 ₀ shown in FIG.
In this embodiment, one end of the resonance reactor L ₁ is connected to the negative electrode of the DC power supply 1 via a parallel circuit of the semiconductor switch S ₃ , the diode D ₃ and the resonance capacitor C _1. in, one end of the resonant reactor L _1, connected to a power supply midpoint M, as described below, the voltage across Vc ₂ of the resonance capacitor C _2, the voltage of the DC power source 1 1 /
2 are resonated.

Next, the operation of the zero voltage circuit 2 of this embodiment will be described with reference to the waveform diagram of FIG. 2 and the operation mode diagram of FIG.

[0027] Note that, in FIG. 2, (A) a current I _L flowing through the resonant reactor L _1, (B) is the voltage across Vc ₂ of the resonance capacitor C _2, (C) the PWM pulse, (D) is Rising and falling detection pulses of the PWM pulse,
(E) and (F) show the first and second semiconductor switches S ₁ and S ₂
, (G) and (H) are operating states of the first and second diodes D ₁ and D ₂ , (I) is a delayed PWM pulse for switching of the inverter circuit 3, and (J) is Each operation mode is shown, and in FIG.
(A) to (E) show respective states of mode 1 to mode 5.

The initial state of the zero voltage circuit 2, i.e., in the mode 1, the first semiconductor switch S ₁ is turned on, the second semiconductor switch S ₂ is turned off, the voltage across the resonant capacitor c ₂ vc ₂ is the voltage of the DC power source 1, current I _L flowing through the resonant reactor L ₁ is zero.

Next, when turned on second switch S ₂ is in response to the rise or fall of the PWM pulse, resonant reactor L ₁ is energized, the current I _L flowing through the reactor L ₁ is linearly increased (mode 2), when to start the resonant operation first off semiconductor switch S ₁ (mode 3), the current I _L flowing through the resonant reactor L _1, resonant capacitor C ₂ is discharged as the voltage across Vc ₂ is lowered Te, the voltage of the power supply midpoint M, i.e., when it is half the voltage of the DC power source 1, the voltage across the resonant reactor L ₁ is zero, resonant reactor L current I _L flowing through the _primary becomes maximum point, further,
From transients LC, it drops to the voltage across Vc ₂ of the resonance capacitor C ₂ becomes zero volts, the current I _L flowing through the resonant reactor L ₁ becomes zero when it is zero volts.

When the voltage Vc ₂ across the resonance capacitor C ₂ becomes zero volts, the second diode D ₂ conducts (mode 4), the capacitor C ₂ is charged, and the voltage Vc ₂ across it increases. when it is the voltage of the power supply midpoint M, the current I _L flowing through the resonant reactor L ₁ becomes minimum point.

Further, when the resonance capacitor C ₂ is charged and the voltage Vc ₂ across the resonance capacitor C ₂ reaches the voltage of the DC power supply 1,
The first diode D ₁ is conducting (mode 5), the current I _L flowing through the resonant reactor L ₁ is zero decreases, first, the second diodes D _1, D ₂ are turned off initial state Return. Note that the first semiconductor switch S ₁ is in mode 5
In in period T _1, is turned on, the second semiconductor switch S _2, in the period T ₂ of the mode 4 or mode 5 is turned off.

As described above, as shown in FIG. 2B, the output voltage of the zero voltage circuit 2 is instantaneously set to zero voltage, and the timing of this zero voltage, that is, FIG.
At the rising and falling timings t ₁ and t ₂ of the delayed PWM pulse shown in FIG.
Zero volt switching of the inverter circuit 3 is performed.

FIG. 4 is a block diagram of a main part of the control circuit 5 for performing such control. The PWM pulse shown in FIG.
As shown in FIG. 2I, the delay circuit 14 delays the signal by td ₁ and supplies it to the semiconductor switches S ₄ and S ₇ of the inverter circuit 3 as switching pulses.
The signal is inverted at 5 and supplied to the semiconductor switches S ₅ and S ₆ of the inverter circuit 3 as switching pulses, and the semiconductor switches S _{4 to} S ₇ are switched at the rising and falling timings.

As shown in FIG. 2D, the rising and falling detecting circuit 16 detects the rising and falling of the PWM pulse, and the detected pulse is delayed by td _{2 in the} delay circuit 17. The delay circuit 1 is supplied to the set terminal of the first flip-flop 18 and
9 and is applied to the reset terminal of the first flip-flop 18 after being delayed by td _3,
The output of 8 controls the first semiconductor switch S ₁ shown in FIG.

Further, a rise / fall detection circuit 1
6 is supplied to the second flip-flop 2 as it is.
0, and is applied to the reset terminal of the second flip-flop 20 after being delayed by td ₄ by the delay circuit 21, and the output of the second flip-flop 20 causes the second flip-flop 20 to output the second signal shown in FIG. of the semiconductor switch S ₂ is controlled.

As described above, in the zero voltage circuit 2 of this embodiment, the parallel circuit of the semiconductor switch S ₃ , the diode D ₃ and the resonance capacitor C ₁ and the diode D ₄ in the conventional example of FIG. Although the first and second capacitors C ₃ and C ₄ are required as voltage dividing elements, the number of components can be reduced, power loss can be reduced, and cost can be reduced. The size can be reduced.

The point at which the output voltage of the zero voltage circuit 2 becomes zero volts varies depending on the load current, and as shown in FIG.
Current Ic ₂ of ₂ becomes a current obtained by superimposing the load current I ₀ which is indicated by a broken line, and the point of zero voltage, as shown by the broken line of FIG. 5 (B), so that the earlier the load current I ₀ . FIG. 5A shows the resonance reactor L _1.
Shows the current I _L.

Then, as another embodiment of the present invention,
The load current I ₀ on the output side of the inverter circuit 3 is detected, and when the load current I ₀ is large, as shown in FIG. 5B, the above-described delay td ₁ is corrected to be short and set as td ₁ ′. Is also good.

FIG. 6 is a block diagram corresponding to FIG. 1 of still another embodiment of the present invention, and portions corresponding to the above-described embodiment are denoted by the same reference numerals.

In the above-described embodiment, the first and second capacitors C ₃ and C ₄ are connected in parallel to the DC power supply 1, and the connection between the capacitors C ₃ and C ₄ is set to the midpoint M of the power supply. in this embodiment, the power supply means, first connected in series, as well as constituted by the second DC power source 1 _1, 1 _2, both supply 1 _1, 1 ₂ of the connecting portion as midsupply M I have.

Other configurations and operations are the same as those of the above-described embodiment.

According to this embodiment, the voltage fluctuation at the power supply midpoint M is reduced, and more stable operation can be realized. Also, if parallel connected capacitors C _3, C ₄ on both the power supply 1 _1, 1 _2, respectively, the less further voltage fluctuation, it becomes stable course.

In the above-described embodiment, the capacitors C ₃ and C ₄ are used as voltage dividing elements. However, as another embodiment of the present invention, a resistor and other voltage dividing elements may be used.

Further, the voltage dividing element or the power supply
The number is not limited to two, and it is needless to say that two or more may be used.

In the above embodiment, the inverter circuit 3
While the input voltage of the inverter circuit 3 provided with a zero-voltage circuit 2, 2 ₁ in the preceding stage was zero voltage, as another embodiment of the present invention is not limited to the inverter circuit 3, for example, DC-DC converter Ya The input voltage of a circuit for performing other switching may be set to zero voltage.

Although the above embodiment has been described with reference to the photovoltaic power generation system, the present invention is not limited to the photovoltaic power generation system.

In the above embodiment, the DC power supply 1
Although a solar cell was used as a battery, a DC power supply such as a battery power supply other than the solar cell may be used.

[0048]

As described above, according to the zero voltage circuit of the present invention, the second switch means is provided between the connection between the first switch means and the resonance capacitor and the midpoint of the power supply means. The resonance reactor is connected through
Since one end of the resonance reactor is connected to the midpoint of the power supply, it is possible to reduce the number of semiconductor switches and capacitors and diodes in parallel with the semiconductor switches, which were conventionally required, thereby reducing costs and reducing power loss. It is possible to further reduce the size.

According to the inverter of the present invention, since the zero voltage circuit of the present invention is provided, the power loss can be reduced and the efficiency can be improved, and the cost and size can be reduced. it can.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a solar power generation system including a zero voltage circuit according to one embodiment of the present invention.

FIG. 2 is a signal waveform diagram for explaining the operation.

FIG. 3 is a mode diagram for explaining the operation.

FIG. 4 is a block diagram of a main part of the control circuit of FIG. 1;

FIG. 5 is a signal waveform diagram corresponding to FIG. 2 of another embodiment of the present invention.

FIG. 6 is a configuration diagram corresponding to FIG. 1 of still another embodiment of the present invention.

FIG. 7 is a configuration diagram of a conventional example.

[Explanation of symbols]

1,1 _1, 1 ₂ DC power supply 2, 2 _1, 2 ₀ zero voltage circuit 3 inverter circuit 5,5 ₀ control circuits 11 and 12 first and second switching means C ₂ resonance capacitor L ₁ resonant reactor C ₃ , C ₄ capacitor (element for voltage division)

Claims (5)

[Claims] 1. A switching device comprising first and second switch means connected in reverse parallel to a rectifier element, and a resonance capacitor connected between both ends of the power supply means via the first switch means. On the other hand, between the connection between the first switch means and the resonance capacitor and the midpoint of the power supply means,
A resonance reactor is connected via the switch means. 2. The zero voltage circuit according to claim 1, wherein the power supply means is configured by connecting a plurality of power supplies, and a connection portion of the power supply is set to the power supply midpoint. 3. The power supply according to claim 1, wherein the power supply means is configured by connecting a power supply to the plurality of voltage dividing elements in parallel, and a connection portion of the voltage dividing element is set to the midpoint of the power supply. Voltage circuit. 4. The zero voltage circuit according to claim 3, wherein said voltage dividing element is a capacitor. 5. The zero voltage circuit according to claim 1, further comprising an inverter circuit for converting a direct current from the zero voltage circuit into an alternating current, wherein the zero voltage circuit performs switching of the inverter circuit. An inverter, wherein the input voltage of the inverter circuit is sometimes set to zero voltage.