JPH10178169A - Single electron transistor - Google Patents

Abstract

(57) Abstract: A single-electron transistor is designed to realize a configuration in which electrons can move in a vertical direction (vertical direction) of a wafer, that is, in a three-dimensional manner, thereby enabling ultra-high integration. SOLUTION: n-Al _0.4 Ga _0.6 As electron supply layer 1
Non-doped Al with a potential barrier layer comprising 3 or 19
_0.2 Ga _0.8 As drain layer 15 and non-doped Al
_A quantum well is formed by sandwiching a first well layer including the _0.2 Ga _0.8 As source layer 17 and the like, and the potential in the first well layer in the quantum well is lower than that of the first well layer. A source electrode that contacts a two-dimensional electron gas layer generated near one interface of the first well layer with a non-doped GaAs island layer 16 as a second well layer that generates a potential well, and the other interface A drain electrode that contacts a two-dimensional electron gas layer generated in the vicinity and a gate electrode that applies a potential to the island layer 16 that is a second well layer are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an improvement in a single-electron transistor utilizing a quantum effect due to the wave nature of electrons.

At present, silicon MOSFETs (metal
Oxide semiconductor field
In the field of effect transistors and compound semiconductor FETs, high integration due to miniaturization is progressing, but there is a limit to the miniaturization, and carriers due to, for example, tunneling due to miniaturization. There is a problem that an undesired quantum effect, such as leakage of, appears.

[0003] In order to solve such a problem, a single-electron transistor, which is one of quantum effect devices utilizing the wave nature of electrons, has been receiving attention.

A single electron transistor can be realized by using a silicon semiconductor or a compound semiconductor, and can operate at room temperature.
Although research and development are being actively carried out, what has appeared so far is a structure in which electrons move in a plane on the wafer, and it is still one step in terms of high integration. In short, the present invention provides one means of addressing such problems.

[0005]

2. Description of the Related Art Generally, a single-electron transistor is composed of a source, a drain, a gate, and an island. Electrons emitted from the source enter the island, the potential of the island containing the electrons increases, and the next electron is emitted. If the island cannot enter the island and the electrons in the island exit the drain, then the next electron can enter from the source, and the entry and exit of such an island is controlled by the gate. It is supposed to.

The above-described single electron transistor is manufactured by processing a wafer surface two-dimensionally, that is, two-dimensionally, by a fine processing technique.

FIG. 9 is an explanatory view of a main part of a single-electron transistor for explaining a conventional technique.
"T. Fujisawa and S. Taruch
a, Extended Abstracts of t
he 1995 International Con
reference on Solid State De
visits and Materials, p. 198
-P. 200 ").

In the figure, (A) is a main part slope showing the structure of a single-electron transistor, (B) is an outline of the potential of the single-electron transistor, 31 and 32 are in-plane gates,
3, 34 and 35 are Schottky gates, 36 is a source,
37 is a drain, 38 is a two-dimensional electron gas (2DEG)
Layer, 39 is a Ga injection line, 40 is a depletion region,
41 indicates a dot (island), W indicates a channel width on processing conditions (the injection position of the Ga injection line), W _ch indicates an effective channel width, and L indicates a channel length.

In this single electron transistor, AlGa
As / GaAs HEMT (high electro
It utilizes a 2DEG layer 38 generated in an n mobility transistor structure.

The in-plane gates 31 and 32 perform Ga implantation using a Ga focused ion beam,
9 to form.

The production of the Schottky gates 33, 34, 35 is realized by applying a usual technique and forming a Schottky electrode made of, for example, Al on the surface.

The width is W due to the in-plane gates 31 and 32.
Is generated, and a dot 41 is formed in the middle of the channel by the Schottky gates 33 and 34. The entrance and exit of electrons in the dots 41 are controlled by the Schottky gate 35.

[0013]

In the above-described conventional single-electron transistor, electrons move planarly on the wafer. However, even with this structure, compared with a normal semiconductor device, , Sufficiently high integration is possible.

However, in a configuration in which electrons move in a plane, it is a matter of course that a certain area is required on a plane, and it is preferable that further integration can be realized with a simple structure. Nor.

In the present invention, it is intended to realize a configuration in which electrons can move in a vertical direction (vertical direction) of a wafer, that is, in a three-dimensional manner, in a single-electron transistor, thereby enabling ultra-high integration.

[0016]

According to the present invention, the required semiconductor layers are stacked so that the single-electron transistor becomes a so-called vertical type, and the whole structure is simplified so that it can be easily manufactured. Is the basis.

As described above, in the single-electron transistor according to the present invention, (1) a potential including a semiconductor layer (for example, the electron supply layers 13 and 19) made conductive by introducing impurities. The quantum well formed by sandwiching the first well layer (for example, the drain layer 15 and the source layer 17) with the barrier layer is compared with the potential of the first well layer in the first well layer in the quantum well. A second well layer (e.g., island layer 16) for generating a lower potential well, and a source electrode (e.g., source) for contacting a two-dimensional carrier gas layer generated near one interface of the first well layer. (E.g., electrode 21) and a drain electrode (eg, drain electrode 22) in contact with a two-dimensional carrier gas layer generated near the other interface, and a gate electrode (e.g., For example, a gate electrode 23), or

(2) In the above (1), the impurity concentration in the semiconductor layer which is contained in the potential barrier layers formed on both sides of the first well layer and made conductive by introducing impurities. Is different on one side and the other, or

(3) In the above (1) or (2),
Non-doped spacer layers (for example, spacer layers 14 and 18) made of the same material as the semiconductor layer are interposed between the semiconductor layer made conductive by introducing impurities and the first well layer. Or characterized by, or

(4) In the above (3), the thickness of the non-doped spacer layer adjacent to both sides of the first well layer is different between one side and the other side. Or

(5) In any one of the above (1) to (4), the non-doped spacer layer of the semiconductor layer which is made conductive by introducing impurities is adjacent on the opposite side to the adjacent side. And a non-doped layer made of the same material as the semiconductor layer.
Characterized in that it comprises an energy band control layer (eg, energy band control layers 12 and 20), or

(6) In the above (5), the non-doped energy contained in the potential barrier layer constituting the quantum well
The band control layer is provided with independent gate electrodes (for example, gate electrodes 25 and 26) for applying a potential to the band control layer.

By adopting the above-mentioned means, in the single electron transistor according to the present invention, the carrier moves in the vertical direction (vertical direction) of the wafer, that is, three-dimensionally. The degree of integration can be much higher than that of the structure in which the carrier moves in a plane on the wafer.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a cutaway side view showing a main part of a required semiconductor layer laminate used to constitute a single electron transistor according to a first embodiment of the present invention.

In the figure, 10 is a substrate (part), 11
Is a buffer layer, 12 is an energy band control layer, 13 is an electron supply layer, 14 is a spacer layer, 15 is a drain layer,
6 is an island layer, 17 is a source layer, 18 is a spacer layer, 19 is an electron supply layer, and 20 is an energy band control layer. It should be noted that the illustrated substrate 10 shows only a part formed into a mesa for isolation between elements. Actually, the substrate 10 extends laterally below the illustrated substrate 10 to form a large number of mesas. Is formed on the wafer.

FIG. 2 is a plan view of a principal part showing a principle single electron transistor in the present invention using the laminate shown in FIG.

In the figure, 21 is a source electrode, 22 is a drain electrode, 23 is a gate electrode, and 24 is a protective insulating film. In the figure, the bonding pad portion of each electrode appears to fly out of the semiconductor portion formed into a mesa for the purpose of element isolation and to float in the air. Through a lead wire drawn out of the substrate and a bonding pad on a substrate (not shown). Of course, in that case, it is necessary to provide an insulating film below the leads on the side surfaces of the mesa-formed semiconductor portion.

FIGS. 3 and 4 are cutaway side views of a main part of a single-electron transistor in a process step for explaining a method of manufacturing the single-electron transistor according to the first embodiment. The process will be described with reference to FIGS.
FIG. 3 is a view cut along a line XX shown in FIG. 2, and FIG. 4 is a view cut along a line YY shown in FIG.

Referring to FIG. 1, 1- (1) molecular beam epitaxial growth (molecul)
By applying an ar beam epitaxy (MBE) method, a buffer layer 11, an energy band control layer 12, an electron supply layer 13, and a spacer layer 1 are formed on a substrate 10.
4, drain layer 15, island layer 16, source layer 1
7. The spacer layer 18, the electron supply layer 19, and the energy band control layer 20 are grown.

The energy band control layer 12 and the energy band control layer 20 correspond to a second embodiment described later.
Required to construct a single electron transistor of
Since it is unnecessary for the single-electron transistor of the first embodiment, it is better not to form it. However, even if it is present, no particular adverse effect occurs.

Here, the main data relating to each semiconductor portion is exemplified as follows. (1) About substrate 10 Material: Semi-insulating GaAs Surface index: (100)

(2) Buffer layer 11 Material: GaAs Thickness: 1 [μm]

(3) Energy band control layer 12 Material: Non-doped Al _0.4 Ga _0.6 As Thickness: 0.1 [μm]

(4) Electron Supply Layer 13 Material: n-Al _0.4 Ga _0.6 As Impurity: Si Impurity concentration: 1 × 10 ¹⁸ [cm ⁻³ ] Thickness: 0.1 [μm]

(5) Spacer layer 14 Material: Non-doped Al _0.4 Ga _0.6 As Thickness: 20 [nm]

(6) Regarding the drain layer 15 Material: Non-doped Al _0.2 Ga _0.8 As Thickness: 20 [nm]

(7) Regarding the island layer 16 Material: non-doped GaAs Thickness: 20 [nm]

(8) Source Layer 17 Material: Non-doped Al _0.2 Ga _0.8 As Thickness: 20 [nm]

(9) Spacer layer 18 Material: Non-doped Al _0.4 Ga _0.6 As Thickness: 20 [nm]

(10) Regarding the electron supply layer 19 Material: n-Al _0.4 Ga _0.6 As Impurity: Si Impurity concentration: 1 × 10 ¹⁸ [cm ^-3 ] Thickness: 0.1 [μm]

(11) Energy band control layer 20 Material: Non-doped Al _0.4 Ga _0.6 As Thickness: 0.1 [μm]

See FIGS. 2, 3 and 4. 2- (1) A portion where a source electrode is to be formed and a portion where a drain electrode is to be formed by applying a resist process in lithography and an electron beam exposure method. Then, a resist film having an opening (notch) at a portion where a gate electrode is to be formed is formed on the surface of the energy band control layer 20.

2- (2) Reactive ion beam etching (reac) using Cl ₂ -based gas as the etching gas
five ion beam etching: RIB
By applying the method E), etching is performed from the surface to the source layer 17 using the resist film as a mask.

2- (3) A portion where a drain electrode is to be formed and a portion where a gate electrode is to be formed by removing the resist film and applying a resist process in lithography and an electron beam exposure method. Then, a resist film having an opening (notch) is formed.

2- (4) Etching from the surface to the island layer 16 is performed using the resist film as a mask by applying the RIBE method using the etching gas as a Cl ₂ -based gas.

After removing the resist film, a resist film having an opening (notch) at a portion where a drain electrode is to be formed is formed by applying a resist process in lithography and an electron beam exposure method. Form.

2- (5) Etching from the surface to the drain layer 15 is performed using the resist film as a mask by applying the RIBE method using the etching gas as a Cl ₂ -based gas.

Through the above steps, the electrode contact surfaces are exposed at the portions where the source electrode is to be formed, the drain electrode is to be formed, and the gate electrode is to be formed.

2- (6) After removing the resist film, a chemical vapor deposition (chemical vapor deposition) is performed.
By applying an evaporation (CVD) method, the entire surface is made of SiO ₂ having a thickness of, for example, 100 nm.
Is formed.

2- (7) By applying a resist process in a lithography technique and an electron beam exposure method, a portion where a source electrode contact window is to be formed, a portion where a drain electrode contact window is to be formed, and a gate electrode contact window A resist film having an opening (notch) in a portion to be formed is formed.

2- (8) Reactive ion etching (reactive) using CHF ₃ gas as an etching gas
By applying the ion etching (RIE) method, the protective insulating film 24 made of SiO ₂ is etched using the resist film as a mask to form a source electrode contact window, a drain electrode contact window, and a gate electrode contact window.

2- (9) The source electrode 21 in contact with the source layer 17 and the drain electrode in contact with the drain layer 15 by applying a resist process, a vacuum deposition method and a lift-off method in the lithography technique. 22, a gate electrode 23 that contacts the island layer 16 is formed.

Here, since the material of the source electrode 21 and the drain electrode 22 and the material of the gate electrode 23 are different, it is necessary to form them separately.
And the drain electrode 22 has a thickness of 30 [nm] / 200.
The gate electrode 23 is made of an Al film having a thickness of 100 nm.

FIG. 5 is an energy band diagram for explaining the operation of the single electron transistor according to the first embodiment.
This is a diagram, and the same symbols as those used in FIGS. 1 to 4 represent the same parts or have the same meanings. In the figure, only the bottom E _{C of the} conduction band is shown for simplicity, and this energy band diagram is viewed from the side taken along the line YY shown in FIG. You can think.

In the figure, (A) shows the bottom of the conduction band when the electron supply layer 13 and the electron supply layer 19 are not doped, and (B) shows the case when the gate voltage V _g = 0. The bottom of the conduction band, (C) is the bottom of the conduction band when the gate voltage V _g > 0, and H ₁ is the spacer layer 18 and the source layer 17.
Hetero interface between, H ₂ is the drain layer 15 and the spacer layer 1
4 shows a hetero interface with each other.

In this single electron transistor, the spacer layer 18 and the electron supply layer 19 form one barrier portion in the quantum well, and the electron supply layer 13 and the spacer layer 14 form the other barrier in the quantum well. Part.

As is clear from (A), the well layer sandwiched between the barrier portions is composed of the source layer 17, the island layer 16,
It is composed of a drain layer 15, of which the island layer 1
The bottom E _C16 of the conduction band at 6 is further depressed, _{leaving more} wells in the well layer.

As is apparent from FIG. 8B, since the electron supply layer 19 and the electron supply layer 13 are actually n-type doped, the energy band bends as shown in FIG. At the hetero interface H ₁ between the spacer layer 18 and the source layer 17 and at the hetero interface H ₂ between the drain layer 15 and the spacer layer 14, two-dimensional electrons leaking from the electron supply layer 19 or the electron supply layer 13 are accumulated. However, the well in the quantum well, that is, the island layer 16 has:
There are no electrons yet.

As is clear from FIG. 7C, the source layer 17
When a voltage of V _g > 0 is applied to the gate electrode 23 that contacts the island layer 16 in a state where a voltage is applied between the source electrode 21 that contacts the drain layer 15 and the drain electrode 22 that contacts the drain layer 15, Since the level of the bottom E _C16 of the conduction band in the island layer 16 decreases, the two-dimensional electrons existing at the hetero interface H ₁ are injected into the island layer 16 by a tunnel effect.

When the above state is reached, the island layer 1
6, the two-dimensional electrons are not injected indefinitely, but the electrons injected into the island layer 16 are further subjected to the tunneling effect to the hetero interface H _2.
Since moving to, the potential of the island layer 16 is lowered again, so that it is able to accept an electron from the hetero interface H _1.

As described above, the movement of electrons from the hetero interface H ₁ to the island layer 16 and from the island layer 16 to the hetero interface H ₂ can be arbitrarily determined depending on whether or not a voltage is applied to the gate electrode 23 contacting the island layer 16. Can be controlled.

FIG. 6 is a plan view showing a main part of a single-electron transistor for describing a second embodiment of the present invention. The same reference numerals as those used in FIGS. 1 to 5 denote the same parts. Or have the same meaning. However, FIG.
The gate electrode indicated by reference numeral 23 in FIG. 5 is referred to as a first gate electrode here.

The difference between the single-electron transistor shown in FIG. 6 and the single-electron transistor described as the first embodiment is that the single-electron transistor which contacts the energy band control layer 20 which has been in the idle state in the first embodiment is different from the first embodiment. The second gate electrode 25 and the energy that was also in the idle state.
Third gate electrode 2 contacting band control layer 12
6 is provided.

FIGS. 7 and 8 are cutaway side views for explaining a single electron transistor according to the second embodiment.
6 shows a plane cut along a line Y1-Y1 in FIG. 6, and FIG. 8 shows a plane cut along a line Y2-Y2 in FIG. The same symbols as those used in FIGS. 1 to 6 represent the same parts or have the same meaning.

According to FIG. 7 and FIG. 8, the second gate electrode 25 contacts the energy band control layer 20 and the third gate electrode 26 contacts the energy band control layer 1.
The structure contacting No. 2 is clear.

In order to manufacture this single electron transistor, the same means as in the process of manufacturing the single electron transistor of the first embodiment described above, that is, the formation of a required semiconductor layer and the selective formation of the semiconductor layer It can be easily realized by means such as etching and formation of an electrode on the semiconductor layer exposed by the etching.

In the single-electron transistor according to the second embodiment, the second gate electrode 25 and the third gate electrode 26
Can control the bending of the energy band by applying a voltage to the device, whereby the device functions can be diversified.

In the present invention, without being limited to the above-described embodiment, many other modifications can be realized. For example, the impurity concentrations in the electron supply layer 13 and the electron supply layer 19 are respectively reduced. It is possible to change the energy band structure and the state of the wave function of the quantum well, and further the characteristics of the single-electron transistor, by making them different or by changing the thickness of the spacer layers 14 and 18. it can.

In the present invention, the gate electrodes related to the energy band control layer may be formed on both upper and lower sides of the first well layer, or may be formed on any one side. The number of gate electrodes of the control layer is 0, 1,
According to any one of the above two, as a transistor,
It is possible to realize three types of three terminals, four terminals, and five terminals. In any case, even if the transistors have the same structure, three types of roles are performed depending on whether or not the gate electrode is provided. Is possible.

Further, for example, when configuring a neuro computer, it is possible to use more terminals, for example, 24 terminals, and the number of terminals is appropriately selected depending on what kind of operation is performed.

[0071]

In the single-electron transistor according to the present invention, a quantum well constituted by sandwiching a first well layer with a potential barrier layer including a semiconductor layer made conductive by introducing an impurity is provided. And a second well layer that generates a well with a lower potential in the first well layer compared to the potential of the first well layer in the quantum well, and near one interface of the first well layer. A source electrode in contact with the two-dimensional carrier layer generated in the second step, a drain electrode in contact with the two-dimensional carrier layer generated in the vicinity of the other interface, and a gate electrode for applying a potential to the second well layer.

According to the above configuration, in the single-electron transistor according to the present invention, the carriers move in the vertical direction (vertical direction) of the wafer, that is, three-dimensionally. The degree of integration can be much higher than that of the structure in which the carrier moves in a plane on the wafer.

[Brief description of the drawings]

FIG. 1 is a cutaway side view showing a main part of a required semiconductor layer stack used for forming a single electron transistor according to a first embodiment of the present invention;

FIG. 2 is a plan view of a principal part showing a principle single electron transistor in the present invention using the laminate shown in FIG. 1;

FIG. 3 is a fragmentary side view showing a single-electron transistor in a process key point for describing a method of manufacturing the single-electron transistor according to the first embodiment;

FIG. 4 is a fragmentary side view showing a single-electron transistor at a key point in a process for explaining a method of manufacturing the single-electron transistor according to the first embodiment;

FIG. 5 is an energy band diagram for explaining the operation of the single-electron transistor according to the first embodiment.

FIG. 6 is a main part plan view showing a single-electron transistor for describing Embodiment 2 of the present invention;

FIG. 7 is a fragmentary side view for explaining a single-electron transistor according to a second embodiment;

FIG. 8 is a fragmentary side view for explaining a single-electron transistor according to a second embodiment;

FIG. 9 is an explanatory view of a main part showing a single-electron transistor for explaining a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Substrate 11 Buffer layer 12 Energy band control layer 13 Electron supply layer 14 Spacer layer 15 Drain layer 16 Island layer 17 Source layer 18 Spacer layer 19 Electron supply layer 20 Energy band control layer 21 Source electrode 22 Drain electrode 23 Gate electrode 24 Protective insulating film 25 Second gate electrode 26 Third gate electrode

Claims (6)

[Claims] 1. A quantum well comprising a first well layer sandwiched by a potential barrier layer including a semiconductor layer made conductive by introducing impurities, and a first well layer in the quantum well. Contacting a second well layer that generates a well with a lower potential than the potential of the first well layer, and a two-dimensional carrier gas layer generated near one interface of the first well layer A single-electron transistor comprising: a source electrode; a drain electrode in contact with a two-dimensional carrier gas layer generated in the vicinity of the other interface; and a gate electrode for applying a potential to the second well layer. 2. The semiconductor layer which is included in a potential barrier layer formed on both sides of a first well layer and made conductive by introducing an impurity has an impurity concentration of one side and the other side. 2. The single electron transistor according to claim 1, wherein the single electron transistor is different. 3. A non-doped spacer layer made of the same material as the semiconductor layer is interposed between the semiconductor layer made conductive by introducing impurities and the first well layer. 3. The single-electron transistor according to claim 1, wherein: 4. The single electron transistor according to claim 3, wherein the thickness of the non-doped spacer layer adjacent to both sides of the first well layer is different on one side and the other side. 5. A non-doped energy band which is adjacent to the non-doped spacer layer of the semiconductor layer which is made conductive by introducing impurities and which is made of the same material as the semiconductor layer on the side opposite to the adjacent side. 5. The single-electron transistor according to claim 1, further comprising a control layer. 6. The single-electron transistor according to claim 5, further comprising an independent gate electrode for applying a potential to a non-doped energy band control layer included in a potential barrier layer constituting the quantum well. .