JPH10178125A - Package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a package in which high impedance line is realized on the input side substrate without increasing current-flowing loss. SOLUTION: In a package 1, a recessed housing part 1a in which the input side substrate 2 is housed, a protruding housing part 16 in which an FET(field effect transistor) chip 3 is housed, and a recessed housing part 1c in which the output side substrate is housed are placed. A mounting surface of the input side substrate 2 in the housing part 1a and a mounting surface of the output side substrate 4 in the housing part 1c are provided on a level lower than a mounting surface of the FET chip 3 of the housing part 1b, and the mounting surface of the input side substrate 2 in the housing part 1a is provided on a level lower than the mounting surface of the output side substrate 4 in the housing part 1c.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package,
In particular, the present invention relates to a package including a metal housing for housing a field effect transistor, an input side substrate, and an output side substrate.

[0002]

2. Description of the Related Art Conventionally, a field effect transistor (FET:
A Field-Effect Transistor has an input terminal and an output terminal, and a few megahertz (MHz) to a few gigahertz (GH) from the input terminal.
z) The microwave is input and the power of the microwave is reduced by several dB.
The signal is output from the output terminal after amplification.

[0003] Therefore, a package containing a field effect transistor is composed of a metal case for containing an FET chip, an input side substrate, and an output side substrate, which are components of the field effect transistor. Either the portion where the substrate and the output side substrate are mounted is the same surface (flat surface), or only the portion where the FET chip is mounted is convex.

For example, as shown in FIGS. 2A and 2B, only the mounting surface 11b of the package 11 on which the FET chip 13 is mounted is made convex, and the input side substrate 12 and the output side substrate 14 are mounted respectively. Mounting surface 11a,
11c is the same surface, that is, the mounting surfaces 11a and 11c are the same in height from the mounting surface 11b. FIG. 3 shows an example of the impedance of this FET chip.

[0005] Further, in the same configuration as described above, there is a type in which a cap is attached to the upper surface of the package. A radio wave absorber is attached to the cap on the opposing surface of the input side substrate and the output side substrate. There is also a configuration example in which a blocking wall protruding so as to block the coupling between the side substrates is provided. This configuration example is disclosed in
No. 3202.

[0006]

In the above-mentioned conventional package, the portion for mounting the FET chip, the input side substrate and the output side substrate is made the same surface, or only the portion for mounting the FET chip is formed in a convex shape. I have.

However, since the impedance of the FET chip is different between the input side and the output side, and the impedance on the input side is high, when the impedance of the FET chip is matched to 50 Ω in the package, the phase of the input side circuit is reduced. Must be turned larger than the phase of the output side circuit. That is, as shown in FIG. 3, the input side (S1
Since 1) has a higher impedance than the output side (S22) [in FIG. 3, the input (S11) is located outside the output side (S22)], it must be moved a larger distance in order to achieve 50Ω matching. .

Therefore, when the side substrate is formed of a dielectric substrate (for example, an alumina substrate), the input side substrate must be a high-impedance line with a narrow line width. Becomes larger.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide a package capable of realizing a high-impedance line on an input-side substrate without increasing a transmission loss.

[0010]

A package according to the present invention comprises a field effect transistor, an input substrate electrically connected to an input side of the field effect transistor, and an electric field connected to an output side of the field effect transistor. A package comprising a metal housing for storing an output-side substrate to be connected, the package including the output-side substrate such that connection surfaces of the field-effect transistor and the output-side substrate are at the same height. And a second storage unit that stores the input-side substrate such that a connection surface of the input-side substrate that is thicker than a thickness of the output-side substrate is at the same height as a connection surface of the field-effect transistor. It has.

Another package according to the present invention includes a first mounting portion for mounting a field effect transistor, and a second mounting portion for mounting an input side substrate electrically connected to an input side of the field effect transistor. A package comprising a metal housing provided with a third mounting portion for mounting an output-side substrate electrically connected to the output side of the field-effect transistor, wherein the second and third packages are provided. The mounting surface of each of the mounting portions is lower than the mounting surface of the first mounting portion, and
By setting the mounting surface of the mounting portion to be lower than the mounting surface of the third mounting portion, the connection surface of the field-effect transistor, the connection surface of the input-side substrate, and the connection surface of the output-side substrate It is the same height.

That is, in the package of the present invention, the line width of the input-side substrate is a thick line with a small passage loss, and the thickness of the input-side substrate is increased so that a high impedance can be obtained with this thick line. The mounting surface of the portion for storing the input-side substrate is lower than the mounting surface of the portion for storing the output-side substrate.

Therefore, the connection surface of the FET chip on which the connection wiring pattern is formed and the connection surface of the input-side substrate and the output-side substrate on which the connection wiring pattern is formed can be made the same height. It is possible to realize a high impedance line on the input-side substrate without increasing the passage loss.

[0014]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a plan view of one embodiment of the present invention, and FIG. 1B is a cross-sectional view of one embodiment of the present invention. In these figures, the package 1 has a concave storage portion 11a for storing the input-side substrate 2, a convex storage portion 11b for storing the FET chip 3, and a concave storage portion 11c for storing the output-side substrate. Has been established.

The mounting surface of the input side substrate 2 in the storage portion 11a and the mounting surface of the output side substrate 4 in the storage portion 11c are provided lower than the mounting surface of the FET chip 3 in the storage portion 11b. The mounting surface of the input side substrate 2 is provided lower than the mounting surface of the output side substrate 4 in the storage portion 11c.

The output side substrate 4 is an alumina ceramic substrate which is a generally used dielectric substrate, and has a dielectric constant =
9.8, substrate thickness = 0.254 mm, conductor thickness = 0.038
mm. When the characteristic impedance is 50Ω, the conductor width is ≒ 0.2 mm.

Under these conditions, the input side substrate 2
When matching with a characteristic impedance of 5Ω, the conductor width ≒
It is necessary to reduce the thickness to 0.058 mm, in which case the passage loss due to the line increases by about 0.5 dB.

In this case, the substrate thickness of the input side substrate 2 is 0.5
mm, a characteristic impedance of 65Ω can be obtained with a conductor width of ≒ 0.2 mm, and the passage loss becomes equal to that of the output side substrate 4. In the above-described configuration, the above-described effects become remarkable when the microwave input to the FET chip 3 becomes several GHz or more in the passage loss due to the line width.

As described above, in the package 1 housing the input side substrate 2, the FET chip 3, and the output side substrate 4,
The mounting surface of the storage unit 1a on which the input-side substrate 2 is mounted is lower than the mounting surface of the storage unit 1c on which the output-side substrate 4 is mounted. Connect the connection surface of the input side substrate 2 with thicker FET
The height can be the same as the connection surface of each of the chip 3 and the output side substrate 4. Therefore, a high impedance line can be realized on the input side substrate 2 without increasing the passage loss.

[0020]

As described above, according to the present invention, a field effect transistor, an input substrate electrically connected to the input side of the field effect transistor, and an electrical connection to the output side of the field effect transistor A first storage unit that stores the output-side substrate such that the connection surface of each of the field-effect transistor and the output-side substrate is at the same height; A second housing for housing the input-side substrate such that the connection surface of the input-side substrate thicker than the thickness of the output-side substrate is at the same height as the connection surface of the field-effect transistor; Therefore, there is an effect that a high-impedance line can be realized on the input side substrate without performing.

[Brief description of the drawings]

FIG. 1A is a plan view of one embodiment of the present invention, and FIG. 1B is a cross-sectional view of one embodiment of the present invention.

2A is a plan view of a conventional example, and FIG. 2B is a cross-sectional view of the conventional example.

FIG. 3 is a diagram illustrating an example of impedance of a single FET chip.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Package 1a, 1c Concave storage part 1b Convex storage part 2 Input side board 3 FET chip 4 Output side board

Claims (3)

[Claims] 1. A field effect transistor, an input side substrate electrically connected to an input side of the field effect transistor, and an output side substrate electrically connected to an output side of the field effect transistor. A package including a metal housing, a first storage unit that stores the output-side substrate such that connection surfaces of the field-effect transistor and the output-side substrate are at the same height, and the output-side substrate A second housing portion for housing the input-side substrate such that a connection surface of the input-side substrate thicker than a thickness of the input-side substrate is at the same height as a connection surface of the field-effect transistor. 2. The package according to claim 1, wherein a storage surface of said second storage portion is lower than a storage surface of said first storage portion. 3. A first mounting portion for mounting a field-effect transistor, a second mounting portion for mounting an input-side substrate electrically connected to an input side of the field-effect transistor, and A package comprising a metal housing provided with a third mounting portion for mounting an output-side substrate electrically connected to an output side, wherein each of the second and third mounting portions is mounted. The connection of the field-effect transistor is configured such that a surface is lower than a mounting surface of the first mounting portion and a mounting surface of the second mounting portion is lower than a mounting surface of the third mounting portion. A package, wherein a surface, a connection surface of the input-side substrate, and a connection surface of the output-side substrate have the same height.