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JPH10172960A - Ashing method - Google Patents

Ashing method

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Publication number
JPH10172960A
JPH10172960A JP33201496A JP33201496A JPH10172960A JP H10172960 A JPH10172960 A JP H10172960A JP 33201496 A JP33201496 A JP 33201496A JP 33201496 A JP33201496 A JP 33201496A JP H10172960 A JPH10172960 A JP H10172960A
Authority
JP
Japan
Prior art keywords
substrate
ashing
electrode
gas containing
distance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33201496A
Other languages
Japanese (ja)
Inventor
Minoru Yamamoto
稔 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP33201496A priority Critical patent/JPH10172960A/en
Publication of JPH10172960A publication Critical patent/JPH10172960A/en
Pending legal-status Critical Current

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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PROBLEM TO BE SOLVED: To remove organic residues, by setting a substrate to be processed on the substrate stage of a parallel plane-type plasma ashing device where a distance between electrodes is a specified value, and executing plasma ashing with gas containing oxygen. SOLUTION: A confronted electrode 14 operates as a gas shower head and it can uniformly supply gas containing oxygen to the processed substrate 11. Gas containing oxygen can be supplied from a gas nozzle which is separately provided. The confronting electrode 14 of a substrate stage 12 is stored in a chamber 16 and it is controlled to desired pressure by a vacuum pump and a pressure control means. The inter-electrode distance Gp between the substrate stage 12 and the confronting electrode 14 can be fixed or can finely be adjusted to the range of Gp=10±3mm. The adjusting means of the inter-electrode distance Gp can be a mechanical method by hydraulic and pneumatic fluid cylinder or that by a gear.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置の製造
工程等に用いられるアッシング方法に関し、さらに詳し
くは、レジストマスク等の有機物層を現像処理等により
パターニングした後の有機物残渣、いわゆるスカムを高
精度に除去するアッシング方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ashing method used in a manufacturing process of a semiconductor device and the like, and more particularly, to a method for removing an organic residue, that is, a so-called scum after an organic layer such as a resist mask is patterned by a developing process or the like. The present invention relates to an ashing method for removing with high accuracy.

【0002】[0002]

【従来の技術】LSI等の半導体装置の製造工程におい
ては、電極配線材料や層間絶縁膜等のエッチングに際し
て、これらの被エッチング層上にレジストパターンを形
成し、このレジストパターンをエッチングマスクとし
て、下地の被エッチング層をエッチングすることがおこ
なわれる。レジストパターンの形成は、通常被エッチン
グ層上にレジスト膜を塗布し、このレジスト膜に選択的
にUV光等を照射して露光し、現像液によりパターニン
グする。露光部分のレジスト膜が除去されるのがポジ型
レジスト、非露光部分のレジスト膜が除去されるのがネ
ガ型レジストである。
2. Description of the Related Art In a process of manufacturing a semiconductor device such as an LSI, a resist pattern is formed on a layer to be etched when an electrode wiring material, an interlayer insulating film, and the like are etched, and the resist pattern is used as an etching mask. Is etched. The formation of the resist pattern is usually performed by applying a resist film on the layer to be etched, selectively irradiating the resist film with UV light or the like, exposing the resist film, and patterning with a developer. A positive resist removes the exposed portion of the resist film, and a negative resist removes the unexposed portion of the resist film.

【0003】レジスト膜の現像にあたっては、選択的に
露光された形状にしたがって、忠実にパターニングされ
るのが望ましいが、現実にはレジスト膜が除去された抜
き部には、スカム(scum)と称されるレジスト残渣
が残る場合が多い。スカムの原因は、露光強度のアンバ
ラアンスや、下地の被エッチング層とレジスト膜との相
互作用等が指摘されている。このスカムにもとづく問題
点を図5(a)〜(c)を参照して説明する。
In developing a resist film, it is desirable that the resist film is faithfully patterned in accordance with the selectively exposed shape. In many cases, resist residues remain. It has been pointed out that the cause of the scum is an imbalance in the exposure intensity, an interaction between the underlying etched layer and the resist film, and the like. The problem based on this scum will be described with reference to FIGS.

【0004】被エッチング層1上に例えばポジ型のレジ
スト膜2を塗布形成し、ステッパ等により露光光3を選
択的に照射する(図5(a))。現像液により現像し、
露光光3の照射部分を溶出して開口幅aのレジストパタ
ーン4を形成する。レジストパターン4間には現像残渣
であるスカム5が残存する(図5(b))。このレジス
トパターン4をエッチングマスクとして被エッチング層
1をエッチングすると、被エッチング層の特に底部のス
ペース幅bは所望とするスペース幅aより狭くなり、ス
カム5に起因する負のパターン変換差b−aが発生する
(図5(c))。
[0004] For example, a positive resist film 2 is applied and formed on the layer 1 to be etched, and exposure light 3 is selectively irradiated by a stepper or the like (FIG. 5A). Develop with a developer,
The resist pattern 4 having the opening width a is formed by eluting the irradiated portion of the exposure light 3. A scum 5 which is a development residue remains between the resist patterns 4 (FIG. 5B). When the layer 1 to be etched is etched using the resist pattern 4 as an etching mask, the space width b at the bottom of the layer to be etched becomes narrower than the desired space width a, and the negative pattern conversion difference ba resulting from the scum 5 is obtained. Occurs (FIG. 5C).

【0005】かかるパターン変換差を避けるため、デス
カム(descum)と呼ばれるステップが挿入される
場合がある。このデスカムにおける問題点を図6(a)
〜(c)を参照して説明する。図6(a)に示すレジス
ト膜現像後のスカム5を除去する場合、普通ダウンフロ
ー方式のマイクロ波プラズマアッシング装置により施さ
れる。しかし、通常のアッシング条件ではアッシングレ
ートが1000nm〜5000nm/分と高く、デスカ
ム時間の設定が困難で、スカム5と同時にレジストパタ
ーン4も膜減り、あるいは後退して、所望とした開口幅
aは開口幅cと広くなる(図6(b)。このレジストパ
ターン4をエッチングマスクとして被エッチング層1を
エッチングすると、被エッチング層1のスペース幅cは
所望とするスペース幅aより広くなり、パターン変換差
c−aが発生する(図6(c))。
[0005] In order to avoid such a pattern conversion difference, a step called descum may be inserted. Fig. 6 (a)
This will be described with reference to FIGS. When the scum 5 after the resist film development shown in FIG. 6A is removed, the scum 5 is usually applied by a down-flow microwave plasma ashing apparatus. However, under normal ashing conditions, the ashing rate is as high as 1000 nm to 5000 nm / min, and it is difficult to set the descum time. At the same time as the scum 5, the resist pattern 4 is reduced in film thickness or receded, and the desired opening width a is reduced. (FIG. 6B) When the layer 1 to be etched is etched using the resist pattern 4 as an etching mask, the space width c of the layer 1 to be etched becomes larger than the desired space width a, and the pattern conversion difference is increased. ca occurs (FIG. 6C).

【0006】このため、マイクロ波プラズマアッシング
装置のアッシングレートを抑えたアッシング条件でデス
カムをおこなうが、この場合にもアッシングレートの均
一性は±4.5〜6.0%程度と良くなく、改善が望ま
れる。マイクロ波プラズマアッシング装置による従来の
デスカム条件の一例を下記に示す。 O2 40〜60 sccm 圧力 100〜200 Pa マイクロ波パワー400〜1000 W(2.45GH
z) 被処理基板温度 110〜130 ℃ アッシングレート 60〜90 nm/分 アッシングレートの被処理基板面内均一性 ±4〜6 %
For this reason, descum is performed under ashing conditions in which the ashing rate of the microwave plasma ashing apparatus is suppressed, but in this case, the uniformity of the ashing rate is not as good as about ± 4.5 to 6.0%, and is improved. Is desired. An example of a conventional descum condition using a microwave plasma ashing apparatus is shown below. O 2 40-60 sccm Pressure 100-200 Pa Microwave power 400-1000 W (2.45 GH
z) Temperature of substrate to be processed 110 to 130 ° C. Ashing rate 60 to 90 nm / min Uniformity of ashing rate in the surface of the substrate to be processed ± 4 to 6%

【0007】[0007]

【発明が解決しようとする課題】本発明は上述した従来
技術の諸問題点に鑑みて提案するものである。すなわち
本発明の課題は、レジスト膜現像後のスカム等の有機物
残渣を、パターン変換差等を発生することなく、均一性
よく除去するアッシング方法を提供することである。
SUMMARY OF THE INVENTION The present invention has been proposed in view of the above-mentioned problems of the prior art. That is, an object of the present invention is to provide an ashing method for uniformly removing organic residues such as scum after developing a resist film without generating a pattern conversion difference or the like.

【0008】[0008]

【課題を解決するための手段】本発明のアッシング方法
は上述の課題を解決するために提案するものであり、表
面に有機物残渣を有する被処理基板のアッシング方法に
おいて、前記被処理基板を、電極間距離が7mm以上1
3mm以下の平行平板型プラズマアッシング装置の基板
ステージ上にセッティングし、酸素を含むガスによりプ
ラズマアッシングすることを特徴とする。
An ashing method according to the present invention is proposed to solve the above-mentioned problems. In an ashing method for a substrate having an organic residue on its surface, the method comprises the steps of: Distance between 7mm and 1
It is set on a substrate stage of a parallel plate type plasma ashing apparatus of 3 mm or less, and plasma ashing is performed with a gas containing oxygen.

【0009】このとき、酸素を含むガスの圧力を150
Pa以上250Pa以下に制御することが望ましい。有
機物残渣としては、レジストパターンを現像処理後に、
このレジストパターン間に残存するスカム等を除去する
際に好適に適用することができる。本発明のアッシング
方法においては、有機物残渣を除去するとともに、下地
の被処理基板表面の親水性処理を施すことができる。
At this time, the pressure of the gas containing oxygen is increased to 150
It is desirable to control the pressure to not less than Pa and not more than 250 Pa. As an organic residue, after developing the resist pattern,
It can be suitably applied when removing scum and the like remaining between the resist patterns. In the ashing method of the present invention, the organic residue can be removed, and the surface of the underlying substrate can be subjected to a hydrophilic treatment.

【0010】[0010]

【発明の実施の形態】以下、本発明の具体的実施形態例
につき添付図面を参照して説明する。図1は本発明のア
ッシング方法に適用される平行平板型プラズマアッシン
グ装置の一構成例を示す概略断面図である。被処理基板
11は基板ステージ12上に載置され、ヒータ等の加熱
手段13により所望の温度に加熱制御される。この基板
ステージ12は接地電位とされている。基板ステージ1
2に対向して、ブロッキングコンデンサを介してRF電
源15に接続された対向電極14が配設されており、い
わゆるアノードカップル方式の平行平板型エッチング装
置の構成となっている。対向電極14はガスシャワーヘ
ッドを兼ねており、被処理基板11に酸素を含むガスを
均一に供給することができる。酸素を含むガスは別途設
けたガスノズルから供給してもよい。基板ステージ1
2、対向電極14等はチャンバ16内に収容され、不図
示の真空ポンプおよび圧力制御手段により所望の圧力に
制御される。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a schematic sectional view showing a configuration example of a parallel plate type plasma ashing apparatus applied to the ashing method of the present invention. The substrate 11 to be processed is placed on a substrate stage 12, and is heated to a desired temperature by a heating means 13 such as a heater. This substrate stage 12 is set to the ground potential. Substrate stage 1
A counter electrode 14 connected to an RF power supply 15 via a blocking capacitor is disposed opposite to the counter electrode 2 to form a so-called parallel plate type etching apparatus of an anode couple type. The counter electrode 14 also serves as a gas shower head, and can uniformly supply a gas containing oxygen to the substrate 11 to be processed. The gas containing oxygen may be supplied from a separately provided gas nozzle. Substrate stage 1
2. The counter electrode 14 and the like are housed in the chamber 16 and are controlled to a desired pressure by a vacuum pump and pressure control means (not shown).

【0011】この平行平板型プラズマアッシング装置の
特徴は、基板ステージ12と対向電極14との電極間距
離Gpであり、Gp=10±3mmの範囲に固定あるい
は微調整可能になっている。電極間距離Gpの調整手段
は図示を省略するが、油圧、空圧等の流体シリンダや、
ギア等による機械的方法等のいずれであってもよい。な
お図1では被処理基板11の搬入出手段やガス圧力制御
手段等の装置細部の図示は省略する。
A feature of this parallel plate type plasma ashing apparatus is a distance Gp between the substrate stage 12 and the counter electrode 14, which can be fixed or finely adjusted within a range of Gp = 10 ± 3 mm. The means for adjusting the inter-electrode distance Gp is not shown, but may be a hydraulic cylinder such as hydraulic or pneumatic,
Any of a mechanical method using a gear or the like may be used. In FIG. 1, illustration of the details of the apparatus such as the loading / unloading means for the substrate 11 to be processed and the gas pressure control means is omitted.

【0012】つぎに図1に示した平行平板型プラズマア
ッシング装置による、スカムのアッシング方法を図2
(a)〜(d)を参照して説明する。
Next, a scum ashing method using the parallel plate type plasma ashing apparatus shown in FIG. 1 is shown in FIG.
This will be described with reference to (a) to (d).

【0013】まず図2(a)に示すように、被エッチン
グ層1をその表面に有する被処理基板、例えば口径6イ
ンチのウェハ上にポジ型のレジスト膜2を塗布形成し、
露光光3として例えばi線(365nm)により選択的
に露光する。被エッチング層1の材料は特に限定されな
いが、例えばSiO2 や多結晶シリコン等が挙げられ
る。
First, as shown in FIG. 2A, a positive resist film 2 is applied on a substrate to be etched having a layer 1 to be etched, for example, a wafer having a diameter of 6 inches.
The exposure light 3 is selectively exposed by, for example, i-line (365 nm). The material of the layer 1 to be etched is not particularly limited, and examples thereof include SiO 2 and polycrystalline silicon.

【0014】PEB(Post Exposure B
aking)後、現像液により現像して開口幅aのレジ
ストパターン4を形成する。レジストパターン4底部の
被エッチング層1表面には、スカム5が残存している
(図2(b))。このステップ迄は常法により施してよ
い。
PEB (Post Exposure B)
After the aking, the resist pattern 4 having an opening width a is formed by developing with a developing solution. The scum 5 remains on the surface of the layer to be etched 1 at the bottom of the resist pattern 4 (FIG. 2B). Up to this step, a conventional method may be used.

【0015】この後、図2(b)に示す被処理基板を、
図1に示す平行平板型プラズマアッシング装置の基板ス
テージ12上にセッティングし、一例として下記アッシ
ング条件によりスカム5を除去した。 O2 1000〜2000 sccm 圧力 150〜200 Pa RFパワー 40〜60 W(13.56M
Hz) 被処理基板温度 110〜130 ℃ 電極間距離Gp 10±3 mm アッシングレート 50〜70 nm/分
Thereafter, the substrate to be processed shown in FIG.
The scum 5 was set on the substrate stage 12 of the parallel plate type plasma ashing apparatus shown in FIG. O 2 1000-2000 sccm Pressure 150-200 Pa RF power 40-60 W (13.56M
Hz) Target substrate temperature 110-130 ° C. Distance between electrodes Gp 10 ± 3 mm Ashing rate 50-70 nm / min

【0016】この結果、図2(c)に示すようにレジス
トパターン4の膜減りを発生することなく、スカム5が
効率よく除去された。この後、図2(c)に示す被処理
基板を平行平板型プラズマアッシング装置から搬出し、
例えばECRプラズマエッチング装置により被エッチン
グ層1、例えばSiO2 層をパターニングする。被エッ
チング層1には、レジストパターン4の開口幅aが忠実
に転写された開口幅aのパターンが形成された(図2
(d))。被エッチング層1に形成された開口パターン
は、例えば接続孔として利用することができる。
As a result, as shown in FIG. 2 (c), the scum 5 was efficiently removed without causing a decrease in the film thickness of the resist pattern 4. Thereafter, the substrate to be processed shown in FIG. 2C is unloaded from the parallel plate type plasma ashing apparatus,
For example, an etching target layer 1, for example, an SiO 2 layer is patterned by an ECR plasma etching apparatus. In the layer to be etched 1, a pattern having an opening width a in which the opening width a of the resist pattern 4 was faithfully transferred was formed.
(D)). The opening pattern formed in the layer 1 to be etched can be used, for example, as a connection hole.

【0017】また、図2(c)に示す被処理基板のSi
2 等の被エッチング層1表面は、このプラズマアッシ
ングにより親水性表面に変換される。したがって、次工
程でウェットエッチング処理する場合には、エッチング
溶液との濡れ性に優れ、気泡等の発生を抑制できる。し
たがって、ウェットエッチングの場合にもレジストパタ
ーン4の開口幅に忠実なパターニングが可能となる。
Further, the Si of the substrate to be processed shown in FIG.
The surface of the layer to be etched 1 such as O 2 is converted into a hydrophilic surface by this plasma ashing. Therefore, when wet etching is performed in the next step, the wettability with an etching solution is excellent, and generation of bubbles and the like can be suppressed. Therefore, even in the case of wet etching, patterning faithful to the opening width of the resist pattern 4 can be performed.

【0018】前述のプラズマアッシング条件において、
例えば圧力を175Paに固定した場合の電極間距離G
pとアッシングレートの均一性との関係を図3に示す。
同図から明らかなように、電極間距離Gpが10±3m
mの場合にはアッシングレートの被処理基板面内均一性
は±2%以内と良好な値を示すことが判る。一方、電極
間距離Gpが10±3mmを超えると、アッシングレー
トの均一性は±2%以上となり、スカム5の除去が不充
分であったり、レジストパターン5に膜減りが発生す
る。この結果、エッチング後の被エッチング層1の形状
にパターン変換差が発生する事態が生じる。
Under the aforementioned plasma ashing conditions,
For example, the distance G between the electrodes when the pressure is fixed at 175 Pa
FIG. 3 shows the relationship between p and the uniformity of the ashing rate.
As is clear from the figure, the distance Gp between the electrodes is 10 ± 3 m.
It can be seen that in the case of m, the uniformity of the ashing rate in the surface of the substrate to be processed is a good value of ± 2% or less. On the other hand, when the distance Gp between the electrodes exceeds 10 ± 3 mm, the ashing rate uniformity becomes ± 2% or more, and the removal of the scum 5 is insufficient or the resist pattern 5 is reduced in film thickness. As a result, a situation occurs where a pattern conversion difference occurs in the shape of the layer 1 after etching.

【0019】また前述のプラズマアッシング条件におい
て、一例として電極間距離を10mmに固定した場合の
ガスの処理圧力とアッシングレートの均一性との関係を
図4に示す。同図から明らかなように、処理圧力が15
0〜250Paの場合にはアッシングレートの被処理基
板面内均一性は±2%以内と良好な値を示すことが判
る。一方、圧力が150〜250Paの範囲を超える
と、アッシングレートの均一性は±2%以上となり、ス
カム5の除去が不充分であったり、レジストパターン5
に膜減りが発生する。この結果、やはりエッチング後の
被エッチング層1の形状にパターン変換差が発生する事
態となる。この傾向は、電極間距離Gpが10±3mm
の範囲内においても同様の結果であった。
FIG. 4 shows the relationship between the gas processing pressure and the uniformity of the ashing rate when the distance between the electrodes is fixed to 10 mm, for example, under the above-mentioned plasma ashing conditions. As is apparent from FIG.
It can be seen that in the case of 0 to 250 Pa, the uniformity of the ashing rate in the surface of the substrate to be processed is a good value of ± 2% or less. On the other hand, when the pressure exceeds the range of 150 to 250 Pa, the uniformity of the ashing rate becomes ± 2% or more, the removal of the scum 5 is insufficient, or the resist pattern 5
Film loss occurs. As a result, a pattern conversion difference occurs in the shape of the layer 1 to be etched after the etching. This tendency is observed when the distance Gp between the electrodes is 10 ± 3 mm.
The same result was obtained within the range.

【0020】以上、本発明のアッシング方法につき詳細
な説明を加えたが、本発明はこの実施形態例に限定され
ることなく、各種の実施態様が可能である。例えば、レ
ジスト膜としてi線対応のポジ型レジストを例示した
が、g線対応、エキシマレーザ対応、あるいは電子線露
光対応の各種ポジ型およびネガ型レジストの現像後のス
カム除去に適用することが可能である。また感光性レジ
スト以外にも、ポリイミド膜や、多層レジストにおける
下層平坦化膜のエッチング残渣の除去に好適に用いるこ
ともできる。有機物残渣として、スカムやエッチング残
渣以外にも、表面に各種有機物汚染を有する被処理基板
のクリーニング等に用いてもよい。
As described above, the ashing method of the present invention has been described in detail. However, the present invention is not limited to this embodiment, and various embodiments are possible. For example, although the positive resist for i-line is exemplified as the resist film, it can be applied to scum removal after development of various positive and negative resists corresponding to g-line, excimer laser, or electron beam exposure. It is. In addition to the photosensitive resist, it can be suitably used for removing an etching residue of a polyimide film or a lower-layer planarizing film in a multilayer resist. As the organic residue, in addition to the scum and the etching residue, it may be used for cleaning a substrate to be processed having various kinds of organic contamination on the surface.

【0021】またアッシングガスとして酸素単独の他
に、O3 、NH3 、COあるいは希ガス等の各種添加ガ
スを混合して用いてもよい。他のエッチング条件、例え
ばガス流量、RFパワー等は、使用する被処理基板の口
径やエッチング装置のチャンバ内容積等に応じて最適値
に決定されるべき設計事項である。
As the ashing gas, various additive gases such as O 3 , NH 3 , CO or rare gas may be mixed and used in addition to oxygen alone. Other etching conditions, such as gas flow rate and RF power, are design items that should be determined to be optimal values according to the diameter of the substrate to be used, the volume in the chamber of the etching apparatus, and the like.

【0022】[0022]

【発明の効果】以上の説明から明らかなように、本発明
のアッシング方法によれば、レジスト膜現像後のスカム
等の有機物残渣を、パターン変換差を発生することな
く、均一性よく除去することが可能である。
As is apparent from the above description, according to the ashing method of the present invention, organic residues such as scum after development of a resist film can be removed with good uniformity without generating a pattern conversion difference. Is possible.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のアッシング方法で採用する平行平板型
プラズマアッシング装置の一構成例を示す概略断面図で
ある。
FIG. 1 is a schematic sectional view showing a configuration example of a parallel plate type plasma ashing apparatus employed in an ashing method of the present invention.

【図2】本発明のアッシング方法を、その工程順に示す
概略断面図である。
FIG. 2 is a schematic sectional view showing the ashing method of the present invention in the order of steps.

【図3】電極間距離とアッシングレートの均一性を示す
グラフである。
FIG. 3 is a graph showing the uniformity of an inter-electrode distance and an ashing rate.

【図4】ガスの処理圧力とアッシングレートの均一性を
示すグラフである。
FIG. 4 is a graph showing gas processing pressure and ashing rate uniformity.

【図5】従来のアッシング方法の問題点を、その工程順
に示す概略断面図である。
FIG. 5 is a schematic sectional view showing a problem of a conventional ashing method in the order of steps.

【図6】従来のアッシング方法の別の問題点を、その工
程順に示す概略断面図である。
FIG. 6 is a schematic cross-sectional view showing another problem of the conventional ashing method in the order of steps.

【符号の説明】[Explanation of symbols]

1…被エッチング層、2…レジスト膜、3…露光光、4
…レジストパターン、5…スカム、11…被処理基板、
12…基板ステージ、13…加熱手段、14…対向電
極、15…RF電源、16…チャンバ
DESCRIPTION OF SYMBOLS 1 ... Layer to be etched, 2 ... Resist film, 3 ... Exposure light, 4
... resist pattern, 5 ... scum, 11 ... substrate to be processed,
12: substrate stage, 13: heating means, 14: counter electrode, 15: RF power supply, 16: chamber

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 表面に有機物残渣を有する被処理基板の
アッシング方法において、 前記被処理基板を、電極間距離が7mm以上13mm以
下の平行平板型プラズマアッシング装置の基板ステージ
上にセッティングし、 酸素を含むガスによりプラズマアッシングすることを特
徴とするアッシング方法。
1. An ashing method for a substrate having an organic residue on its surface, comprising: setting the substrate to be processed on a substrate stage of a parallel plate type plasma ashing apparatus having a distance between electrodes of 7 mm or more and 13 mm or less; An ashing method characterized by performing plasma ashing with a gas containing gas.
【請求項2】 前記酸素を含むガスの圧力を150Pa
以上250Pa以下に制御することを特徴とする請求項
1記載のアッシング方法。
2. The pressure of the gas containing oxygen is 150 Pa
2. The ashing method according to claim 1, wherein the pressure is controlled to be not less than 250 Pa.
【請求項3】 前記有機物残渣は、レジストパターンを
現像処理後に、前記レジストパターン間に残存するスカ
ムであることを特徴とする請求項1記載のアッシング方
法。
3. The ashing method according to claim 1, wherein the organic residue is scum remaining between the resist patterns after developing the resist pattern.
【請求項4】 プラズマアッシングにより前記有機物残
渣を除去するとともに、前記被処理基板表面の親水性処
理を施すことを特徴とする請求項1記載のアッシング方
法。
4. The ashing method according to claim 1, wherein the organic residue is removed by plasma ashing, and the surface of the substrate is subjected to a hydrophilic treatment.
JP33201496A 1996-12-12 1996-12-12 Ashing method Pending JPH10172960A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33201496A JPH10172960A (en) 1996-12-12 1996-12-12 Ashing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33201496A JPH10172960A (en) 1996-12-12 1996-12-12 Ashing method

Publications (1)

Publication Number Publication Date
JPH10172960A true JPH10172960A (en) 1998-06-26

Family

ID=18250184

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33201496A Pending JPH10172960A (en) 1996-12-12 1996-12-12 Ashing method

Country Status (1)

Country Link
JP (1) JPH10172960A (en)

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US6607986B2 (en) 1999-12-28 2003-08-19 Kabushiki Kaisha Toshiba Dry etching method and semiconductor device manufacturing method
US6987066B2 (en) 1999-12-28 2006-01-17 Kabushiki Kaisha Toshiba Dry etching method and semiconductor device manufacturing method
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KR20030096669A (en) * 2002-06-17 2003-12-31 삼성전자주식회사 method for manufacturing gate in semiconductor memory device
US9188086B2 (en) 2008-01-07 2015-11-17 Mcalister Technologies, Llc Coupled thermochemical reactors and engines, and associated systems and methods
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