JPH10171550A - Clock circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock circuit capable of shortening clock propagation delay time up to a final flip flop(FF) stage exerting influence upon the characteristics of the whole IC. SOLUTION: An external clock inputted from a clock input terminal 1 is supplied to respective FFs 5, 6 through a clock tree circuit 2 and supplied also to a final FF 7 through a by-pass clock circuit 3. Respective buffers B10 to B16 have equal propagation delay time. A clock tree is constituted of three buffer stages and two buffer stages to reduce the clock skew of the FFs 5, 6. Since the by-pass clock circuit 3 is constituted of one buffer stage B16, the clock propagation delay time of the circuit 3 is higher than that of the clock tree circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock circuit, and more particularly to a clock circuit for supplying a clock with reduced clock skew in a circuit integrated on a semiconductor substrate.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing an example of a conventional clock circuit. This conventional clock circuit includes a clock tree circuit 20 and an integrated circuit (IC) 25.
D mounted on the same IC 25
A clock is supplied to each clock terminal of the flip-flops 5, 6, and 7 of the type. The flip-flops 5, 6 and 7 are cascaded between the data input terminal 4 and the data output terminal 8.

The clock tree circuit 20 converts a clock input to a clock input terminal 1 into a flip-flop 5 via buffers B1, B2, B3 and B4 connected in cascade.
, Cascaded buffers B1, B
The clock is input to the flip-flop 6 via 5 and B6, and further the clock is input to the flip-flop 7 via buffers B1, B7, B8 and B9 connected in cascade.

Here, an external input clock is supplied to a buffer B1.
When a clock is supplied to each of the flip-flops 5, 6, and 7 only through the above, a difference occurs in the propagation delay time to each of the flip-flops 5, 6, and 7 due to the positional relationship between the buffer B1 and the flip-flops 5, 6, and 7. This difference results in clock skew. Therefore, conventionally, the propagation delay time between the buffer B1 and each of the flip-flops 5, 6, and 7 is compared, and the buffers B2 to B9 are added so that the respective propagation delay times become equal. 20.

As a result, the external input clock indicated by Clock in FIG. 5 is supplied to buffers B1, B2,
B3 and B4 are input to the flip-flop 5 with the propagation delay time τ in cascade, and the buffers B1, B5, and B6 are input to the flip-flop 6 with the propagation delay time τ in the cascade, and the buffers B1, B7, B8, and B9 is cascade-connected to the flip-flop 7 with the propagation delay time τ. That is, the waveforms of the output clocks of the buffers B4, B6, and B9, which are input to the respective clock terminals of the flip-flops 5, 6, and 7, change substantially at the same time, and clock skew is reduced.

[0006]

However, in the conventional clock circuit described above, the propagation delay time from the clock input terminal 1 is made equal by the clock tree circuit 20.
The addition of the buffers B2 to B9 inevitably increases the clock propagation delay time. This is because equalizing the propagation delay time to each of the flip-flops 5, 6, and 7 is nothing more than adjusting the propagation delay time of another flip-flop to the flip-flop having the slowest propagation delay time. .

The characteristics of the clock tree circuit 20 are as follows.
This affects the characteristics of the entire IC 25. This is because the clock propagation delay time of the last-stage flip-flop 7, which determines the delay time from the clock input to the data output, which is one of the characteristics of the IC 25, increases. An increase in the delay time from clock input to data output, which is one of the important characteristics of the IC, significantly impairs the usefulness of the IC.

[0008] The present invention has been made in view of the above points,
It is an object of the present invention to provide a clock circuit capable of shortening a clock propagation delay time to a final-stage flip-flop that affects the characteristics of the entire IC.

[0009]

According to the present invention, a clock obtained by shaping a waveform of an external input clock is distributed to a plurality of circuits in an integrated circuit with substantially equal propagation delay times. A clock tree circuit to supply;
A bypass clock circuit for supplying a clock obtained by shaping the waveform of the external input clock to a final-stage circuit connected to the data output terminal of the integrated circuit with a propagation delay time smaller than the propagation delay time of the clock tree circuit; and It has the structure which has.

According to the present invention, the circuit at the final stage which determines the delay time from clock input to data output of the entire integrated circuit is independent of the clock tree circuit and has a shorter propagation delay time than the clock tree circuit. Since the clock is supplied by the bypass clock circuit, the final stage circuit generates a clock skew with respect to a plurality of other circuits to which the clock from the clock tree circuit is input.
Since the propagation delay time of the bypass clock circuit is smaller than that of the clock tree circuit, there is no shortage of hold time in the circuit at the last stage, and the circuit operates stably.

Here, the plurality of circuits to which the clock is input by the clock tree circuit are a plurality of first data latch circuits connected in cascade with each other, and the last-stage circuit to which the clock is input by the bypass clock circuit is And a second data latch circuit that latches data output from the plurality of first data latch circuits at the timing of the output clock of the bypass clock circuit.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration diagram of an embodiment of a clock circuit according to the present invention. In FIG. 1, the clock circuit according to the present embodiment includes a clock tree circuit 2 and a bypass clock circuit 3. Flip-flops 5, 6, and 7 are cascaded between the data input terminal 4 and the data output terminal 8. The external clock input from the clock input terminal 1 is supplied to the respective clock terminals of flip-flops 5 and 6 which are the first data latch circuits via the clock tree circuit 2, while being supplied to the second clock terminal via the bypass clock circuit 3. Is supplied to the clock terminal of the last-stage flip-flop 7, which is a data latch circuit of the second embodiment. The propagation delay time of the bypass clock circuit 3 is set shorter than the propagation time of the clock tree circuit 2.

FIG. 2 shows a circuit diagram of an embodiment of the clock circuit according to the present invention. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals. In FIG. 2, D-type flip-flops 5, 6, and 7 are mounted on an IC 10 in a cascade connection between a data input terminal 4 and a data output terminal 8, and a clock tree circuit 2 and a bypass clock circuit are provided. 3 are mounted respectively.

The clock tree circuit 2 includes buffers B10 to B10.
B15, the clock input to the clock input terminal 1 is cascaded to buffers B10, B11, B1
2 and B13, a clock is input to the flip-flop 5 and buffers B10 and B14 connected in cascade.
And a clock is input to the flip-flop 6 via the B15. The bypass clock circuit 3 includes a single buffer B16, and inputs an external input clock from the data input terminal 1 to the flip-flop 7.

It is assumed that the buffers B10 to B16 have the same propagation delay time. Note that the actual propagation delay time of each of the buffers B10 to B16 is
The values are different depending on the arrangement and wiring within. In order to reduce the clock skew on the flip-flops 5 and 6, the embodiment of FIG. 2 has a three-stage buffer tree and a two-stage clock tree, respectively. On the other hand, the bypass clock circuit 3 has a one-stage buffer B
16, the clock propagation delay time of the bypass clock circuit 3 is faster than the propagation delay time of the clock tree circuit 2.

Next, the operation of this embodiment will be described with reference to FIG.
And FIG.

The data input to the data input terminal 4 in FIG. 2 is input to the data terminal of the flip-flop 5, where it is latched at the timing of the clock input from the clock tree circuit 2 to the clock terminal, and then latched at the next time. The data is input to the data terminal of the flip-flop 6 of the stage, where it is latched at the timing of the clock input from the clock tree circuit 2 to the clock terminal. Further, the output data of the flip-flop 6 is input to the data terminal of the last-stage flip-flop 7, where it is latched at the timing of the clock input from the bypass clock circuit 3 to the clock terminal and output to the output terminal 8.

On the other hand, the external input clock indicated by Clock in FIG. 3 input to the clock input terminal 1 in FIG. 2 is supplied to the buffers B10, B11, B1 in the clock tree circuit 2.
2 and B13, the waveforms are respectively delayed by an inherent time as shown in FIG. 3 and input to the clock terminal of the flip-flop 5 with a propagation delay time larger than the propagation delay time τ as a whole. , B
14 and B15, respectively, and at this time, the flip-flop 5 is delayed by an inherent time as shown in FIG. 3 and has a propagation delay time larger than the propagation delay time τ as a whole.
Clock terminal. That is, as shown in FIG. 3, the output clock waveforms of the buffers B13 and B15, which are the inputs to the clock terminals of the flip-flops 5 and 6, change substantially at the same time, and the clock skew is reduced.

The above-mentioned external input clock is also input to a buffer B16 in the bypass clock circuit 3, where it is shaped and subjected to a delay inherent in the buffer B16, and a propagation delay time .tau. Input to clock terminal. As shown in FIG. 3, the output clock waveform of the buffer B16 changes earlier than the output clock waveforms of the buffers B13 and B15, indicating that the clock propagation delay time is reduced.

Here, buffers B13, B15 and B1
Comparing each output clock waveform of No. 6 clearly shows that the output clock of the buffer B16 has clock skew. However, since the time at which the output clock waveform of the buffer B16 changes is earlier than the output clock waveform of the buffer B15, the flip-flop 7 can stably capture the output data of the flip-flop 6. Therefore, the clock skew does not cause shortage of the hold time in the flip-flop 7 at the last stage, the circuit operates stably, and the delay time from the clock input to the data output of the IC 10 can be reduced.

The present invention is not limited to the above embodiment. For example, the bypass clock circuit 3 may have a configuration in which the clock propagation time is shorter than the clock propagation delay time of the clock tree circuit 2. Therefore, as long as this condition is satisfied, it is possible to use a buffer composed of two or more cascade-connected buffers, or to use only a signal line without providing a buffer.

[0022]

As described above, according to the present invention,
Clock is supplied to the final stage circuit that determines the delay time from clock input to data output of the entire integrated circuit from the bypass clock circuit that is independent of the clock tree circuit and has a shorter propagation delay time than the clock tree circuit Therefore, in an integrated circuit using a conventional clock circuit in which the output clock of the clock tree circuit is also supplied to the final stage circuit, the delay time from the clock input to the data output of the entire integrated circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of one embodiment of the present invention.

FIG. 3 is a time chart for explaining the operation of FIG. 2;

FIG. 4 is a configuration diagram of a conventional example.

FIG. 5 is a time chart for explaining the operation of FIG. 4;

[Explanation of symbols]

Reference Signs List 1 clock input terminal 2 clock tree circuit 3 bypass clock circuit 4 data input terminal 5, 6 D-type flip-flop (first data latch circuit) 7 D-type flip-flop (second data latch circuit) 8 data output terminal 10 integration Circuit (IC)

Claims (3)

[Claims] A clock tree circuit for distributing a clock obtained by shaping the waveform of an external input clock to a plurality of circuits in an integrated circuit with substantially equal propagation delay times; A clock circuit comprising: a bypass clock circuit that supplies a last stage circuit connected to a data output terminal of the circuit with a propagation delay time smaller than a propagation delay time of the clock tree circuit. 2. The plurality of circuits to which a clock is input by the clock tree circuit are a plurality of first data latch circuits connected in cascade with each other, and the last stage to which a clock is input by the bypass clock circuit. 2. The circuit according to claim 1, wherein the circuit is a second data latch circuit that latches data output from the plurality of first data latch circuits at a timing of an output clock of the bypass clock circuit. Clock circuit. 3. The clock circuit according to claim 1, wherein the bypass clock circuit includes at least one buffer.