JPH10163883A - Code rate variable error correction transmitter - Google Patents

Abstract

(57) [PROBLEMS] To enable a single frequency clock generator to generate a plurality of convolutionally encoded data. SOLUTION: Parallel data DATAB output from an input signal generation device 11 is supplied to a parallel / serial converter 12 and converted into parallel data DATA. The clock thinning circuit 16 generates the clock generation circuit 15 based on the coding rate (mn) / m.
Out of the m clocks CLK0 output by
A data read clock CLK is generated. The convolutional encoder 13 performs two types of convolutional operations and generates encoded data CDATA to which an error correction code is added by a clock CLK.
Output 1 and 2. The puncturer circuit 14 deletes data at a predetermined position from the parallel encoded data according to the encoding rate, and outputs transmission symbol data in synchronization with the symbol clock CLKS.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding rate variable error correction transmitting apparatus for adding a convolutional error correcting code to input data and performing digital transmission by selectively using an arbitrary coding rate. Things.

[0002]

2. Description of the Related Art In a recent digital communication system, a coding rate can be easily changed by puncturing processing in convolutional coding, and convolutional coding apparatuses have been put to practical use in various fields. For example, as a coding rate variable error correction transmitting apparatus using a puncture coding technique, a document "Study on a variable coding rate Viterbi decoder and its operation" Y. Yasuda et.al. "Development variable rat
e decorder and its Performance characteristic "6t
h Int.Conf.on Dig. Sat.Commun.

FIG. 7 is a block diagram showing a configuration example of a conventional coding rate variable error correction transmitting apparatus (hereinafter referred to as a convolutional coding apparatus) 20. The coding rate R = B / A means the code amount B
For example, when the error correction additional code is generated and transmitted by performing, for example, two types of convolution processing on the transmission data, the number of error correction additional codes included in the transmission symbol A is AB.
Means that The convolutional encoder 20 shown in FIG.
Is a device that generates encoded data of coding rates R = 3/4 and R = 5/6. In the figure, DATAB is parallel input data, and CLKB is an input clock. Also TD
ATA1 and TDATA2 are output symbols.

[0004] A convolutional encoder 20 includes a serial-to-parallel converter 21 for converting parallel input data into serial data, a convolutional encoder 22 for performing two types of convolutional encoding at a coding rate of 1/2, and a punctured encoder. Puncturing circuit 23 for processing,
A first synchronous clock generator 24 that generates a synchronous clock whose frequency is 3/2 times the output symbol clock in synchronization with the input clock when the coding rate is 3/4, and when the coding rate is 5/6. A second synchronous clock generator 25 for generating a synchronous clock whose frequency is 5/3 times the output symbol clock in synchronization with the input clock, a synchronous clock generator 24 or a synchronous clock depending on the coding rate Generator 2
5, and a synchronous switch 27 for generating a symbol clock in synchronization with the input clock.

The synchronous clock generators 24, 25,
And the synchronous symbol clock generator 27 is generally a PLL
Use a synchronous oscillation circuit. 8 to 10 are time charts showing the appearance of signals at various parts of the convolutional encoding device 20.

[0006] The operation of the convolutional encoder 20 configured as described above will be described. First, 8-bit parallel data is input to the parallel-to-serial converter 21 as shown in FIG. The coding rate is R, and the transmission symbol frequency is f
Assuming that s, 2 · fs · R / 8 as shown in FIG.
The input clock CLKB having the frequency of
Is input to This 8-bit parallel data DATAB
Is a data read clock C as shown in FIG.
The serial data DATA ′ as shown in FIG.
Is converted to Then, when this data DATA 'is input to the convolutional encoder 22, one input data D (j) shown in FIG. 9B is output at the timing j as shown in FIGS. 9C and 9D. Encoded data CDATA1 ',
Data C1 (j), C2 (j) as CDATA2 '
Are output simultaneously.

FIGS. 9 (a) to 9 (g) show data processing when the coding rate is 3/4, while FIGS. 10 (a) to 10 (g) show data processing.
Indicates data processing when the coding rate is 5/6. FIG.
The data CDATA1 'and CDATA2' shown in FIGS. 10C and 10D or FIGS.
When data is input to 3, data at a position predetermined by the coding rate R is deleted. In FIG. 9, C1 (2), C2
(3) is the erased data, and in FIG.
(2), C2 (3), C1 (4) and C2 (5) are the erased data. Which data C1 (x), C2 (y)
Is deleted in advance so that the error correction characteristic at the time of Viterbi decoding is optimized.

Then, by using the output symbol frequency clock CLKS shown in FIG. 9 and FIG. 11 (e), the remaining data is read out in a predetermined order according to the coding rate, thereby obtaining FIG. ) And FIGS. 11 (f), (g)
Output symbol data TDATA1, TDA
TA2 can be generated. Such a thinning process is called a punctured process.

Here, the data read clock CLK 'of the parallel-serial converter 21 and the operation clock CLK' of the convolutional encoder 22 are switched by the changeover switch 26 in accordance with the coding rate R and output. That is, of the synchronous clock generators 24 and 25, when the coding rate R is 3/4, the output clock CLK of the synchronous clock generator 24
1, the output clock CLK2 of the synchronous clock generator 25 is selected when the coding rate R is 5/6.

[0010]

However, in the above configuration, a larger coding rate R, for example, R = 2
When adding functions of coding rates such as / 3 and R = 7/8, the number of synchronous clock generators must be provided by the number of coding rates, and the number of parts of the transmission device increases, In addition, there is a problem that the cost is increased.

The present invention has been made in view of such a conventional problem, and has been made in consideration of the problems described above. One fixed clock generator is capable of generating punctured convolutional data having a plurality of coding rates. A variable rate error correction transmission device is provided.

[0012]

According to the first aspect of the present invention, mn (m, n is m> n) read from a signal source is used.
Is a positive integer that satisfies the following equation, and if m data is an error correction additional code with a coding rate R = (mn) / m, the data of the signal source is a convolutional code at a coding rate R. A coding rate variable error correction transmitting apparatus for converting and transmitting,
Clock generating means for generating a clock having a frequency twice as high as the transmission symbol frequency; and clock thinning for generating a data read clock by thinning out n clocks for every m clocks among the clocks output from the clock generating means. Means for generating a transmission symbol clock by dividing the clock output from the clock generation means by half.
1 / p frequency dividing means for inputting a data read clock of the clock thinning means, dividing the data into 1 / p (p is a positive integer of 2 or more) to generate a frequency-divided clock, and an input clock In parallel with this, the parallel data input from the signal source is temporarily held in an internal buffer, and the parallel data in the internal buffer is converted into serial data and output in synchronization with a data read clock output from the clock thinning means. Parallel / serial conversion means for performing two types of convolutional encoding on serial data output from the parallel / serial conversion means, and outputting a plurality of encoded data in parallel; From the parallel encoded data output from the embedded encoding means, the encoded data at a position predetermined by the encoding rate R is deleted, and the remaining encoded data is replaced with the 1 /
In synchronization with the symbol clock output from the frequency dividing means,
And puncturing means for rearranging in a predetermined order according to the coding rate R to output two transmission symbol data, wherein the puncturing means outputs two transmission symbol data in synchronization with a frequency-divided clock output from the 1 / p frequency-dividing means. The parallel data read from the signal source and the input clock synchronized with the frequency-divided clock are supplied to the parallel-to-serial conversion means, and the values of the positive integers m and n of the clock thinning means are changed to perform arbitrary encoding. The transmission symbol data of the rate R is transmitted.

Further, according to the invention of claim 2 of the present application, m data (m, n is a positive integer satisfying m> n) data read from a signal source are converted into m data. Coding rate R
= (M−n) / m, a code rate variable error correction transmitting apparatus for convolutionally coding the data of the signal source at a coding rate R and transmitting the data, wherein the transmission symbol frequency is 2 Clock generating means for generating a clock having a double frequency; clock thinning means for generating a data read clock by thinning out n clocks for every m clocks among the clocks output from the clock generating means;
A 1/2 divider for generating a transmission symbol clock by dividing the clock output from the clock generator by 1/2, and a data read clock of the clock thinner are input and divided by 1 / p. 1 / p frequency dividing means for generating a frequency-divided clock, and a data read clock output from the clock thinning means for temporarily storing parallel data input from the signal source in an internal buffer in synchronization with the frequency-divided clock. Parallel-serial conversion means for converting parallel data in the internal buffer into serial data and outputting the data in synchronization with the internal buffer; and performing two types of convolutional encoding on the serial data output from the parallel-serial conversion means. Convolutional encoding means for outputting the encoded data in parallel, and a position determined in advance by the encoding rate R from the parallel encoded data output from the convolutional encoding means. The coded data is erased, and the remaining coded data is synchronized with the symbol clock output from the 分 frequency dividing means and rearranged in a predetermined order according to the coding rate R for two transmissions. Puncturing means for outputting symbol data, wherein the parallel / serial conversion means reads out the parallel data of the signal source using the frequency-divided clock output from the 1 / p frequency dividing means, and the clock thinning means The transmission symbol data of an arbitrary coding rate R is transmitted by changing the values of the positive integers m and n.

With such a configuration, by changing the positive integers m and n, it is possible to generate an error correction additional code having an arbitrary coding rate by using one clock generating means. Then, transmission symbol data of a specific coding rate can be transmitted according to the noise level of the transmission path.

In particular, in the configuration according to the second aspect, in addition to the above-mentioned operation, it is possible to use only two cables for the signal source and the coding rate variable error correction transmitting apparatus.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) A coding rate variable error correction transmitting apparatus (convolutional coding apparatus) according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a convolutional encoding device 10 according to the present embodiment. The convolutional encoder 10 includes a serial-to-parallel converter 12 for converting parallel input data into serial data as in the conventional example.
And a convolutional encoder 13 that performs two types of convolutional encoding when serial data is input, and a puncture circuit 14 that performs puncturing processing on two sets of encoded data. .

An input signal generator 11 provided at a stage preceding the convolutional encoder 10 synchronizes parallel data DATAB (here, 8 bits) in synchronization with an input clock CLKB.
Is a signal source that outputs The parallel-to-serial converter 12 has an internal buffer, accumulates parallel data DATAB in the internal buffer based on the input clock CLKB ', reads data from the internal buffer in synchronization with the data read clock CLK, and converts the data into serial data DATA. Output.

The convolutional encoder 13 comprises, for example, a circuit in which a large number of 1-bit delay units are connected in series, and an exclusive OR circuit for calculating the exclusive OR of outputs of a plurality of specified delay units. Two sets of convolution circuits are provided to perform two types of convolution operations. The puncturing circuit 14 deletes the convolutional coded data at a predetermined position according to the specified coding rate R, and reduces the remaining coded data to １ ／.
This circuit generates output symbol data in an order predetermined by the coding rate in synchronization with the symbol clock CLKS from the frequency divider 17.

The clock generation circuit 15 is a generator for generating a clock CLK0 having a frequency twice as high as the symbol clock CLKS. When the coding rate R is B / A = (mn) / m (m and n are positive integers satisfying m> n), the clock thinning circuit 16 generates a clock for the input m clocks CLK0. Is output without changing n times. The 1/2 frequency divider 17 sets the input clock CLK0 to 1
/ 2 frequency divider. The 1/8 frequency divider 18 generates 1 for every 8 clocks of the input aperiodic clock CLK.
This is a frequency divider that outputs a clock as a divided clock.
In general, when p-bit data is used as the minimum unit code, a 1 / p frequency divider is used.

The convolutional coding apparatus 1 configured as described above
The operation of 0 will be described with reference to FIGS. First, as shown in FIG. 2A, the clock generator 15 shown in FIG. 1 has a clock CLK having a frequency twice the output symbol frequency.
Generates 0. When the coding rate is 3/4, that is, m = 4
When n = 1, the clock CLK0 is output by the clock thinning circuit 16 once every four clocks without changing the clock. This output is CLK in FIG. Next, this clock CLK is input to the 1/8 frequency divider 18, and a clock is output once every eight clocks. This is the CLKB in FIG.

The clock CLKB is input to the input signal generator 11. Then, as shown in FIG. 2D, the transmission data DATAB is read in parallel, and the divided clock CLKB is turned back by the input signal generation device 11 to output the input clock CLKB ′, and the parallel data DATAB is output.
B is input to the serial / parallel converter 12 and held in the internal buffer. The data held in the internal buffer is read by the data read clock CLK from the clock thinning circuit 16 and is converted into serial data DATA. This is shown in FIG. As shown in the figure, data D (1) to
The retention period of D (9) differs depending on the data.

FIG. 3 is a time chart in which the time axis of FIG. 2 is slightly enlarged. FIG. 3 input to the convolutional encoder 13
An error correction additional code is added to the data DATA of (c) by two types of convolution operations, and is converted into encoded data CDATA1 and CDATA2 as shown in FIGS. 3 (d) and 3 (e). These data are input to the puncture circuit 14. On the other hand, the output CLK0 from the clock generator 15 is input to the 1/2 frequency divider 17, and is output as shown in FIG.
Is generated. Therefore, the puncturing circuit 14 determines the coding rate R, here 3/4.
Data C1 (2) and C2 at positions predetermined by
(3) is deleted, and the transmission symbol clock CLKS described above is deleted.
Thus, transmission data TDATA1 and TDATA2 are output. These transmission data correspond to C1 (1), C2 (2), C2 (1), C2 shown in FIGS. 3 (f) and 3 (g), respectively.
1 (3).

Considering the input / output of data in four cycles of clock CLK0 as shown in FIG.
C1 (1) and C2 (2) of DATA1 and TDATA2
C2 (1) and C1 (3) are transmitted. Then, in a coding rate variable error correction receiving device (convolutional decoding device) not shown, these data C2 (1) and C2 (2)
And C2 (1) and C1 (3), null data is inserted at the punctured position, and then data D (1) to D (3) are reproduced by Viterbi decoding. That is, data D (i) is set to 3 for 4 bits of transmission data TDATA.
Since the bits are decoded, the coding rate R becomes 3/4.

Next, the operation when the coding rate is 5/6 is shown in FIGS. In this case, m = 6, n = 1,
The clock thinning circuit 16 outputs the clock once every six clocks CLK0 shown in FIG. 4 (a) without changing the clock, and outputs the data read clock CL as shown in FIG. 4 (b).
Generate K. This clock CLK is converted to a parallel / serial converter 1
2, serial data DATA having different data retention periods are obtained as shown in FIG.

FIG. 5 is a time chart in which the time axis of FIG. 4 is slightly enlarged. The convolutional encoder 13 performs two types of convolutional operations using the clock CLK output from the clock thinning circuit 16 and adds an error correction additional code. Thus, the data DATA of FIG.
The encoded data CDATA1, CDATA as shown in (d) and (e).
Each is converted to DATA2. These data are input to the puncturing circuit 14, and are transmitted at a predetermined position based on the coding rate by the transmission symbol clock CLKS output from the 1/2 frequency divider 17, for example, C1 (2),
C2 (3), C1 (4), and C2 (5) are each erased. Then, the transmission symbol clock CL shown in FIG.
Transmission data TDATA1 and TDATA by KS
2 is output. These transmission data are shown in FIG.
C1 (1), C2 (2), C2 (4) and C2 (1), C1 (3), C1 (5) shown in FIG.

As shown in FIG. 5, when input / output of data is considered in six cycles of clock CLK0, output symbol data T
C1 (1), C2 (2), C2 (4) of DATA1,
C2 (1), C1 (3) and C1 (5) of TDATA2 are transmitted. Then, in a coding rate variable error correction receiving device (convolutional decoding device) not shown, these data C1
Using data (1) to C2 (4) and C2 (1) to C1 (5), data D (1) to D (1)
Play (5). That is, since data D (i) is decoded by 5 bits for 6 bits of the transmission symbol TDATA, the coding rate R becomes 5/6.

As described above, when the receiving apparatus infers a transition state of data retrospectively, encoded data at a position considered to have a low likelihood value is deleted in advance in the puncturing circuit 14 of the transmitting apparatus. I do. And the symbol clock CLK
By S, transmission data TDATA1 and TDATA2
Is output. It should be noted that for other coding rates, for example, R = ２ and R = 7/8, the clock thinning rate is controlled by the clock thinning circuit 16 so that transmission data can be transmitted using one clock generating circuit 15. Can be generated.

According to the above-mentioned method, the transmitting apparatus and the receiving apparatus are controlled according to the attenuation of airborne radio waves in a communication satellite or a broadcasting satellite or the level of parasitic noise in a transmission path such as data transmission using a cable. By changing the coding rate in conjunction with the apparatus, it is possible to adaptively control the data error rate to be equal to or less than a predetermined value.

(Embodiment 2) Next, a coding rate variable error correction transmitting apparatus (convolutional coding apparatus) according to a second embodiment of the present invention will be described with reference to the drawings.
FIG. 6 is a block diagram showing a configuration of a convolutional encoding device 10A according to the present embodiment, which includes a serial-to-parallel converter 12A, a convolutional encoder 13, a puncture circuit 14, a clock generation circuit 15, and a clock thinning circuit 16. , 1/2 frequency divider 17,
The configuration including the 1/8 frequency divider (generally, the 1 / p frequency divider) 18 is the same as that of the first embodiment.

The input signal generator 11A is a signal source that outputs parallel data DATAB in synchronization with the input clock CLKB. The difference between the convolutional encoding device 10A of the present embodiment and the convolutional encoding device 10 of the first embodiment is that the frequency-divided clock CLKB output from the 1/8 frequency divider 18 is used.
Is input to the input signal generation device 11A and to the parallel-to-serial converter 12A.

With this configuration, the parallel-to-serial converter 1
2A, the input data DATAB is converted to the convolutional coding device 10.
A can be captured by a clock CLKB from inside A. This can reduce the number of connection cables between the input signal generation device 11A and the convolutional encoding device 10A.
Note that performing convolutional coding on the parallel data DATAB and performing puncturing based on the specified coding rate R is the same as that of the first embodiment.

According to this method, the length of the connection cable depends on the frequency of the frequency-divided clock CLKB for reading parallel data, and the length of the input data DAT within the return delay time.
It is limited to the range where AB can be taken.

[0033]

As described above, according to the present invention, a positive integer m
, Transmission symbol data having an arbitrary coding rate can be generated using a single clock generation unit. Therefore, the clock-related circuit configuration in the coding rate variable error correction transmission device is simplified, and hardware cost can be reduced.

In particular, according to the second aspect of the present invention, in addition to the above-described effects, two cables can be connected to the signal source.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a coding rate variable error correction transmitting apparatus according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the parallel-serial converter in the case of a coding rate of 3/4 in the first embodiment.

FIG. 3 is a timing chart showing operations of a convolutional encoder and a puncturing circuit in a case where a coding rate is 3/4 in the first embodiment.

FIG. 4 is a timing chart showing an operation of the parallel-serial converter when the coding rate is 5/6 in the first embodiment.

FIG. 5 is a timing chart showing operations of a convolutional encoder and a puncturing circuit in a case where the coding rate is 5/6 in the first embodiment.

FIG. 6 is a block diagram illustrating a configuration of a coding rate variable error correction transmitting apparatus according to a second embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration example of a conventional coding rate variable error correction transmission device.

FIG. 8 is a timing chart showing an operation of the parallel-serial converter when the coding rate is 3/4 in the conventional example.

FIG. 9 is a timing chart showing an operation of the parallel-serial converter in the case of a coding rate of 3/4 in a conventional coding rate variable error correction transmitting apparatus.

FIG. 10 is a timing chart showing the operation of a convolutional encoder and a puncture circuit in the case of a coding rate of 5/6 in the conventional coding rate variable error correction transmitting apparatus.

[Explanation of symbols]

 10, 10A Code rate variable error correction transmission device 11, 11A Input signal generation device 12, 12A Parallel-serial converter 13 Convolutional encoder 14 Puncture circuit 15 Clock generator 16 Clock thinning circuit 17 1/2 frequency divider 18 1/8 frequency divider

Claims (2)

[Claims] 1. mn (m, n) read from a signal source
Is a positive integer that satisfies m> n), if m data is an error correction additional code with a coding rate R = (mn) / m, the data at the signal source is A code rate variable error correction transmitting apparatus for performing convolutional coding with R and transmitting the clock, comprising: clock generating means for generating a clock having a frequency twice as high as a transmission symbol frequency; Clock thinning means for generating a data read clock by thinning out n clocks for each clock, and a 1/2 minute for generating a transmission symbol clock by dividing the clock output by the clock generating means by half Frequency dividing means; a 1 / p frequency dividing means for inputting a data read clock of the clock thinning means and dividing the frequency to 1 / p (p is a positive integer of 2 or more) to generate a frequency divided clock; In parallel, the parallel data input from the signal source is temporarily stored in an internal buffer, and the parallel data in the internal buffer is converted into serial data and output in synchronization with a data read clock output from the clock thinning means. Parallel-to-serial conversion means, two kinds of convolutional coding for serial data output from the parallel-to-serial conversion means, and convolutional coding means for outputting a plurality of coded data in parallel; From the parallel encoded data output by the encoding means, the encoded data at a position predetermined by the encoding rate R is deleted, and the remaining encoded data is output from the 1/2 frequency dividing means. Puncturing means for synchronizing with a symbol clock and rearranging in a predetermined order according to the coding rate R to output two transmission symbol data, The parallel data read from the signal source in synchronization with the frequency-divided clock output from the 1 / p frequency dividing means and the input clock synchronized with the frequency-divided clock are supplied to the parallel-to-serial conversion means. A variable coding rate error correction transmission apparatus characterized in that transmission symbol data having an arbitrary coding rate R is transmitted by changing values of positive integers m and n. 2. mn (m, n) read from a signal source
Is a positive integer that satisfies m> n), if m data is an error correction additional code with a coding rate R = (mn) / m, the data at the signal source is A code rate variable error correction transmitting apparatus for performing convolutional coding with R and transmitting the clock, comprising: clock generating means for generating a clock having a frequency twice as high as a transmission symbol frequency; Clock thinning means for generating a data read clock by thinning out n clocks for each clock, and a 1/2 minute for generating a transmission symbol clock by dividing the clock output by the clock generating means by half Frequency dividing means; a 1 / p frequency dividing means for inputting a data read clock of the clock thinning means and dividing the frequency to 1 / p (p is a positive integer of 2 or more) to generate a frequency divided clock; The parallel data input from the signal source is temporarily held in an internal buffer in synchronization with a clock, and the parallel data in the internal buffer is converted into serial data in synchronization with a data read clock output from the clock thinning means. Parallel-to-serial conversion means for outputting, convolutional coding means for performing two types of convolutional encoding on serial data output from the parallel-to-serial conversion means, and outputting a plurality of encoded data in parallel; From the parallel coded data output from the convolutional coding means, the coded data at a position predetermined by the coding rate R is deleted, and the remaining coded data is output from the 1/2 frequency dividing means. Puncturing means that synchronizes with the symbol clock to be output and outputs two transmission symbol data by rearranging in a predetermined order according to the coding rate R, The parallel-to-serial conversion means reads out the parallel data of the signal source using the frequency-divided clock output from the 1 / p frequency-dividing means, and changes the values of the positive integers m and n of the clock thinning-out means. Wherein the transmission symbol data having the coding rate R is transmitted.