JPH10163863A - Monitoring circuit of phase locked loop circuit - Google Patents

Abstract

(57) Abstract: A monitoring circuit for a phase-locked loop circuit detects an out-of-synchronization of the phase-locked loop circuit, a stop of operation of a voltage controlled oscillator, and the like, and issues an alarm signal. SOLUTION: A first flip-flop F1 for dividing an output signal of a voltage controlled oscillator 1 or an output signal (Fout signal) divided by a frequency divider 4 or the like into two, and an output of a * Q terminal of the flip-flop F1 A phase comparator 2 including a second flip-flop F2 for inputting a signal and a reference signal (Fin signal) and an exclusive logic circuit G1, and averaging the phase comparison output signal of the phase comparator 2 to obtain a voltage. Controlled oscillator 1
And a low-pass filter 3 having a control voltage of the phase locked loop circuit.
n signal) divided by 2 by a third flip-flop F3
And a fourth flip-flop F4 for inputting the Q terminal output signal and the * Q terminal output signal of the second flip-flop F2, and a peak detection for detecting a peak of the Q terminal output signal and outputting an alarm signal ALM. And a unit 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monitoring circuit for a phase locked loop circuit that synchronizes a phase with a relatively high-speed clock signal. A phase locked loop circuit including a voltage controlled oscillator is used to generate a clock signal that is phase-locked to an input clock signal. The clock signal at the time of loss of synchronization or deterioration of the voltage controlled oscillator in the phase locked loop circuit is not synchronized with the input clock signal, so that signal processing according to the clock signal cannot be performed normally. Therefore, a monitoring circuit that detects such an abnormal state and outputs an alarm signal is required.

[0002]

2. Description of the Related Art FIG. 13 is an explanatory view of a main part of an optical transmission unit.
A case is shown in which 8-channel data or 8-parallel data DATA and a clock signal CLK1 are input to the optical transmission unit 100, converted into serial data SD, further converted into an optical signal, and transmitted to an optical fiber transmission line. In the figure, 101 is a voltage controlled oscillator (VCO), 102 is a phase comparator, 103
Is a low-pass filter (LPF), 104 is a frequency divider, 10
5 is a monitoring circuit (PLALLM), 106 is a phase locked loop circuit, 107 is a parallel / serial converter (P / S), and 108 is an electric / optical converter.

A phase locked loop circuit 106 uses a clock signal CLK1 as an input frequency Fin, an output signal of the frequency divider 104 as an output frequency Fout, and a phase comparator 102.
, And a voltage corresponding to the phase difference is averaged by a low-pass filter 103 to be a control voltage, and the output frequency of the voltage controlled oscillator 101 is controlled. In this case, the output frequency is a frequency that is a multiple of the frequency division ratio of the frequency divider 104. The frequency divider 104 adjusts the frequency of the voltage controlled oscillator 101 to 1 in order to match the frequency Fin of the clock signal CLK1. / 8.

Further, eight channels or eight parallel data DATA synchronized with the clock signal CLK1 are transmitted to the parallel / serial conversion unit 1.
At 07, the output signal of the voltage controlled oscillator 101 is parallel-to-serial converted as the clock signal CLK2, and the serial data SD and the clock signal CLK2 (= 8 × CLK1) are transferred to the electro-optical converter 108, and the serial data The SD is converted into an optical signal and transmitted to an optical fiber transmission line. The monitoring circuit 105 monitors whether the control voltage of the voltage controlled oscillator 101 is within a normal range, and when the control voltage exceeds the normal range, determines that the synchronization is lost and outputs an alarm signal.

FIG. 14 is an explanatory view of a conventional example, showing the above-mentioned phase locked loop circuit and the monitoring circuit 105, 109 is a voltage shift & offset unit, 110 is a differential amplifier, 11
1, 112 are first and second flip-flops, 113 is an exclusive logic circuit, 114 and 115 are resistors, 116 is a capacitor, 117 and 118 are comparators, and 119 is an OR circuit (OR).

D of the flip-flops 111 and 112 is a data terminal, C is a clock terminal, and Q and * Q are output terminals of a non-inverted output signal and an inverted output signal. * Q is Q
Shows the reversal of. PD and * PD are phase comparison output signals, and * PD indicates inversion of PD. Fin indicates an input frequency, Fout indicates an output frequency, VRH and VRL indicate a reference voltage, ALM indicates an alarm signal, and Vo indicates a control voltage.

The phase comparator 102 compares the phase of the reference signal of the input frequency Fin with the phase of the output signal of the output frequency Fout obtained by dividing the output signal of the voltage controlled oscillator 101 by the frequency divider 104. Flip-flop 11
1, the output signal is divided by two, the * Q terminal output signal of the first flip-flop 111 is input to the data terminal D of the second flip-flop 112, and its clock terminal C
, A Q terminal output signal and a Q terminal output signal of the flip-flop 111 are input to an exclusive logic circuit 113, and a phase comparison output signal P
D and * PD are input to the differential amplifier 110.

The differential amplifier 110 obtains the difference between the complementary phase comparison output signals PD and * PD to obtain an amplified phase comparison output signal, and outputs the amplified phase comparison output signal.
In step 09, voltage adjustment for correcting the control voltage characteristic of the voltage controlled oscillator 101 is performed. The voltage shift & offset unit 109 can be omitted when the characteristics of the voltage controlled oscillator 101 are uniform. A voltage obtained by averaging the output signal of the voltage shift & offset unit 109 via the low-pass filter 103 is used as a control voltage V of the voltage controlled oscillator 101.
o. The low-pass filter 114 includes a resistor 114,
This shows a case of a configuration composed of 115 and a capacitor 116.

The monitoring circuit 105 monitors the control voltage Vo, and when the control voltage Vo rises above the reference voltage VRH, sets the output signal of the comparator 117 to “1” and outputs “1” through the OR circuit 119. Output the alarm signal ALM. When the control voltage Vo drops below the reference voltage VRL, the output signal of the comparator 118 is set to "1" and the OR circuit 1
An alarm signal ALM of "1" is output through the terminal 19.

FIG. 15 is a diagram for explaining the normal operation of the conventional example. The same reference numerals as in FIG. 14 denote the same signals.
Reference numeral 1 denotes a Q and * Q terminal output signal of the first flip-flop 111, Q2 denotes a Q terminal output signal of the second flip-flop 112, and DF denotes an output signal of the differential amplifier 110.

It is assumed that the phase synchronization is established when the input frequency Fin and the output frequency Fout are the same, and the phase relationship shown (180 ° phase difference) is established. In this state,
The Q and * Q terminal output signals of the first flip-flop 111 are obtained by dividing the output frequency Fout by 2 as shown by Q1 and * Q1, and the second flip-flop 112
The Q terminal output signal shown in FIG. The phase comparison output signal PD becomes “0” when Q1 = Q2 and “1” when Q1 ≠ Q2, and the differential amplifier 110 outputs the phase comparison output signal PD to the − terminal and the phase comparison output signal * PD. Since the signal is input to the + terminal, the output signal is as shown by DF, and the average voltage of the output signal DF becomes Vo. That is,
By averaging with the low-pass filter 103,
The control voltage Vo is obtained, and the voltage controlled oscillator 101
n = Fout and the illustrated phase state is maintained.

FIG. 16 is a diagram for explaining the relationship between the control voltage and the output frequency. When the voltage control oscillator 101 has the characteristic of the straight line a1, when the output frequency Fout changes within the range of FA, the control voltage Vo changes to VA It changes within the range, and the voltage controlled oscillator 101 is controlled so that Fin = Fout. In that case, the monitoring circuit 105 shown in FIG.
Sets the control voltage range VA, for example, based on the reference voltages VRH and VRL, and outputs the alarm signal ALM when the control voltage Vo exceeds the range VA.

When the characteristic of the voltage controlled oscillator 101 changes from a straight line a1 to a2 due to aging or environmental change, F
The control voltage Vo for setting in = Fout is V1 to V
When the characteristic changes from the straight line a1 to the straight line a3, the control voltage Vo for setting Fin = Fout changes from V1 to V1 ″. Therefore, the phase can be synchronized with the change in the characteristic. .

FIG. 17 is a diagram for explaining the operation when the control voltage changes, and the same reference numerals as those in FIG. 15 indicate the same signals. This is a case where the signal phase of the output frequency Fout is delayed with respect to the signal phase of the input frequency Fin as compared with the case shown in FIG.
The phase comparison output signal PD from the phase comparator 102 (see FIG. 14) is no longer at a duty of 50%, and the output signal DF of the differential amplifier 110 has a high-level period shorter than a low-level period, and a low-pass filter 109. Is lower than the normal control voltage V1.
Therefore, the voltage controlled oscillator 101 operates to advance the phase of the output signal.

FIG. 18 is a diagram for explaining the operation when the control voltage changes. The same reference numerals as those in FIGS. 15 and 17 denote the same signals. The output frequency F with respect to the signal phase of the input frequency Fin
This is a case where the signal phase of out is advanced as compared with the case shown in FIG. 15, and the phase comparison output signal PD from the phase comparator 102 (see FIG. 14) is no longer 50% duty and the output of the differential amplifier 110 In the signal DF, the high level period is longer than the low level period, and the control voltage Vo is higher than the normal control voltage V1, contrary to the case of FIG. Therefore, the voltage controlled oscillator 101 operates to delay the phase of the output signal.

FIG. 19 is an explanatory diagram of control voltage monitoring in a conventional example. In the case where Fin = Fout, the control voltage Vo is V1, the fluctuation standard of the input frequency Fin is ± a, and the fluctuation of the control voltage Vo due to a temperature change or the like. ± b, voltage-controlled oscillator 101
± c is the variation due to the secular change of ±, and the variation range is ± (a
+ B + c), the upper limit is VRH, and the adjustment is VRL. The upper limit VRH and the adjustment VRL are set as reference voltages VRH and VRL of the monitoring circuit 105 in FIG. 14 to set a normal operation range, and the control voltage Vo is set as a reference. When the voltage becomes higher than the voltage VRH or becomes lower than the reference voltage VRL, it is determined that there is an abnormality such as loss of synchronization or the like, and an alarm signal ALM is output.

[0017]

As shown in FIG. 14, a monitoring circuit for a conventional phase locked loop circuit includes a control voltage Vo of a voltage controlled oscillator 101 and reference voltages VRH and VRL.
When the control voltage exceeds the reference voltage VRH or rises above the reference voltage VRL or falls below the reference voltage VRL, the control voltage exceeds the normal operation range. Output. However, when the voltage controlled oscillator 101 deteriorates and the output frequency Fout is fixed to a certain value different from the input frequency Fin,
A state occurs in which the alarm signal ALM is not output.

Such a state will be described with reference to FIG. 20, FIG. 17, FIG. 17, and FIG.
And FV indicate the same signal, FV indicates a change in the phase comparison output signal PD in an analog manner by a solid line, and the control voltage Vo averaged by the low-pass filter 103 is indicated by a chain line.

That is, when the output frequency Fout is different from the input frequency Fin, the phase comparison output signal PD has a waveform whose pulse width changes sequentially in accordance with the frequency difference. In addition, the part shown with a dotted line shows an uncertain part.
Therefore, when the pulse width gradually becomes narrower from the wide pulse width, the waveform becomes analog-like in a sawtooth shape as indicated by a solid line of FV.
Therefore, by averaging through the loop filter 103, the phase comparison output signal PD becomes the same control voltage Vo as when the duty is 50% normal, and the monitoring circuit 105
There is a problem that the control voltage Vo is regarded as normal and the alarm signal ALM is not output. SUMMARY OF THE INVENTION An object of the present invention is to make it possible to reliably detect a case where the output frequency is fixed due to loss of synchronization of a phase locked loop circuit and deterioration of a voltage controlled oscillator.

[0020]

The monitoring circuit of the phase locked loop circuit according to the present invention comprises: (1) dividing the output signal of the voltage controlled oscillator 1 or an output signal obtained by dividing the output signal (Fout signal) by 2; A first flip-flop F1, a second flip-flop F2 receiving an inverted output signal (* Q terminal output signal) of the first flip-flop F1 and a reference signal (Fin signal), and a second flip-flop F2. The output signal of the flip-flop F2 and the first flip-flop F1
And a low-pass filter 3 for averaging the output signal of the phase comparator 2 to obtain a control voltage of the voltage-controlled oscillator 1. In a monitoring circuit of the loop circuit, a third flip-flop F3 for dividing the signal obtained by inverting the reference signal into two, an output signal of the third flip-flop F3, and an inverted output of the second flip-flop F2 A fourth flip-flop F4 for inputting a signal (* Q terminal output signal) and a peak detection for outputting an alarm signal ALM by detecting a peak of an output signal (Q terminal output signal) of the fourth flip-flop F4 And a unit 7.

(2) The peak detector has a configuration for detecting peaks of the non-inverted output signal (Q terminal output signal) and the inverted output signal (* Q terminal output signal) of the fourth flip-flop F4. A gate circuit that outputs an alarm signal when both of the peak detection output signals are at a high level can be provided.

(3) a second peak detector for receiving an output signal of the voltage controlled oscillator 1 or an inverted output signal and a non-inverted output signal of an output signal obtained by dividing the output signal, and detecting respective peaks; It is possible to provide a gate circuit for outputting an alarm signal when one of the second peak detecting sections and the other peak detecting output signal are different.

(4) a first flip-flop F1 for dividing the output signal of the voltage-controlled oscillator 1 or an output signal obtained by dividing the output signal by two, and the first flip-flop F
A second flip-flop F2 for inputting the inverted output signal of the first F1 and the reference signal, and comparing the output signal of the second flip-flop F2 with the output signal of the first flip-flop F1 to obtain a phase comparison output signal. An output phase comparator 2,
In a monitoring circuit of a phase-locked loop circuit including a low-pass filter 6 averaging the output signal of the phase comparator 2 and setting the average as a control voltage of the voltage-controlled oscillator 1, a signal obtained by inverting the reference signal is divided by two. A third flip-flop, a fourth flip-flop receiving an output signal of the third flip-flop and an inverted output signal of the second flip-flop, a differentiating circuit receiving an output signal of the flip-flop, The comparator includes a comparator for comparing a differential output signal of the differentiating circuit with a reference voltage, and a latch circuit for latching an output signal of the comparator when the differential output signal exceeds the reference voltage and using the signal as an alarm signal.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory diagram of a first embodiment of the present invention, wherein 1 is a voltage controlled oscillator (VCO), 2 is a phase comparator, 3 is a low-pass filter (LPF), and 4 is Frequency divider, 5 is a differential amplifier, 6 is a voltage shift and offset unit, 7 is a peak detection unit, F1 to F4 are first to fourth flip-flops, G1 is an exclusive logic circuit, R1 to R3 are resistors, C1 and C2 indicate capacitors.

The phase locked loop circuit includes a voltage controlled oscillator 1
, A frequency divider 4, a phase comparator 2, a differential amplifier 5, a voltage shift & offset unit 6, and a low-pass filter 3. The phase comparator 2 uses the reference signal of the input frequency Fin and the output frequency The phase of the output signal of Fout (frequency-divided output signal of frequency divider 4) is compared with the output signal, and voltage-controlled oscillator 1 is controlled so that phase synchronization is established.

The phase comparator 2 comprises first and second flip-flops F1 and F2 and an exclusive logic circuit G1, and inputs the Q terminal output signals of the first and second flip-flops F1 and F2. A phase comparison output signal PD and an inverted phase comparison output signal * PD are output from the exclusive logic circuit G1 and input to the differential amplifier 5. The low-pass filter 3 is composed of resistors R1 and R2 and a capacitor C1, and applies an output signal obtained by averaging input signals to the voltage-controlled oscillator 1 as a control voltage. The voltage shift & offset unit 6 performs voltage adjustment for correcting the control voltage characteristic of the voltage controlled oscillator 1 as in the conventional example. Also, the frequency divider 4 shows a case where the output frequency of the voltage controlled oscillator 1 is frequency-divided to 1/8 as in the conventional example.

The monitoring circuit outputs the * Q terminal output signal (inverted output signal) of the second flip-flop F2 of the phase comparator 2.
Is input to the data terminal D of the fourth flip-flop F4, the reference signal having the inverted input frequency * Fin is input to the clock terminal C of the third flip-flop F3, and this reference signal is divided by two to obtain the fourth signal. Input to the clock terminal C of the flip-flop F4,
The terminal output signal is input to the peak detector 7. When the phase-locked loop circuit is in a state of synchronization establishment, the Q terminal output signal of the fourth flip-flop F4 becomes low level “L”.

For example, the peak detecting section 7 outputs 0 V and -5.
It comprises a capacitor C2 and a resistor R3 connected in series between 2V and the Q terminal of the fourth flip-flop F4 at the connection point. Therefore, in a normal state, the peak detection output signal is at the low level “L”. When the output signal of the Q terminal of the fourth flip-flop F4 is inverted to a high level (“H”), the capacitor C is output according to the CR time constant.
The potential at the connection point between the resistor 2 and the resistor R3 rises and is output as a high-level “H” alarm signal ALM directly or through a gate circuit or the like (not shown).

FIG. 2 is an explanatory diagram of the first embodiment of the present invention in a normal state, where Fin is a signal of an input frequency and Fout.
Is an output frequency signal, F1Q and F1 * Q are Q terminal output signals and * Q terminal output signals of the first flip-flop F1, F2Q is a Q terminal output signal of the second flip-flop F2, and PD is a phase comparison output signal , F2 * Q is the * Q terminal output signal of the second flip-flop F2, * Fin is the signal of the inverted input frequency, F3Q and F4Q are the Q terminal output signals of the third and fourth flip-flops F3 and F4, and ALM is Indicates an alarm signal.

Assuming that phase synchronization is established when the signal phase between the input frequency Fin and the output frequency Fout is in the state shown in the figure, the phase comparison output signal PD and the inverted phase comparison output signal * from the phase comparator 2 PD is duty 5
The signal becomes 0%, and the control voltage Vo via the low-pass filter 3 becomes V1 as in the normal state in the above-described conventional example, so that Fin = Fout and the phase state shown can be maintained.

The * Q terminal output signal F2 * Q of the second flip-flop F2 is an inverted version of the Q terminal output signal F2Q, and the Q terminal output signal F3Q of the third flip-flop F3 is an inverted input. This is a signal obtained by dividing the signal of frequency * Fin by two. When the signal F3Q rises, the second
The * Q terminal output signal F2 * Q of the flip-flop F2 is at a low level “L”, so that the Q terminal output signal F4Q of the fourth flip-flop F4 is at a low level “L”. The low level is fixed at "L", indicating a normal state.

FIG. 3 is an explanatory diagram of the first embodiment of the present invention at the time of loss of synchronization. The same reference numerals as those in FIG. 2 denote the same signals. Input frequency Fin <output frequency Fo due to loss of synchronization
In the state of “ut”, the phase comparison output signal PD is no longer 50% different from the normal state of FIG. 2, and the Q terminal output signal F3 of the third flip-flop F3 is output.
At the first rising of Q, the second flip-flop F
2, the * Q terminal output signal F2 * Q is at a low level “L”, but at the second rising edge, it is at a high level.
The Q terminal output signal F4Q of the fourth flip-flop F4 is at a high level "H", the potential is increased according to the time constant of the capacitor C2 and the resistor R3, and the high level "H".
Is issued as an alarm signal ALM indicating the loss of synchronization.

In this case, even if Fin <Fout, the voltage-controlled oscillator 1 determines that Fin = F in accordance with the control voltage.
When controlled to be out, the second flip-flop F3 at the rising edge of the Q terminal output signal F3Q has the second
Since the * Q terminal output signal F2 * Q of the flip-flop F2 becomes low level "L", the alarm signal ALM is not output.

Therefore, when the output frequency is fixed due to the deterioration of the voltage controlled oscillator 1 or the like and the state becomes out of synchronization, * Q of the second flip-flop F2 of the phase comparator 2
If the level of the terminal output signal is
Since the signal becomes high level "H" at the time of rising of the divided signal, it can be detected by the fourth flip-flop F4 to output the alarm signal ALM.

FIG. 4 is an explanatory view of a second embodiment of the present invention. In FIG. 4, the same reference numerals as those in FIG. 1 denote the same parts, 17 is a peak detector, G2 is an AND circuit, C3 is a capacitor, R4
Is resistance. First to fourth flip-flops F1 to F
Numeral 4 is constituted by, for example, an ECL (emitter-coupled logic) circuit capable of high-speed operation.

The peak detecting section 17 determines the connection point between the capacitor C2 and the resistor R3 by the Q of the fourth flip-flop F4.
And the connection point between the capacitor C3 and the resistor R4 is connected to the * Q of the fourth flip-flop F4.
The output signal of the fourth flip-flop F4 is connected to the terminal and the AND circuit G2 to maintain the high level “H” of the output signal of the fourth flip-flop F4. When the level changes to “H”, a high-level “H” signal is output at a relatively high speed,
Conversely, when the signal changes from the high level "H" to the low level "L", the signal maintains the high level "H" but outputs a signal which decreases to the low level "L" according to the time constant.

FIG. 5 is a diagram for explaining the case where an alarm signal is erroneously issued. In FIG. 1, the output signal of the Q terminal of the third flip-flop F3 is inverted according to the signal of the inverted input frequency * Fin. When the inversion timing is different from the case shown in FIG. 7, the second flip-flop F3 is turned on at the rising point of the Q terminal output signal F3Q of the third flip-flop F3.
2 * Q terminal output signal F2 * Q is always high level “H”
Therefore, the Q terminal output signal F4Q of the fourth flip-flop F4 becomes the high level “H”, and the high level “H” alarm signal ALM is output. That is, there is no problem when the timing of dividing the inverted input frequency * Fin by two is shown in FIG. 2 or FIG. 3, but in the case shown in FIG. 5, the alarm signal ALM is erroneously issued.

Therefore, in the second embodiment of the present invention shown in FIG. 4, the peak detecting section 17 detects a peak between the Q terminal output signal and the * Q terminal output signal of the fourth flip-flop F4. In normal operation, only one of the output terminals is at the high level “H” and the other output terminal is at the low level “L”. Therefore, the alarm signal ALM output from the AND circuit G2 is always at the low level. L ”.

When the fourth flip-flop F4 inverts due to loss of synchronization or the like, the peak detector 17
From the high level "H" is maintained as it is, and the terminal which has been inverted to the high level "H" at the low level "L" until now becomes the high level "H" at a relatively high speed. Since the peak detection output signals of the AND circuit G2 and the other are both at the high level "H", the output signal of the AND circuit G2 is at the high level "H" and the alarm signal ALM is issued. When the output frequency Fout becomes fixed due to deterioration of the voltage controlled oscillator 1 or the like, the flip-flop F4 performs an inverting operation at a period according to the frequency difference from the input frequency Fin, and the peak detection unit 17 outputs the AND circuit G2. , A high level “H” signal is continuously input, and an alarm signal ALM is issued.

FIG. 6 is an explanatory diagram of the second embodiment of the present invention in a normal state. The same reference numerals as in FIG. 5 denote the same signals.
F4 * Q is the * Q terminal output signal of the fourth flip-flop F4, and shows the same case as the signal shown in FIG. 5 except for the alarm signal ALM. In this embodiment,
Even if the Q terminal output signal F4Q of the fourth flip-flop F4 is at the high level “H”, the * Q terminal output signal F4 *
Since Q is at the low level “L”, the output signal of the AND circuit G2 is at the low level “L”.

When the initial state of the third flip-flop F3 is as shown in FIG. 2, the Q terminal output signal F4Q of the fourth flip-flop F4 is low level "L" and the * Q terminal output signal F4 * Q is high level. Since the signal becomes "H", the output signal of the AND circuit G2 becomes low level "L", and the erroneous generation of the alarm signal ALM does not occur regardless of the initial state of the third flip-flop F3.

FIG. 7 is an explanatory view of the second embodiment of the present invention at the time of out-of-synchronization. The same reference numerals as those in FIG. When the * Q terminal output signal F2 * Q of the flip-flop F2 is at the high level “H”, the Q terminal output signal F3Q of the third flip-flop F3 rises, and the Q terminal output signal F4Q of the fourth flip-flop F4 becomes Invert from low level “L” to high level “H”. The * Q terminal output signal F4 * Q is inverted from high level "H" to low level "L".

At this time, as described above, the peak detecting section 17 changes the peak detection signal from the low level "L" to the high level "H" at a relatively high speed and holds the high level "H". High level "H"
Becomes a peak detection signal which changes at a relatively low speed with respect to the change from "L" to "L". Therefore, the peak detector 1
7 are both high level "H",
An alarm signal ALM will be issued. When the output frequency Fout is in a fixed state due to deterioration of the voltage controlled oscillator 1 or the like, the fourth flip-flop F4 operates at the input frequency Fout.
Since the output signal is inverted at a period corresponding to the frequency difference from the output signal in, both output signals of the peak detection unit 17 maintain the high level “H”, whereby the alarm signal ALM is continuously output. .

FIG. 8 is an explanatory view of a third embodiment of the present invention. The same reference numerals as those in FIGS. 1 and 4 denote the same parts, and FIG.
7 is a second peak detector, C4 and C5 are capacitors, R
5, R6 are resistors, G3 is an OR circuit, G4 is a complementary output AND circuit, and G5 is a NAND circuit. The second peak detecting section 27 has a configuration to hold the high level “H” for at least one cycle of the signal of the output frequency Fout in the normal state.

When the voltage controlled oscillator 1 is operating, the complementary output signal of the AND circuit G3 is alternately inverted in accordance with the output frequency Fout, and the peak detector 27 holds the high level "H". The output signal of the NAND circuit G5 becomes low level "L". Voltage controlled oscillator 1
Is stopped and the high level is fixed at "H" or the low level is fixed at "L", one of the complementary output signals of the AND circuit G4 is fixed at the high level "H" and the other is at the low level "L". "Because it is fixed, the second peak detector 27
Changes to a level corresponding to the output signal of the AND circuit G4, whereby the output signal of the NAND circuit G5 becomes high level "H". Therefore, the alarm signal ALM is issued via the OR circuit G3.

FIG. 9 is an explanatory diagram when the operation of the voltage controlled oscillator is stopped, and shows the operation when the second peak detector 27 is not provided. The same reference numerals as those in FIGS. 6 and 7 denote the same signals. Show. When the operation of the voltage controlled oscillator 1 stops at the timing indicated as VCO disconnection and is fixed at the high level, for example, the Q terminal output signal F1Q of the first flip-flop F1 is at the low level “L” and the * Q terminal Output signal F1
When * Q is fixed to the high level “H”, the * Q terminal output signal F2 * Q of the second flip-flop F2 is fixed to the low level “L”. Therefore, the Q terminal output signal F4Q of the fourth flip-flop F4 is low level “L”, *
Since the Q terminal output signal F4 * Q keeps the high level “H”, the alarm signal ALM keeps the low level “L”.

Therefore, in the third embodiment of the present invention, the out-of-synchronization state is monitored by the first peak detecting section 17, and the operation of the voltage controlled oscillator 1 is controlled by the second peak detecting section 27. It is configured to monitor whether or not it has stopped.

FIG. 10 is an explanatory diagram of the third embodiment of the present invention when operation is stopped. The same reference numerals as those in FIG. 9 denote the same signals, and G4Q and G4 * Q denote complementary output signals of the AND circuit G4. G5 * Q indicates an output signal of the NAND circuit G5.

As in the case shown in FIG. 9, when the voltage-controlled oscillator 1 stops operating as shown as VCO cut-off and the signal of the output frequency Fout is fixed at the high level "H",
Since the Q terminal output signal F4Q of the fourth flip-flop F4 maintains the low level "L" and the * Q terminal output signal F4 * Q maintains the high level "H", the output signal of the AND circuit G2 is at the low level. L ”. And circuit G
The output signal G4Q of the second peak detector 27 corresponding to the complementary output signal of No. 4 maintains the high level “H”, but the output signal G4 * Q becomes the low level “L” according to the time constant.

Therefore, the output signal G5 * of the NAND circuit G5
Q becomes high level "H", and the alarm signal ALM is issued. In this case, the time constant of the second peak detector 27 in the case of G4 * Q in FIG. 10 is illustrated as being small, but is usually selected to be a time constant of about one to several cycles of the output frequency Fout. Then, the stop of the operation of the voltage controlled oscillator 1 can be quickly detected and the alarm signal ALM can be issued.

FIG. 11 is an explanatory view of the fourth embodiment of the present invention. The same reference numerals as in FIG. 1 denote the same parts, 31 is a comparator, 32 is a latch circuit, C6 is a capacitor, R7 and R
8 is a resistor. This capacitor C6 and resistors R7, R8
To form a differentiating circuit, and the fourth flip-flop F
The differential output signal Va when the Q terminal output signal of No. 4 is inverted is compared with the reference voltage Vref by the comparator 31, and the comparison output signal is latched by the latch circuit 32 to output the alarm signal AL.
M is issued.

FIG. 12 is a diagram for explaining the operation of the fourth embodiment of the present invention. The same reference numerals as those in FIG. 10 denote the same signals.
Va indicates a differential output signal. When the signal at the output frequency Fout is out of synchronization with the signal at the input frequency Fin, as described with reference to FIGS. 1 and 3, the * Q terminal output signal F2 * Q of the second flip-flop F2.
Is high level "H", the third flip-flop F
3, the Q terminal output signal F3Q rises, and the Q terminal output signal F4Q of the fourth flip-flop F4 becomes low level "L".
To a high level “H”.

The Q terminal output signal F4Q of the fourth flip-flop F4 is input to a differentiating circuit comprising resistors R7, R8 and a capacitor C6, and the differentiated output signal Va is compared with a reference voltage Vref in a comparator 31. Then, a high-level "H" output signal when the voltage exceeds the reference voltage Vref is latched in the latch circuit 32, and is used as an alarm signal ALM.

The present invention is not limited to the above embodiments, but can be variously added and changed. The configuration of the low-pass filter (LPF) 3, the first and second peak detection The configuration of the units 17 and 27 can be another circuit configuration. Further, the present invention can be applied to a phase locked loop circuit having a configuration in which the frequency divider 4 is omitted.

[0055]

As described above, the present invention provides the first,
Second flip-flops F1 and F2 and exclusive logic circuit G
1 of the phase comparator 2 including the first flip-flop F2
The inverted output signal (* Q terminal output signal) and the inverted reference signal (* Fin signal) are divided by 2 by the third flip-flop F3 and input to the fourth flip-flop F4,
In the phase synchronization established state, the output signal (Q terminal output signal) of the fourth flip-flop F4 is low level “L”.
However, when the state of the synchronization is lost, the high level “H” is set.
This is detected by the peak detection unit 7 and an alarm signal ALM is issued. Even if the control voltage becomes the same value as in the normal state in the out-of-synchronization state,
The fourth flip-flop F4 continues the inversion operation, and its output signal (Q terminal output signal) is peak-detected by the peak detection unit 7, and the alarm signal A of high level "H" is surely detected.
There is an advantage that LM can be issued.

The peaks of the non-inverted output signal (Q terminal output signal) and the inverted output signal (* Q terminal output signal) of the fourth flip-flop F4 are detected by the peak detector 17, and the respective peak detection signals are output. Become high level "H", that is, when the state is out of synchronization, the fourth flip-flop F4 continues the inverting operation, and the high level " H "alarm signal ALM can be issued. In this case, it is possible to prevent the alarm signal from being erroneously issued due to the initial state of the third flip-flop F3.

The output signal of the voltage controlled oscillator 1 or an output signal obtained by dividing the output signal is input to the second peak detecting section 27 as an inverted output signal and a non-inverted output signal by a complementary output AND circuit G4 or the like. Since the non-inverted output signal (Fout signal) and the inverted output signal are high-speed clock signals that alternately alternate between high level "H" and low level "L", respectively, in the normal state, the high level signal is output. H ”is detected and held. Therefore, the NAND circuit G5
A low-level “L” signal is output from such a gate circuit. However, when the output signal (Fout signal) is fixed at a high level or fixed at a low level, the second peak detection section 27 makes the peak detection output signals of one and the other different, and thereby the gate of the NAND circuit G5 or the like. A high-level "H" signal is output from the circuit. That is, the alarm signal ALM is issued. Thereby, there is an advantage that the operation stop state of the voltage controlled oscillator 1 can be reliably detected and the alarm signal ALM can be issued.

The output signal of the fourth flip-flop F4 is differentiated by a differentiating circuit to detect the inversion operation of the fourth flip-flop F4, and the detection signal is latched by a latch circuit to generate an alarm signal ALM. Since the fourth flip-flop F4 performs an inversion operation in an out-of-synchronization state, the out-of-synchronization is detected with a relatively simple configuration, and the alarm signal ALM is output.
There is an advantage that can be issued.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of the first embodiment of the present invention in a normal state.

FIG. 3 is an explanatory diagram when the synchronization is lost according to the first embodiment of this invention;

FIG. 4 is an explanatory diagram of a second embodiment of the present invention.

FIG. 5 is an explanatory diagram in the case of an erroneous issue of an alarm signal.

FIG. 6 is an explanatory diagram of a second embodiment of the present invention in a normal state.

FIG. 7 is an explanatory diagram at the time of loss of synchronization according to the second embodiment of this invention.

FIG. 8 is an explanatory diagram of a third embodiment of the present invention.

FIG. 9 is an explanatory diagram when the operation of the voltage controlled oscillator is stopped.

FIG. 10 is an explanatory diagram when operation is stopped in a third embodiment of the present invention.

FIG. 11 is an explanatory diagram of a fourth embodiment of the present invention.

FIG. 12 is an operation explanatory diagram of the fourth embodiment of the present invention.

FIG. 13 is an explanatory diagram of a main part of an optical transmission unit.

FIG. 14 is an explanatory diagram of a conventional example.

FIG. 15 is an explanatory diagram of a normal operation in a conventional example.

FIG. 16 is an explanatory diagram showing a relationship between a control voltage and an output frequency.

FIG. 17 is an explanatory diagram of the operation when the control voltage changes.

FIG. 18 is an explanatory diagram of the operation when the control voltage changes.

FIG. 19 is an explanatory diagram of control voltage monitoring of a conventional example.

FIG. 20 is an explanatory diagram of a problem in an out-of-synchronization state.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 voltage controlled oscillator (VCO) 2 phase comparator 3 low-pass filter (LPF) 4 frequency divider 5 differential amplifier 6 voltage shift & offset unit 7 peak detection unit F1 to F4 first to fourth flip-flops G1 exclusive logic Circuit ALM Alarm signal

Claims (4)

[Claims] 1. A first flip-flop for dividing an output signal of a voltage controlled oscillator or an output signal obtained by dividing the output signal by two, and an inverted output signal of the first flip-flop and a reference signal are input. A second flip-flop and the second flip-flop;
A phase comparator that compares an output signal of the first flip-flop with an output signal of the first flip-flop to output a phase comparison output signal, and controls the voltage-controlled oscillator by averaging the output signal of the phase comparator. In a monitoring circuit of a phase-locked loop circuit including a low-pass filter that converts a voltage, a third flip-flop that divides a frequency obtained by inverting the reference signal by two, an output signal of the third flip-flop and the second flip-flop. A fourth flip-flop for inputting an inverted output signal of the second flip-flop, and a peak detector for detecting a peak of the output signal of the fourth flip-flop and outputting an alarm signal. Monitoring circuit for the phase-locked loop circuit. 2. The method according to claim 1, wherein the peak detecting section detects a peak of each of a non-inverted output signal and an inverted output signal of the fourth flip-flop. 2. The monitoring circuit according to claim 1, further comprising a gate circuit for outputting an alarm signal. 3. A second peak detecting section which receives an output signal of the voltage controlled oscillator or an inverted output signal and a non-inverted output signal of an output signal obtained by dividing the output signal, and detects respective peaks, 3. A gate circuit for outputting an alarm signal when one of the second peak detectors has a different peak detection output signal from that of the second peak detector.
A monitoring circuit for the phase-locked loop circuit according to the above. 4. A first flip-flop for dividing an output signal of a voltage controlled oscillator or an output signal obtained by dividing the output signal by two, and an inverted output signal of the first flip-flop and a reference signal are input. A second flip-flop and the second flip-flop;
A phase comparator that compares an output signal of the first flip-flop with an output signal of the first flip-flop to output a phase comparison output signal, and controls the voltage-controlled oscillator by averaging the output signal of the phase comparator. In a monitoring circuit of a phase-locked loop circuit including a low-pass filter that converts a voltage, a third flip-flop that divides a frequency obtained by inverting the reference signal by two, an output signal of the third flip-flop and the second flip-flop. A fourth flip-flop for inputting an inverted output signal of the second flip-flop, a differentiating circuit for inputting the output signal of the fourth flip-flop, and a comparison for comparing a differential output signal of the differentiating circuit with a reference voltage And a latch circuit that latches an output signal of the comparator when the differential output signal exceeds the reference voltage and sets the latched output signal as an alarm signal. Monitoring circuit of that phase-locked loop circuit.