JPH10163599A - Printed wiring board - Google Patents
Printed wiring boardInfo
- Publication number
- JPH10163599A JPH10163599A JP8322421A JP32242196A JPH10163599A JP H10163599 A JPH10163599 A JP H10163599A JP 8322421 A JP8322421 A JP 8322421A JP 32242196 A JP32242196 A JP 32242196A JP H10163599 A JPH10163599 A JP H10163599A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- chip mounting
- printed wiring
- flip chip
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007747 plating Methods 0.000 claims abstract description 24
- 229910000679 solder Inorganic materials 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000000654 additive Substances 0.000 claims abstract description 7
- 230000000996 additive effect Effects 0.000 claims abstract description 7
- 239000004020 conductor Substances 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 27
- 229920005989 resin Polymers 0.000 abstract description 11
- 239000011347 resin Substances 0.000 abstract description 11
- 238000007789 sealing Methods 0.000 abstract description 11
- 230000035699 permeability Effects 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 238000007772 electroless plating Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000000945 filler Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
- H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
- H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、プリント配線板に
関し、特に狭ピッチのフリップチップ実装に用いられる
高密度配線基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board, and more particularly to a high-density wiring board used for flip-chip mounting at a narrow pitch.
【０００２】[0002]
【従来の技術】従来のフリップチップ実装構造を図５に
示す。プリント配線板に形成されたフリップチップ実装
パッド４にあらかじめはんだ６を供給し、半導体チップ
７をバンプ９を介してフェースダウンで搭載した後、半
導体チップ７の保護のために封止樹脂１０を浸透させ硬
化する。2. Description of the Related Art A conventional flip chip mounting structure is shown in FIG. Solder 6 is supplied in advance to flip chip mounting pads 4 formed on the printed wiring board, and semiconductor chip 7 is mounted face down via bumps 9, and then penetrates sealing resin 10 to protect semiconductor chip 7. And harden.
【０００３】プリント配線板の製造には、銅張積層板で
ある基材１上にエッチングにより配線パターン３を形成
し、その上からソルダーレジスト１２を印刷した後、フ
リップチップ実装パッド４部を開口させて製造するサブ
トラクティブ工法や、基材１上にパーマネントレジスト
２を形成後、メッキにより配線パターン３を析出させ、
その後同様な方法によりソルダーレジスト１２を形成す
るアディティブ工法を用いる。In manufacturing a printed wiring board, a wiring pattern 3 is formed by etching on a base material 1 which is a copper-clad laminate, a solder resist 12 is printed thereon, and a flip chip mounting pad 4 is opened. After the subtractive method of manufacturing and forming the permanent resist 2 on the base material 1, the wiring pattern 3 is deposited by plating,
Thereafter, an additive method for forming the solder resist 12 by the same method is used.
【０００４】半導体チップ７上に形成された電極の狭ピ
ッチ化に伴い、プリント配線板の配線密度もより高いも
のとなるが、サブトラクティブ工法では微細配線に限界
があり、これらに対応するためにアディティブ工法によ
るプリント基板が有望視されている。[0004] As the pitch of the electrodes formed on the semiconductor chip 7 becomes narrower, the wiring density of the printed wiring board becomes higher. However, in the subtractive method, there is a limit to fine wiring. Printed circuit boards by the additive method are promising.
【０００５】アディティブ工法の場合、パターン精度は
パーマネントレジスト２の形成精度のみで制御できるた
め、高密度配線が可能となる。しかしソルダーレジスト
１２は配線パターン３の保護およびソルダーダムとして
の機能を目的として配線パターン３上に形成されるた
め、その厚みの分だけ半導体チップ７の下面とソルダー
レジスト１２表面との間隙が狭くなる。そのため封止樹
脂１０の浸透性が悪くなったり、又は封止樹脂１０中に
含まれるフィラーにより、半導体チップ７の回路面に損
傷を与える等の問題が発生する。これを回避するため特
開平４−３６０５９７号公報（図６）に示されるプリン
ト基板のように、チップ部品１３の下面におけるソルダ
ーレジスト１２の厚みを部分的に部品実装パッド１４よ
りも薄くする構造が、発明されている。In the case of the additive method, the pattern accuracy can be controlled only by the formation accuracy of the permanent resist 2, so that high-density wiring is possible. However, since the solder resist 12 is formed on the wiring pattern 3 for the purpose of protecting the wiring pattern 3 and functioning as a solder dam, the gap between the lower surface of the semiconductor chip 7 and the surface of the solder resist 12 is reduced by the thickness. For this reason, problems such as poor permeability of the sealing resin 10 or damage to the circuit surface of the semiconductor chip 7 due to the filler contained in the sealing resin 10 occur. In order to avoid this, a structure in which the thickness of the solder resist 12 on the lower surface of the chip component 13 is partially smaller than that of the component mounting pad 14 as in a printed circuit board disclosed in Japanese Patent Application Laid-Open No. Hei 4-36097 (FIG. 6). Has been invented.
【０００６】なお、基材１上の部品実装パッド１４間に
は、ソルダーレジスト１２とともに、はんだ流れによる
ショート防止やチップ部品１３の位置表示のためにシン
ボルプリント１５が塗布されている。A symbol print 15 is applied between the component mounting pads 14 on the base material 1 together with the solder resist 12 in order to prevent a short circuit due to a solder flow and to indicate the position of the chip component 13.
【０００７】[0007]
【発明が解決しようとする課題】従来の技術の第１の問
題点は、ますます高密度化が進み実装パッドピッチが狭
くなるにつれ、上述した半導体チップとソルダーレジス
ト間の間隙が狭まることである。The first problem of the prior art is that the gap between the semiconductor chip and the solder resist becomes narrower as the packing density increases and the mounting pad pitch becomes narrower. .
【０００８】その理由は、狭ピッチ化に伴い半導体チッ
プ上の電極寸法が小さくなるため、電極上に形成するバ
ンプ寸法も縮小するためである。The reason for this is that, as the pitch becomes narrower, the dimensions of the electrodes on the semiconductor chip become smaller, and the dimensions of the bumps formed on the electrodes also become smaller.
【０００９】従来の技術の第２の問題点は、ソルダーレ
ジストの厚み制御が困難なことである。A second problem of the prior art is that it is difficult to control the thickness of the solder resist.
【００１０】その理由は、回路保護の信頼性を確保する
ために、配線パターン上に厚めに形成するからである。[0010] The reason for this is that in order to ensure the reliability of circuit protection, the wiring pattern is formed thicker.
【００１１】本発明の課題は、半導体チップとソルダー
レジストとの間隙寸法を十分に確保することにより、狭
ピッチフリップチップ実装においても封止樹脂の浸透性
を良好にし、半導体の回路面への損傷なく高い信頼性を
有したフリップチップ実装を実現するためのプリント配
線板を提供することである。An object of the present invention is to improve the permeability of a sealing resin even in a narrow-pitch flip-chip mounting by securing a sufficient gap dimension between a semiconductor chip and a solder resist, and to prevent damage to a circuit surface of a semiconductor. It is an object of the present invention to provide a printed wiring board for realizing flip-chip mounting with high reliability.
【００１２】[0012]
【課題を解決するための手段】本発明は、前記課題を解
決するため、次の手段を採用する。The present invention employs the following means to solve the above-mentioned problems.
【００１３】（１）絶縁層上の配線パターン部に実装用
パッドを設けているプリント配線板において、前記パタ
ーン部がアディティブ法により形成され、且つ前記実装
用パッドの導体厚が前記配線パターンの導体厚よりも厚
く形成されたプリント配線板。(1) In a printed wiring board in which mounting pads are provided on a wiring pattern portion on an insulating layer, the pattern portion is formed by an additive method, and the thickness of the mounting pad is equal to the conductor thickness of the wiring pattern. Printed wiring board formed thicker than thick.
【００１４】（２）前記実装用パッドのめっき厚が、パ
ーマネントレジスト厚と同等以上に形成されている前記
（１）記載のプリント配線板。(2) The printed wiring board according to (1), wherein a plating thickness of the mounting pad is equal to or greater than a permanent resist thickness.
【００１５】（３）前記実装用パッドのめっき厚が、パ
ーマネントレジスト厚より厚く形成され、且つ前記実装
用パッドがはんだ又は金属により皮膜されている前記
（１）記載のプリント配線板。(3) The printed wiring board according to (1), wherein a plating thickness of the mounting pad is formed to be thicker than a permanent resist thickness, and the mounting pad is coated with solder or metal.
【００１６】（４）フリップチップを実装された前記
（１）、（２）又は（３）記載のプリント配線板。(4) The printed wiring board according to (1), (2) or (3), wherein the flip chip is mounted.
【００１７】[0017]
【発明の実施の形態】以下に、本発明の実施の形態につ
いて、図１を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.
【００１８】図１（ａ）〜（ｃ）は、本発明の３つの実
施の形態である、プリント配線板の構造を示した断面図
である。FIGS. 1A to 1C are cross-sectional views showing the structure of a printed wiring board according to three embodiments of the present invention.
【００１９】（ａ）は、本発明の第１実施の形態を示し
た断面図である。FIG. 1A is a sectional view showing a first embodiment of the present invention.
【００２０】一般的にプリント配線板に用いられる基材
１上に、フォトリソグラフィ技術によりめっきレジスト
となるパーマネントレジスト２ａを形成し、無電解めっ
きにより配線パターン３を形成する。その後少なくとも
フリップチップ実装パッド４部を含む部品実装パッド部
を開口し、且つ配線パターン３を完全に覆うようにパー
マネントレジスト２ｂを形成し、その後無電解めっきを
施す。これによりフリップチップ実装パッド４の導体厚
とパーマネントレジスト２ｂは、ほぼ同じ厚みとなる。In general, a permanent resist 2a to be a plating resist is formed on a base material 1 used for a printed wiring board by photolithography, and a wiring pattern 3 is formed by electroless plating. Thereafter, a permanent resist 2b is formed so as to open at least the component mounting pad portion including the flip chip mounting pad 4 portion and completely cover the wiring pattern 3, and then apply electroless plating. As a result, the conductor thickness of the flip chip mounting pad 4 and the permanent resist 2b become substantially the same.
【００２１】（ｂ）は、本発明の第２実施の形態を示す
断面図である。本実施形態は、前述（ａ）の構造と比較
し、フリップチップ実装パッド４の導体厚をパーマネン
トレジスト２ｂ厚よりも厚く形成したものである。
（ａ）と同様に基材１上にパーマネントレジスト２ａを
形成し、無電解めっきにより配線パターン３を形成した
後、さらにパーマネントレジスト２ｂを形成する。その
後パーマネントレジスト２ｂを上回る厚さに無電解めっ
きを施す。FIG. 2B is a sectional view showing a second embodiment of the present invention. In the present embodiment, the conductor thickness of the flip chip mounting pad 4 is formed to be larger than the thickness of the permanent resist 2b as compared with the above-described structure (a).
As in (a), a permanent resist 2a is formed on a substrate 1, a wiring pattern 3 is formed by electroless plating, and then a permanent resist 2b is formed. Thereafter, electroless plating is performed to a thickness exceeding the thickness of the permanent resist 2b.
【００２２】（ｃ）は、本発明の第３実施の形態を示し
た断面図である。本実施形態は、前述（ｂ）により形成
されたフリップチップ実装パッド４上に、フリップチッ
プ実装におけるバンプとしての機能を付与するために、
はんだ又は金属による皮膜５を形成した構造を示す。FIG. 3C is a sectional view showing a third embodiment of the present invention. In the present embodiment, in order to provide a function as a bump in flip-chip mounting on the flip-chip mounting pad 4 formed in (b) above,
This shows a structure in which a coating 5 made of solder or metal is formed.
【００２３】[0023]
【実施例】次に本発明の第１実施の形態の実施例につい
て図２を参照して説明する。Next, an example of the first embodiment of the present invention will be described with reference to FIG.
【００２４】半導体チップ７上に設けられたパッドのピ
ッチが８０〜１００μｍのＡｌ電極８上に、ボールバン
プ技術でバンプ９を形成する。この場合、バンプ９の高
さは、３５〜４５μｍ程度になる。A bump 9 is formed on the Al electrode 8 having a pad pitch of 80 to 100 μm provided on the semiconductor chip 7 by a ball bump technique. In this case, the height of the bump 9 is about 35 to 45 μm.
【００２５】また、基材１としてガラス布基材エポキシ
樹脂板の上にフォトリソグラフィ技術によりパーマネン
トレジスト２ａを形成し、露光、現像を施した後に無電
解銅めっき処理により配線パターン３を形成する。その
後フリップチップ実装パッド４を除く配線パターン３部
分の全てに再度パーマネントレジスト２ｂを形成し、再
び無電解銅めっき処理を施す。無電解銅めっき厚は、め
っき厚公差を考慮し、通常パーマネントレジストよりも
約５μｍ程度低くなるよう設計するが、めっき厚精度と
して±３μｍ程度のばらつきが発生する。その後プリン
ト配線板上のフリップチップ実装パッド４に所定量のは
んだ６をめっき処理で供給する。Further, a permanent resist 2a is formed on a glass cloth base epoxy resin plate as a base material 1 by a photolithography technique, and after exposure and development, a wiring pattern 3 is formed by electroless copper plating. Thereafter, a permanent resist 2b is formed again on all of the wiring pattern 3 except for the flip chip mounting pads 4, and the electroless copper plating process is performed again. The thickness of the electroless copper plating is usually designed to be about 5 μm lower than the permanent resist in consideration of the plating thickness tolerance, but the plating thickness accuracy varies about ± 3 μm. Thereafter, a predetermined amount of solder 6 is supplied to the flip chip mounting pads 4 on the printed wiring board by plating.
【００２６】次に前述した半導体チップ７をフェースダ
ウンでプリント配線板上のフリップチップ実装パッド４
と位置合わせをし、所定の加熱および加圧を施し接合を
行う。Next, the above-mentioned semiconductor chip 7 is mounted face-down on the flip-chip mounting pad 4 on the printed wiring board.
And heat and pressure are applied to perform bonding.
【００２７】その後、フィラー入り封止樹脂１０を半導
体チップ７とプリント配線板の間隙部に浸透させ硬化す
る。このとき、半導体チップ７とプリント配線板の間隙
が１５μｍ以下になると、封止樹脂１０の充填性が著し
く悪くなり、半導体チップ７の中央部にボイドが発生し
たり、また封止樹脂１０の充填時間が長くなる。またフ
ィラーによる半導体チップ７上の回路を損傷したりもす
る。しかし、本実施例によれば、前記ギャップ寸法は前
記バンプ９の高さにのみ支配され、その寸法はおおよそ
２７〜４３μｍとなる。Thereafter, the sealing resin 10 containing the filler penetrates into the gap between the semiconductor chip 7 and the printed wiring board and is cured. At this time, if the gap between the semiconductor chip 7 and the printed wiring board is 15 μm or less, the filling property of the sealing resin 10 is significantly deteriorated, and voids are generated at the center of the semiconductor chip 7 and the filling of the sealing resin 10 The time gets longer. Also, the circuit on the semiconductor chip 7 may be damaged by the filler. However, according to the present embodiment, the gap dimension is controlled only by the height of the bump 9, and the dimension is approximately 27 to 43 μm.
【００２８】次に第２実施の形態の実施例について、図
３を参照して説明する。Next, an example of the second embodiment will be described with reference to FIG.
【００２９】第１実施の形態の実施例と同様な方法によ
り、基材１に配線パターン３を形成するためパーマネン
トレジスト２ａを形成した後、無電解銅めっき処理をす
る。その後フリップチップ実装パッド４を除く配線パタ
ーン３部分全てに再度パーマネントレジスト２ｂを形成
し、再び無電解銅めっき処理を施し、フリップチップ実
装パッド４を形成する。さらにフリップチップ実装パッ
ド４をパーマネントレジスト２ｂから突出させるため、
めっきレジストを約１０μｍの厚さで形成し、無電解銅
めっき処理をする。その後前述しためっきレジストを除
去した後、フリップチップ実装パッド４に所定量のはん
だ６をめっき処理で供給する。In the same manner as in the first embodiment, after forming a permanent resist 2a for forming a wiring pattern 3 on a substrate 1, an electroless copper plating process is performed. After that, the permanent resist 2b is formed again on all of the wiring pattern 3 except the flip chip mounting pad 4, and the electroless copper plating process is performed again to form the flip chip mounting pad 4. Further, in order to make the flip chip mounting pads 4 protrude from the permanent resist 2b,
A plating resist is formed with a thickness of about 10 μm, and an electroless copper plating process is performed. Thereafter, after removing the plating resist described above, a predetermined amount of solder 6 is supplied to the flip chip mounting pad 4 by plating.
【００３０】その後第１実施の形態の実施例と同様な方
法により、バンプ９付き半導体チップ７をフェースダウ
ンでフリップチップ実装パッド４に接合した後、封止樹
脂１０を半導体チップ７とプリント配線板の間隙部に浸
透させ硬化する。Thereafter, the semiconductor chip 7 with the bumps 9 is bonded face-down to the flip-chip mounting pads 4 in the same manner as in the example of the first embodiment, and then the sealing resin 10 is connected to the semiconductor chip 7 and the printed wiring board. And hardens.
【００３１】この構造の場合、第１実施の形態の実施例
と比較し、半導体チップ７とプリント配線板との間隙寸
法が３７〜４３μｍとなり、さらに拡大させることがで
きる。In the case of this structure, the gap dimension between the semiconductor chip 7 and the printed wiring board is 37 to 43 μm as compared with the example of the first embodiment, and can be further enlarged.
【００３２】次に第３実施の形態の実施例について、図
４を参照して説明する。Next, an example of the third embodiment will be described with reference to FIG.
【００３３】第２実施の形態の実施例と同様な方法にて
フリップチップ実装パッド４がパーマネントレジスト２
ｂから突出した構造を形成する。ただし、ここではフリ
ップチップ実装パッド４は、フリップチップ実装時に半
導体チップ７上のＡｌ電極８とのコンタクト性を重視す
るため、２０〜３０μｍ角のパッド寸法にする。無電解
銅めっきによりフリップチップ実装パッド４を形成した
後、無電解金めっき処理を厚さ約５μｍ施し、フリップ
チップ実装パッド４上に金めっき皮膜１１を形成する。In the same manner as in the embodiment of the second embodiment, the flip-chip mounting pad 4 is
b to form a structure projecting therefrom. However, here, the flip chip mounting pad 4 has a pad size of 20 to 30 μm square in order to attach importance to contact with the Al electrode 8 on the semiconductor chip 7 during flip chip mounting. After the flip chip mounting pad 4 is formed by electroless copper plating, an electroless gold plating process is performed to a thickness of about 5 μm to form a gold plating film 11 on the flip chip mounting pad 4.
【００３４】その後バンプを形成していない半導体チッ
プ７をフェースダウンで位置合わせし、所定の圧力およ
び加熱により半導体チップ７上のＡｌ電極８と、金めっ
き皮膜１１を形成したフリップチップ実装パッド４とを
接合する。After that, the semiconductor chip 7 on which no bump is formed is positioned face down, and the Al electrode 8 on the semiconductor chip 7 and the flip chip mounting pad 4 on which the gold plating film 11 is formed by a predetermined pressure and heating. To join.
【００３５】[0035]
【発明の効果】本発明によれば、アディティブ工法によ
り配線パターンを形成した高密度フリップチップ実装に
おいて、フリップチップ実装パッドの厚みを配線パター
ンの厚みより厚くし、且つパーマネントレジストと同等
又はそれ以上の厚みにすることにより、プリント配線板
と半導体チップの間隙寸法を十分確保することができ、
封止樹脂の充填性が良好で半導体チップの回路損傷がな
い高い信頼性を有した接合が可能となる。According to the present invention, in a high-density flip-chip mounting in which a wiring pattern is formed by the additive method, the thickness of the flip-chip mounting pad is made larger than the thickness of the wiring pattern and is equal to or greater than that of the permanent resist. By setting the thickness, the gap size between the printed wiring board and the semiconductor chip can be sufficiently secured,
A highly reliable bonding with good filling of the sealing resin and no damage to the circuit of the semiconductor chip becomes possible.
【図１】本発明の３つの実施の形態である、プリント配
線板の断面図であり、（ａ）は第１実施の形態、（ｂ）
は第２実施の形態、（ｃ）は第３実施の形態を、それぞ
れ示す。FIGS. 1A and 1B are cross-sectional views of a printed wiring board according to three embodiments of the present invention, wherein FIG. 1A is a first embodiment, and FIG.
Shows a second embodiment, and (c) shows a third embodiment.
【図２】本発明の第１実施の形態の実施例を示し、
（ａ）は半導体チップの平面図、（ｂ）はプリント配線
板の断面図、（ｃ）はフリップチップ実装構造の断面図
である。FIG. 2 shows an example of the first embodiment of the present invention,
(A) is a plan view of a semiconductor chip, (b) is a cross-sectional view of a printed wiring board, and (c) is a cross-sectional view of a flip chip mounting structure.
【図３】本発明の第２実施の形態の実施例を示すフリッ
プチップ実装構造の断面図である。FIG. 3 is a sectional view of a flip chip mounting structure showing an example of the second embodiment of the present invention.
【図４】本発明の第３実施の形態の実施例を示すフリッ
プチップ実装構造の断面図である。FIG. 4 is a cross-sectional view of a flip-chip mounting structure showing an example of the third embodiment of the present invention.
【図５】従来のフリップチップ実装構造の断面図であ
る。FIG. 5 is a sectional view of a conventional flip chip mounting structure.
【図６】従来のプリント配線板の断面図である。FIG. 6 is a sectional view of a conventional printed wiring board.
１ 基材 ２，２ａ，２ｂ パーマネントレジスト ３ 配線パターン ４ フリップチップ実装パッド ５ 皮膜 ６ はんだ ７ 半導体チップ ８ Ａｌ電極 ９ バンプ １０ 封止樹脂 １１ 金めっき皮膜 １２ ソルダーレジスト １３ チップ部品 １４ 部品実装パッド １５ シンボルプリント DESCRIPTION OF SYMBOLS 1 Base material 2, 2a, 2b Permanent resist 3 Wiring pattern 4 Flip chip mounting pad 5 Film 6 Solder 7 Semiconductor chip 8 Al electrode 9 Bump 10 Sealing resin 11 Gold plating film 12 Solder resist 13 Chip component 14 Component mounting pad 15 Symbol Print
Claims (4)
ドを設けているプリント配線板において、前記パターン
部がアディティブ法により形成され、且つ前記実装用パ
ッドの導体厚が前記配線パターンの導体厚よりも厚く形
成されたプリント配線板。In a printed wiring board provided with mounting pads on a wiring pattern portion on an insulating layer, the pattern portion is formed by an additive method, and the conductor thickness of the mounting pad is equal to the conductor thickness of the wiring pattern. Printed wiring board formed thicker.
ネントレジスト厚と同等以上に形成されている請求項１
記載のプリント配線板。2. The mounting pad according to claim 1, wherein a plating thickness of the mounting pad is equal to or greater than a permanent resist thickness.
The printed wiring board as described.
ネントレジスト厚より厚く形成され、且つ前記実装用パ
ッドがはんだ又は金属により皮膜されている請求項１記
載のプリント配線板。3. The printed wiring board according to claim 1, wherein a plating thickness of the mounting pad is formed larger than a permanent resist thickness, and the mounting pad is coated with solder or metal.
２又は３記載のプリント配線板。4. The method according to claim 1, wherein the flip chip is mounted.
4. The printed wiring board according to 2 or 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8322421A JPH10163599A (en) | 1996-12-03 | 1996-12-03 | Printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8322421A JPH10163599A (en) | 1996-12-03 | 1996-12-03 | Printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10163599A true JPH10163599A (en) | 1998-06-19 |
Family
ID=18143483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8322421A Pending JPH10163599A (en) | 1996-12-03 | 1996-12-03 | Printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10163599A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000260792A (en) * | 1999-03-10 | 2000-09-22 | Toshiba Corp | Semiconductor device |
| JP2011134818A (en) * | 2009-12-24 | 2011-07-07 | Shinko Electric Ind Co Ltd | Semiconductor element built-in substrate |
-
1996
- 1996-12-03 JP JP8322421A patent/JPH10163599A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000260792A (en) * | 1999-03-10 | 2000-09-22 | Toshiba Corp | Semiconductor device |
| JP2011134818A (en) * | 2009-12-24 | 2011-07-07 | Shinko Electric Ind Co Ltd | Semiconductor element built-in substrate |
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