JPH10163335A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce power consumption by reducing parasitic current of a push-pull driver IC. An active region to become the n-type island 4, 5 n ⁺ buried regions 3a, 3b is formed, the n ⁺ buried region 3
n ⁺ drain wall region 6 to reach a, 3b,
7 is formed. On the n-type island 4, a lateral p-channel MOSFET serving as the high-side transistor N2 is formed.
On the island 5, a vertical n-channel MOSFET serving as the low-side transistor N1 is formed. On the high side transistor N2 side, the power supply terminal VDH is connected to the source electrode 13 and the metal electrode 15, and the drain electrode 14 is connected to the output terminal DO. Low-side transistor N
On the 1 side, the drain electrode 21 is connected to the output terminal DO, and the source electrode 20 is connected to the metal electrode 22 formed on the p-type isolation region 3a and the ground terminal GND.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit (hereinafter abbreviated as IC) having a push-pull type output circuit for driving a flat panel display such as a plasma display panel, an electroluminescence display panel, and a fluorescent display panel. ).

[0002]

2. Description of the Related Art FIG. 5 shows an example of an IC for driving a plasma display panel and shows an output circuit per dot. The output terminal DO of the data driver IC 51 and the output terminal DO of the scan driver IC 52 which constitute a push-pull type driver IC are connected to both ends of the discharge tube 53 which is a display cell, respectively. The output circuit of each of the driver ICs 51 and 52 is n
It is a push-pull type in which channel MOSFETs are connected in series, and an output terminal DO is taken out between two series-connected MOSFETs (N1 and N2, N3 and N4). The elements connected to the high potential terminals (power supply terminal: VDH) of the power supplies 54 and 55 are high-side elements (here, N2 and D2 and N4 and D4), and the power supply 5
The elements connected to the low potential terminals (ground terminals: GND) 4 and 55 are called low-side elements (here, N1 and D1 and N3 and D3). Data driver IC5
In 1, a high-side diode D2 and a low-side diode D1 are connected in parallel to the high-side transistor N2 and the low-side transistor N1, respectively. A high-side diode D4 and a low-side diode D3 are connected in parallel to the high-side transistor N4 and the low-side transistor N3 of the scan driver IC 52, respectively.

The high-side transistors N2 and N4 and the low-side transistors N1 and N3 are turned on / off by signals from the control circuits 56 and 57, thereby providing an output terminal D.
A method of controlling the potential of O to charge and discharge the display cell 53 to emit light is general. FIG. 6 shows the data driver IC 5
FIG. 3 is a cross-sectional view of a main part when the high-side transistor N2 and the low-side transistor N1 of the output unit 1 are formed in a CMOS structure. In the following description, layers, regions and the like bearing n and p mean layers and regions using electrons and holes as majority carriers, respectively.

Usually, a CMOS structure (Complimen) is used.
n-channel MOSFET, p-channel MOS
A method of forming an FET and an n-channel MOSFET) is to form an n-well region 102 in a surface layer of a p-type semiconductor substrate 101 and to form a p-type
⁺ Source region 103 and p ⁺ drain region 104 are formed, and n ⁺ region 10 is brought into contact with p ⁺ source region 103.
5 is formed, a gate electrode 107 is formed on the n well region 102 interposed between the p ⁺ source region 103 and the p ⁺ drain region 104 via the gate insulating film 106, and the p ⁺ source region 103 and the n ⁺ region Source electrode 108 on 105
Is formed, a drain electrode 109 is formed on p ⁺ drain region 104, and a p-channel high-side transistor N2 is formed. On the other hand, n ⁺ source region 110 and n ⁺ drain region 11
1 is formed, p ⁺ region 112 in contact with n ⁺ source region 110 is formed, via the n ⁺ source region 110 and n ⁺ drain region 111 and the gate insulating film 113 on the p-type semiconductor substrate 101 sandwiched between the A gate electrode 114 is formed, a source electrode 115 is formed on the n ⁺ source region 110 and the p ⁺ region 112, and a drain electrode 116 is formed on the p ⁺ drain region 111. Is formed. The source electrode 108 of the high-side transistor N2 is connected to the power supply VDH, and the drain electrode 109 of the high-side transistor N2 is
The drain electrode 116 of the low-side transistor N1 is connected to the output terminal DO, and the source electrode 115 of the low-side transistor N1 is connected to the ground terminal GND.

[0005]

As shown in FIG. 6, in this structure, a parallel diode D1 is formed between an output terminal DO and a ground terminal GND by a p-type semiconductor substrate 101 and an n ⁺ drain region 111. , A parallel diode D2 is also formed between the output terminal DO and the power supply terminal VDH by the n-well region 102 and the p ⁺ drain region 104. The ground terminal GND is connected to the high-side transistor N2 to which the output terminal DO is connected. In between, the p ⁺ drain region 10
4, the n-well region 102 and the p-type semiconductor substrate 101 form a parasitic pnp transistor T1.

FIG. 7 shows one of the circuits in FIG. 5, and shows an equivalent circuit in which a parasitic pnp transistor is connected to the high-side diode D2. The emitter and base of the parasitic pnp transistor T1 are connected in parallel with the high side diode D2 as shown by the dotted line. Data driver I shown in FIG.
Output terminals DO of the C51 and the scan driver IC 52 are connected to a discharge tube 53 and are electrically capacitively coupled. Therefore, the potential of the output terminal DO may be higher than the power supply terminal VDH depending on the charging / discharging timing of the discharge tube 53, in which case, as shown in FIG. A current Id flows to the power supply terminal VDH via the power supply terminal VDH.

As described above, in the data driver IC 51, when the potential of the output terminal DO becomes higher than the power supply terminal VDH, the current Id flows from the output terminal DO to the power supply terminal VDH via the high-side diode D2. A part of this current Id becomes the base current of the parasitic pnp transistor T1, and the collector current of the parasitic pnp transistor T1 becomes a large value obtained by multiplying this base current by the current amplification factor of the parasitic pnp transistor T1, and this collector current flows to the ground terminal side. It flows out as a parasitic current Il. Due to the parasitic current Il, power consumption increases and the data driver IC 51 generates heat. Of course, scan driver IC5
The same phenomenon occurs in the case of No. 2.

[0008] An object of the present invention is to solve the above-mentioned problems and reduce a parasitic current caused by a parasitic pnp transistor.
An object of the present invention is to provide a semiconductor integrated circuit which forms a push-pull output circuit with low power consumption.

[0009]

In order to achieve the above object, an integrated circuit including a push-pull type output circuit having a high side transistor, a low side transistor, and diodes respectively connected to the transistors in anti-parallel. In the circuit, both transistors are formed in an active region surrounded by an isolation region.

The high-side transistor is a horizontal p-type transistor.
Channel MOSFET, and the p-channel MOSFET
Preferably, an n-type region is selectively formed in the surface layer of the p-type drain region of T, and the p-type drain region and the n-type region are connected by a conductor. As a method for connecting the conductors, a drain electrode may be formed on the p-type drain region, a metal electrode may be formed on the n-type region, and the drain electrode and the metal electrode may be connected by a conductor.

As another connection method, an exposed portion of a pn junction where the p-type drain region and the n-type region are in contact with each other is formed as follows.
There is also a method of selectively short-circuiting the drain electrode formed on the p-type drain region. Further, there is a method in which the exposed portion of the pn junction where the p-type drain region and the n-type region are in contact with each other is short-circuited by a drain electrode formed on the p-type drain region.

By doing so, the current flowing into the base of the parasitic pnp transistor can be reduced, the collector current that is a parasitic current can be reduced, and the power consumption of the driver IC can be reduced.

[0013]

FIG. 1 is a sectional view of an essential part of a first embodiment of the present invention. In order to form n ⁺ buried regions 2a and 2b in p-type semiconductor substrate 1, n-type impurities are selectively diffused, and an n-type epitaxial layer is grown thereon. P-type isolation region 3 reaching p-type semiconductor substrate 1 from the surface
a, 3b are formed by diffusion, and p-type
N-type islands 4 and 5 serving as active regions surrounded by the p-type semiconductor substrate 1 and the p-type semiconductor substrate 1 are formed, and the above-mentioned n ⁺ buried regions 3a and 3b are formed therein. The n ⁺ buried regions 3a, to form the n ⁺ drain wall region 6 to reach the 3b. The n-type island 4 on the right side of FIG.
Form an SFET. The formation method is to form an n-well region 8 (the concentration of the n-well region 8 is slightly higher than the concentration of the n-type island 4) in the surface layer of the n-type island 4, A p ⁺ source region 9 is formed on the surface of the n-type island 4 interposed between the n well regions 8 and a p drain region 10
To form A gate electrode 12 is formed on a surface of n well region 8 and n type island 4 interposed between p ⁺ source region 9 and p drain region 10 via gate insulating film 11.
Source electrode 13 is formed on the surface of p ⁺ source region 9 and a part of the surface of n well region 8, and p drain region 10 is formed.
The drain electrode 14 is formed on the surface of the substrate. Metal electrode 15 is formed on the surface of n ⁺ drain wall region 6. Incidentally, the gate electrode 12 is usually formed of polysilicon.

On the other hand, the n-type island 5 on the left side of FIG.
Vertical n-channel MOSFE which becomes the transistor N1
T is formed. The formation method is as follows: the surface layer of the n-type island 5
A p-well region 16 is formed on the surface of the p-well region 16.
N in layer⁺A source region 17 is formed. n⁺Source area 1
7 and the surface of the n-type island 5
A gate electrode 19 is formed via a gate insulating film 18 and n
⁺The source is located on the source region 17 and part of the p-well region 16.
An electrode 20 is formed. n⁺The drain region is n ⁺Embedding
Only region layer 2b and n⁺Formed in the drain wall region 7
You. n⁺A drain electrode 2 is formed on the surface of the drain wall region.
1 is formed.

On the high-side transistor N2 side, the power supply terminal VDH is connected to the source electrode 13 and the metal electrode 15, and the drain electrode 14 is connected to the output terminal DO. On the low-side transistor N1 side, the drain electrode 21 and the output terminal DO are connected, and the source electrode 20 and p
The metal electrode 22 formed on the isolating region 3a is connected to the ground terminal GND.

The above structure has a higher size than the conventional structure.
P-type transistor and low-side transistor
N-type island surrounded by regions 3a and 3b and p-type semiconductor substrate 1
Parasitic pnp transformers to be formed in
The parasitic current flowing through the transistor is small, reducing power consumption.
Can be reduced. But to form a high-side transistor
In the n-type island 4, p⁺Emitter drain region 10
Region and n-type islands 4 and n⁺Base with embedded layer 2a
And a p-type semiconductor substrate 1 and a p-type isolation region 3b.
Parasitic pnp transistor as collector region still exists
And the potential of the output terminal DO is higher than the power supply terminal VDH.
Output terminal DO-drain electrode 14-emitter
Region (p drain region 10) -base region (n-type island 4)
And n⁺Buried regions 2a and n⁺Drain wall area
Zone 6)-The base current flows through the path of the power supply terminal VDH,
Collector region forming a junction with the source region (p-type semiconductor
A base current is applied to the body substrate 1 and the p-type isolation region 3a).
Flow amplification factor (h_FE) Multiplied by the collector current as the parasitic current
Flowing. This parasitic current is said to be lower than the conventional structure
Well, it is still large enough to be ignored. Here, the parasitic pn
n serving as a base region of a p-transistor⁺Embedding area 2
The impurity concentration of a is 1 × 10¹⁷~ 1 × 10¹⁸cm ^-3, N-type
The impurity concentration of the epitaxial layer (n-type island 4) is about 1 ×
10^Fifteencm^-3It is.

FIG. 2 is a sectional view of a main part of a second embodiment of the present invention. The difference from FIG. 1 is that
⁺ A n ⁺ region 23 is formed on the surface layer of the drain region 10,
The drain electrodes 24 are separated from each other on the surfaces of the regions 10 and 23.
And a metal electrode 25 are provided, and these electrodes 24 and 25 are connected by a conductive wire. By doing so, n is connected between the emitter and the base of the parasitic pnp transistor T1 as shown.
A pn transistor T2 is added, and the added np
The conduction of the n-transistor T2 reduces the base current flowing from the emitter region of the parasitic pnp transistor T1 to the base region, thereby reducing the parasitic current due to the parasitic pnp transistor T1. Thus, the power consumption of the semiconductor integrated circuit can be reduced. Note that n ⁺ region 2
When the pn junction with the p drain region 10 immediately below 5 is wide in the lateral direction, the same effect can be obtained even if the entire region where the pn junction is exposed is short-circuited by the drain electrode 26.

FIG. 3 is a sectional view of a main part of a third embodiment of the present invention. The difference from FIG. 2 is that the drain electrode 26 also serves as the metal electrode 25 of FIG. 2 and is selectively connected on the semiconductor surface, and a pn junction formed locally by the p drain region 10 and the n ⁺ region 23 is formed. It is a point that is short-circuited on the surface. In this case, the effect is the same as described above. FIG. 4 is a sectional view showing a main part of a fourth embodiment of the present invention. The difference from FIG.
Is that the n ⁺ region 23 is entirely covered.
In this case, the exposed portion of the pn junction formed by the p drain region 10 and the n ⁺ region 23 covers the entire surface of the drain electrode 2.
Short-circuited at 7. Therefore, the additional npn transistor T
The condition in which 1 works is when the pn junction with the p drain region 10 immediately below the n ⁺ region 25 becomes wider in the lateral direction, or when the thickness of the p drain region 10 immediately below the n ⁺ region 25 is thin. The same effect as described above can be obtained by operating the additional npn transistor T2.

As a fifth embodiment of the present invention, although not shown, the high-side transistor is a p-channel MOSFET.
Parasitic np when formed with n-channel MOSFET instead of T
An additional pnp transistor having a p-well region as a collector is formed between the emitter and the base of the n-transistor,
Again, the parasitic current can be reduced.

[0020]

According to the present invention, since the high-side transistor and the low-side transistor are formed in separate islands (active regions), the parasitic current is reduced even when the potential of the output terminal DO becomes higher than the power supply terminal VDH. Thus, the power consumption of the semiconductor integrated circuit can be reduced. Also,
When the high-side transistor is formed of a p-channel MOSFET, an n ⁺ region is provided in the p ⁺ drain region of the p-channel MOSFET and these regions are connected by a conductor, thereby further reducing the parasitic current and reducing the consumption current. The power can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a first embodiment of the present invention.

FIG. 2 is a sectional view of a main part of a second embodiment of the present invention.

FIG. 3 is a sectional view of a main part of a third embodiment of the present invention.

FIG. 4 is a sectional view of a main part of a third embodiment of the present invention.

FIG. 5 is an example of an IC for driving a plasma display panel, and an output circuit diagram per dot.

FIG. 6 is a sectional view of a main part of a conventional structure.

FIG. 7 shows a parasitic p in a high-side diode D2 in a conventional structure.
Equivalent circuit diagram with np transistor connected

[Explanation of symbols]

REFERENCE SIGNS LIST 1 p-type semiconductor substrate 2 an ⁺ embedded region 2 b n ⁺ embedded region 3 a p-type isolation region 3 b p-type isolation region 4 n-type island 5 n-type island 6 n ⁺ drain wall region 7 n ⁺ drain wall region 8 n-well Region 9 p ⁺ source region 10 p drain region 11 gate insulating film 12 gate electrode 13 source electrode 14 drain electrode 15 metal electrode 16 p well region 17 n ⁺ source region 18 gate insulating film 19 gate electrode 20 source electrode 21 drain electrode 22 metal Electrode 23 n ⁺ region 24 drain electrode 25 metal electrode 26 drain electrode 27 drain electrode 51 data driver IC 52 scan driver IC 53 discharge tube 54 power supply 55 power supply 56 control circuit 57 control circuit 101 p-type semiconductor substrate 102 n well region 103 p ⁺ Source area 104 ⁺ Drain region 105 n ⁺ region 106 a gate insulating film 107 gate electrode 108 source electrode 109 drain electrode 110 n ⁺ source regions 111 n ⁺ drain region 112 p ⁺ region 113 a gate insulating film 114 gate electrode 115 source electrode 116 drain electrode GND ground terminal DO output terminal VDH power supply terminal N1 low-side transistor N2 high-side transistor T1 parasitic pnp transistor T2 additional npn transistor N3 low-side transistor N4 high-side transistor D1 low-side diode D2 high-side diode D3 low-side diode D4 high-side diode Id current Il parasitic current

Claims (5)

[Claims] 1. An integrated circuit including a push-pull output circuit having a high-side transistor, a low-side transistor, and a diode connected in anti-parallel to each of the transistors, wherein the high-side transistor and the low-side transistor are connected to each other. A semiconductor integrated circuit formed in an active region surrounded by an isolation region. 2. The high-side transistor is a lateral p-channel MOSFET, and the p-channel MOSFET has a p-channel MOSFET.
Selectively forming an n-type region in a surface layer of the drain region;
2. The semiconductor integrated circuit according to claim 1, wherein the p-type drain region and the n-type region are connected by a conductor. 3. The drain electrode according to claim 2, wherein a drain electrode is formed on the p-type drain region, a metal electrode is formed on the n-type region, and the drain electrode and the metal electrode are connected by a conductor. Semiconductor integrated circuit. 4. A p-type drain region and an n-type region in contact with each other.
The exposed portion of the n-junction is selectively short-circuited by a drain electrode formed on the drain region.
A semiconductor integrated circuit as described in the above. 5. A p-type drain region in contact with an n-type region.
3. The exposed region of the n-junction is short-circuited in all regions by a drain electrode formed on the drain region.
A semiconductor integrated circuit as described in the above.