JPH10161589A - Driving method of flat display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driving method of flat display which eliminates visual, irregular brightness due to differences of luminous efficacy dependent on brightness level, makes the brightness differences constant over the whole brightness regions and enhances display quality. SOLUTION: A data discriminating section 1 and a subfield control section 4 are provided to discriminate which one of the three tripartite gradation groups includes the original picture image data based on the top two bits of the original picture image data and selects the combination of the subfields which correspond to the gradation-brightness characteristics matching the gradation group. Brightness differences between gradations are lowered in the low-brightness region and enhanced in the high-brightness region complementarily to human spectral luminous characteristics and accordingly uniform brightness density is visually recognized over all brightness regions and good display quality is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method of a flat panel display device such as a plasma display panel (PDP), which realizes a gray scale display by a lighting time length.

[0002]

2. Description of the Related Art A PDP in which a desired display image is formed by controlling light emission and non-light emission for each pixel using a plasma discharge has an advantage of being thin, and a liquid crystal display (LCD) is used. ) Is being actively developed as a flat panel display.

In a PDP, a row electrode and a column electrode cross each other on opposing surfaces of a pair of substrates, and a gas for discharging is sealed in a gap between the substrates. The discharge light emission is performed by applying a voltage to the discharge cell at the intersection of the column electrode and the row electrode specified in a matrix.I, these dot-like discharge light emission are visually recognized macroscopically, and images of characters, figures, etc. Is formed. In a PDP, the amount of light emitted by discharge cannot be linearly controlled by an applied voltage. For this reason, by controlling the lighting time in association with the luminance, multi-gradation is realized.

FIG. 5 shows the structure of a conventional PDP. R,
The G and B original image data are sent to a multi-tone processor (10).
Is performed, and is converted into data of a predetermined bit, for example, 4 bits. The converted original image data is temporarily stored in a frame memory (11).
Is stored in the PDP display unit (1).
It is sent to the data driver (18) of 5). On the other hand, the horizontal synchronization pulse S separated from the composite video signal
The YNC is sent to the sub-field timing control unit (13) to generate signal pulses for various timing controls such as columns and rows, sub-fields, fields, and frames. It is supplied to a memory (11), a data controller (12) and a driver controller (14). In the driver controller (14), under the control of the subfield timing control unit (13), the drive timing of the Y electrode driver (16), the X electrode driver (17) and the data driver (18) of the PDP display unit (15). Control.

The PDP display section (15) has a plurality of Y electrodes (19) and X electrodes (20) arranged in parallel with each other.
A plurality of data electrodes (21) are arranged crossing this. The Y electrode (19) and the X electrode (20) are formed on one substrate, and the data electrode (21) is formed on the other substrate. A dielectric layer is coated on the surface of the substrate on which the Y electrode (19) and the X electrode (20) are formed, and R, G, and B phosphors are provided on the substrate on which the data electrode (21) is formed. Have been. In addition, a discharge cell including a Y electrode (19), an X electrode (20), and a data electrode (21)
A discharge space is partitioned by an insulator layer formed on the substrate.

The Y electrode driver (16) supplies a scan pulse and a common pulse in the row direction, and the X electrode driver (17) supplies a common pulse. All the X electrodes (20) are commonly driven. The data driver (18) performs an address in the column direction. Such a device having three types of electrodes is called a three-electrode type. 3
In the electrode-type PDP, one field includes a plurality of subfields, and each subfield mainly includes an address period and a sustain discharge period. In the address period, first, one row, that is, one scan line composed of one set of the Y electrode (19) and the X electrode (20) is selected. That is, the Y electrode (1
A scan pulse is applied to 9), and a sufficiently large voltage is applied between the scan pulse and the X electrode (20). In this state, a signal voltage is applied to a predetermined data electrode (21) from the data driver (18), and a write discharge is performed in a discharge cell corresponding to one point designated in a matrix, and a dielectric layer is applied to each of the discharge cells. A pair of wall charges is formed on the sandwiched Y electrode (19) and X electrode (20). In the subsequent sustain discharge period, a sustain discharge pulse is simultaneously applied alternately to the Y electrode (16) and the X electrode (17), and a sufficiently large wall charge selectively generated in the address period switches its polarity. And discharge light emission is performed while maintaining the charge. This discharge is repeated reversibly, positive and negative,
Lights up to display sufficient brightness.

In the batch erasing and batch writing method, a signal voltage is simultaneously applied to all cells from the data driver (18) at the time of batch writing before the address period, and wall charges are generated in all cells. In the subsequent address period, an erase pulse is selectively applied from the data driver (18). The erase pulse is a pulse having a smaller wavelength or amplitude than the sustain discharge pulse, and the cell to which the erase pulse is supplied receives an erase voltage by applying a voltage having a polarity opposite to that of the wall charge generated at the time of writing. And the wall charges are erased. In the sustain discharge period, the sustain discharge pulse is alternately applied to the Y electrode (16) and the X electrode (17), and the sustain discharge is repeated a predetermined number of times, as described above.

In the case of performing gradation display in a PDP,
By changing the length of the sustain discharge period controlled by the number of sustain discharges of each discharge cell, the luminance of each pixel as a discharge cell is adjusted. That is, a plurality of subfields having a sustain discharge period corresponding to a predetermined luminance ratio are created by the subfield timing control unit (13), and each bit of the original image data is allocated to these subfields. A combination of subfields to be lit in the form is selected. In other words, the pixels are turned on only in the selected subfield, and for each pixel, the total length of the sustain discharge is controlled in a form corresponding to the gradation of the original image data. The multi-gradation display is realized by being visually recognized as a desired display luminance.

[0009]

Conventionally, a composite video signal for television broadcast or computer video output has been subjected to gamma correction in accordance with the display characteristics of a cathode ray tube, and is therefore transmitted to a device other than a CRT. The luminance correction is performed to match the voltage-luminance characteristic inherent to the display. Also in the configuration shown in FIG. 5, the original image data supplied to the multi-tone processor (10) is further subjected to gamma correction for PDP to a signal subjected to gamma correction at the time of image transmission or computer output. As a result, the voltage-luminance relationship curve is linearized. In this example, the display of 16 gradations is obtained by the 4-bit original image data, but the relation curve between the gradation and the display luminance is linear. That is, the luminance difference between the gray levels is equal at all levels. However, when actually observed by the naked eye, human visibility is high in a low luminance area and the luminance difference is clearly recognized. However, in a high luminance area, on the other hand, the visual sensitivity is low and the luminance difference is sharp. It is hard to be recognized. For this reason, in the visual recognition, the brightness varies over the entire brightness region, and the display quality is degraded.

[0010]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and has been made in order to solve the above-mentioned problem. In the driving method of the flat panel display device which performs gradation control of the total lighting time in one field period by controlling the lighting and non-lighting of each of the sub-fields, the lower four gradations, The lower gradation group, the middle gradation group, and the upper gradation group are divided into three gradation groups of middle 4 gradations and upper 8 gradations, and the original image data belongs to any of these gradation groups. A luminance having a predetermined relative ratio is obtained by employing any one of the first, second, and third selection methods respectively associated with the gradation group.
By selecting four subfields from the four subfields, allocating each bit of the 4-bit original image data to each of the selected subfields, and controlling lighting and non-lighting of each subfield, A method for driving a flat panel display device, wherein the luminance difference between the gradations belonging to the group is the smallest and the luminance difference between the gradations belonging to the higher gradation group is the largest.

As a result, the luminance difference between the gray scales compressed in the low luminance region where the human visual sensitivity is high expands and is visually recognized, and conversely, the luminance difference between the gray scales expanded in the high luminance region where the human visual sensitivity is low. Since the difference is visually perceived in a compressed manner, as a result, unevenness in luminance over the entire luminance region is eliminated.

[0012]

FIG. 1 shows a configuration of a PDP according to an embodiment of the present invention. The R, G, B original image data is received by a multi-tone processor (10), where:
An error diffusion process is performed, and the data is converted into data of a predetermined bit, for example, 4 bits. The converted original image data is temporarily stored in the frame memory (11), and the upper two bits are also supplied to the data discrimination unit (1) according to the present invention. The data discriminating unit (1) discriminates, from the upper two bits of the original image data, which region of the gradation group divided into the lower, middle, and upper three groups. The discrimination signal created by the data discrimination unit (1) is sent to the subfield timing control unit (4) according to the present invention. The subfield timing control unit (4) is provided with subfield data for realizing characteristics of gradation and display luminance associated with each of the three divided gradation groups. Based on the determination signal sent from (1), the gradation group including the original image data is determined, and the corresponding subfield data is sent to the frame memory (11), and the corresponding 4-bit data is transmitted. It is stored in a form associated with the original image data.

The data controller (12) reads each bit of the original image data stored in the frame memory (11) in a form associated with the subfield data obtained from the subfield timing control section (4). Pixel data is created and supplied to the data driver (18) of the PDP display (15). On the other hand, the horizontal and vertical synchronizing signals S separated from the composite video signal
The YNC is sent to the sub-field timing control unit (4) to generate signal pulses for frame period, field period, sub-field period, and row and column timing control. (11), sent to the data controller (12) and the driver controller (14). The driver controller (14) controls the driving of the Y electrode driver (16), the X electrode driver (17), and the data driver (18) to control the frame period, the field period, the subfield period, and the address of each subfield period. The timing of columns and rows in the period and the sustain discharge period is controlled. Further, the data driver (18) receives timing control from the driver controller (14) and, based on the pixel data sent from the data controller (12), generates a PDP during the subfield period to be turned on.
A signal voltage is supplied to the display unit (15), and the pixels specified in a matrix are turned on.

FIG. 2 shows a detailed configuration of the data discrimination section (1) and the subfield timing control section (4). The data discrimination section (1) comprises a frame memory (2) and a data discrimination circuit (3). The subfield timing control section (4) comprises a timing controller (5) and first, second and third sub-controllers. It comprises a field timing circuit (6, 7, 8) and a selector circuit (9).

The upper two bits of original image data R, G, B sent from the multi-tone processor (10) are temporarily stored in the frame memory (2). The 2-bit original image data is read out to the data discrimination circuit (3),
By discriminating any one of 1, 1 ×, it is determined which of the lower, middle, or upper gradation groups the original original image data is divided into three. That is, when the upper two bits are 00, the lower group is determined, when 01, the middle group is determined, and when the uppermost bit is 1, the upper group is determined. This discrimination signal is
It is sent to the selector circuit (9) of the subfield timing control section (4).

On the other hand, in the subfield timing control section (4), the timing controller (5) controls the externally supplied horizontal and vertical synchronization signals SYNC.
Frame, field, subfield,
Various timing pulses for lines and dots are created,
Multi-tone processor (10), frame memory (11),
The data is sent to the data controller (12) and the driver controller (14).

The timing controller (5) also controls the timing of the first, second and third subfield timing circuits (6, 7, 8). First, second and third subfield timing circuits (6, 7, 8)
Reads the subfield data corresponding to the lower, middle, and upper gradation groups from the subfield timing information prepared in the ROM or the like while receiving the control of the timing controller (5). 9). The ROM includes a first sub-field SF0, a second sub-field SF1, a third sub-field SF2, a fourth sub-field SF3, and a fifth sub-field SF3.
Subfield SF4, sixth subfield SF5
And each subfield timing control data of the seventh subfield SF6. These first to seventh subfields SF0, SF1, SF
2, SF3, SF4, SF5, SF6, the relative ratio of the length of the sustain discharge period in each subfield is 1:
2: 4: 8: 16: 5: 14. The first subfield timing circuit (6) includes a first subfield SF0, a second subfield SF1, a sixth subfield SF5, and a seventh subfield SF6.
The first sub-field data comprising the respective timing control data is prepared, and the second sub-field timing circuit (7) provides the second sub-field SF
First, second subfield data including timing control data of the third subfield SF2, the sixth subfield SF5, and the seventh subfield SF6 is prepared, and is supplied to the third subfield timing circuit (8). Are the third subfield SF2, the fourth subfield SF3, the fifth subfield SF4, the seventh
The third sub-field data including the sub-field SF6 is prepared. That is, the first, second and third sub-field data are those in which four sub-fields are selectively specified in the above-described combination from the seven sub-field timing control data. To achieve. The selector circuit (9) receives the gradation group discrimination signal sent from the data discrimination unit (1), selects any one of the subfield data, and sends out the data to the frame memory (11). It is stored in association with the original image data of bits. That is, the 4-bit original image data is composed of the lower, middle,
It is associated with a predetermined combination of subfields depending on which of the higher order it belongs to.

Table 1 shows the gradation of the original image data in the 4-bit 7-subfield system of the present invention, the corresponding subfield combinations, the luminance at that time, and the relative ratio thereof.

[0019]

[Table 1]

As a comparative example, similar values in the case of the conventional 4-bit 4-subfield system are shown. As can be seen from the table, in the present invention, 16 bits of original image data of 4 bits are used.
In the gradation display, four sub-fields SF in the lower four gradations are based on the above-described first sub-field data.
0, SF1, SF5 and SF6 are selected, and each bit of the original image data is assigned to this. In the middle four gradations, four subfields SF1, SF2, SF5 and SF6 are selected based on the above-mentioned second subfield data,
Each bit of the original image data is assigned to this. In the upper eight gradations, four subfields SF2, SF3, SF4,
SF6 is selected, and each bit of the original image data is assigned to it. As a result, the brightness difference between the gray levels from 1 to 4 is 1, 2, and 8 between the 4 to 8 gray levels.
The luminance difference between the gradation and the 9th gradation is 3, and the luminance difference from the 9th gradation to the 16th gradation is 4. On the other hand, in the comparative example, the luminance difference is constant at 2 between the 1st to 16th gradations.

FIG. 3 shows the relationship between the gradation and the luminance obtained from Table 1 by characteristic curves A and B for the respective cases of the present invention and the comparative example. The horizontal axis is the number of gradations, and the vertical axis is the relative ratio of luminance. According to the curve A, in the present invention, from one gradation to 4
The slope of the characteristic curve is different between the lower region up to the gray scale, the middle region from 4 gray scale to 8 gray scale, and the upper region from 9 gray scale to 16 gray scale. That is, the luminance difference between the gray levels in the low luminance area from the 1st to 4th gray levels is the smallest, and the luminance difference between the gray levels in the high luminance area from the 9th to 16th gray levels is the largest. .

On the other hand, from the curve B, conventionally, the relationship curve between the gradation and the luminance is linear, and the luminance rises or falls in proportion to the gradation. In such a case, when the display screen is actually observed, human visibility is high in a low luminance area, and a large luminance difference between gradations is felt. In a high luminance area, human visibility is low and the gradation is low. The difference in brightness between the two is felt small. Therefore, a clear image cannot be observed over the entire luminance region. On the other hand, in the present invention, such a display characteristic is corrected by the human perception characteristic by reducing the luminance difference between gradations in the low luminance region and increasing the luminance difference between gradations in the high luminance region. As a result, the brightness difference between the gray scales is recognized uniformly over the entire brightness area, and a clear image without unevenness in brightness is observed.

FIG. 4 shows a PD according to an embodiment of the present invention.
1 shows a configuration of one field in a P driving method. (A) of the figure shows the configuration of one field created by the timing controller (5), and includes seven sub-yields SF0, SF1, and SF0 having an address period and a sustain discharge period.
It consists of SF2, SF3, SF4, SF5 and SF6. These subfields SF0, SF1, SF2, SF
The sustain discharge periods of 3, SF4, SF5, and SF6 are changed so as to exhibit a predetermined luminance ratio. The length of the sustain discharge period is the length of the lighting time, and is associated with the luminance. Each subfield SF0, SF1, SF2, SF
3, the relative ratio of the lighting time of SF4, SF5 and SF6 is
1: 2: 4: 8: 16: 5: 14.

FIG. 2B shows a case where the original image data has one to four gradations, and is composed of four subfields SF0, SF1, SF5 and SF6 to which each bit is assigned.
FIG. 3C shows one field including four subfields SF1, SF2, SF5, and SF6 to which each bit is assigned when the original image data has five to eight gradations, and FIG. ) Is one field including four subfields SF2, SF3, SF4, and SF6 assigned to each bit when the original image data has 9 to 16 gradations. That is, in one field consisting of seven subfields in advance as shown in (a), four subfields are selectively provided as shown in (b), (c) or (d) in accordance with the gradation to be displayed. Prepared, each bit of the original image data is assigned to each subfield, and lighting and non-lighting are controlled to perform gradation display.

[0025]

According to the present invention, the luminance difference between gradations is reduced in advance in a low luminance region where human visibility is high, and the luminance difference between gradations is increased in advance in a high luminance region where human visibility is low. Since the luminance difference is expanded and recognized in the luminance region, and the luminance difference is compressed and recognized in the high luminance region, the density distribution of luminance perceived over the entire display luminance region is made uniform, and the display quality is improved. You.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a PDP according to an embodiment of the present invention.

FIG. 2 is a partial detailed diagram of a configuration of a PDP according to the embodiment of the present invention.

FIG. 3 is a characteristic curve showing a relationship between gradation and display luminance of the PDP according to the embodiment of the present invention.

FIG. 4 is a timing chart showing combinations of subfields according to the PDP driving method according to the embodiment of the present invention;

FIG. 5 is a configuration diagram of a conventional PDP.

[Explanation of symbols]

 Reference Signs List 1 data discriminating unit 2 frame memory 3 data discriminating circuit 4 subfield timing control unit 5 timing controller 6, 7, 8 subfield timing control circuit 9 selector circuit 10 multi-tone processor 11 frame memory 12 data controller 13 subfield timing control unit 14 Driver Controller 15 PDP Display 16 Y Electrode Driver 17 X Electrode Driver 18 Data Driver 19 Y Electrode 20 X Electrode

Claims (1)

[Claims] 1. A one-field period by controlling lighting and non-lighting of each of a plurality of subfields having a lighting time associated with a luminance of a predetermined relative ratio so as to show a desired luminance in a unit of one field. In the driving method of the flat panel display device which performs the multi-gradation display by controlling the total lighting time in the above, the gradation is divided into three gradation groups of lower 4 gradations, middle 4 gradations and upper 8 gradations The first, second, and third gradations respectively associated with the lower gradation group, the middle gradation group, and the higher gradation group depending on which of the gradation groups the original image data belongs to. Either of the selection methods is adopted, four subfields are selected from the seven subfields having a luminance of a predetermined relative ratio, and each of the selected subfields has four bits of original image data. Split each bit By controlling the lighting and non-lighting of the sub-fields, respectively, the luminance difference between the gradations belonging to the lower gradation group is minimized, and the luminance difference between the gradations belonging to the upper gradation group is maximized. A method for driving a flat panel display device.