JPH10160804A - Scancell - Google Patents

Abstract

[PROBLEMS] To grasp the average operation speed and the magnitude of AC delay over the entire integrated circuit chip while suppressing an increase in circuit elements required for measuring the operation speed and AC delay. SOLUTION: When a selection signal A is in an L state, it operates as a scan cell. On the other hand, when the selection signal A is in the H state, the signals of CK, CKN, CKA, and CKNA of the clocked inverters I1, I3, I4, and I6 become as shown in the figure, and operate as a buffer gate as a whole.
It can be used as a delay element of an AC chain for measuring an operation speed and an AC delay. Therefore, the scan cell can be used also as a delay element of the AC chain.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a flip-flop and a multiplexer, which are used as a flip-flop of a normal circuit to be tested. The present invention relates to a scan cell in which the flip-flop is switched from a normal circuit connection to a shift register together with another scan cell by the multiplexer, and each flip-flop is externally accessed by a shift operation. The present invention relates to a scan cell capable of grasping the magnitude of an average AC delay over an integrated circuit chip while suppressing an increase in circuit elements required for measuring an AC delay.

[0002]

2. Description of the Related Art Integrated circuits are guaranteed to operate at operating speeds in a range defined by their specifications. Therefore,
In order to satisfy such specifications, management is performed so that the manufacturing process falls within a variation range considered during design. In addition, a test of an integrated circuit to be shipped to determine whether or not such an operation speed specification is satisfied is performed by using a logic tester to determine whether a normal circuit operation is performed at the maximum operation speed specified in the specification. It is done by doing. Alternatively, it is performed by estimating the maximum operation speed of the integrated circuit to be shipped by a test using an AC chain described below.

In particular, a logic tester is very expensive if it has a limit on the maximum operation speed (maximum operation frequency) that can be tested or has a high maximum operation speed. For this reason, whether or not the integrated circuit to be shipped satisfies the operation speed specification is generally determined by a test using an AC chain.

The above-described AC chain is built in a target integrated circuit in order to evaluate whether the operation speed of the integrated circuit is fast or slow. For example, as shown in FIG. 1, FIG. 2 or FIG. There is something. Here, a time delay in which a signal change in the H state or the L state is transmitted to the internal circuit is referred to as an AC delay.

The AC chain of FIG. 1 is the most basic. Here, the delay time of the delay element D built in the integrated circuit also fluctuates according to the fluctuation of the operation speed or the AC delay of the integrated circuit which fluctuates due to the manufacturing process or the like. Therefore, the delay time of the delay element D is measured by measuring the time until the signal input to the input terminal PI is output to the output terminal PU, and the operating speed of the integrated circuit and AC
Delays can be predicted. Note that the delay time of the delay element D is set so that the signal delay time from the input terminal PI to the output terminal PU can be easily measured.

The AC chain shown in FIG. 2 is disclosed, for example, in Japanese Patent Application Laid-Open No. 60-79274, and has an input terminal P.
After a certain time from the input of the signal to I1, the input terminal P
A signal is input to I2, and the output signal of the delay element D is captured by the flip-flop FF. That is, the input terminal PI1
The signal input to the input terminal PI1 indicates the magnitude relationship between the signal delay time from the input to the input terminal PI1 of the flip-flop FF and the time from the input of the signal to the input terminal PI1 to the next input of the signal to the input terminal PI2. Is determined whether or not the signal after the change according to the above is correctly taken into the flip-flop FF.
I try to understand the C delay. Therefore, the operation speed and AC delay of the integrated circuit to be determined are determined by the flip-flop FF.
In this case, the influence of the measurement error due to the variation after the buffer B3 is removed, and the measurement accuracy is improved.

The AC chain shown in FIG.
The gate (delay element) is (M> N) in the N-stage delay element D1 and the M-stage delay element D2. Here, the input terminal PI
[Tm−Tn) / (M−N)], where Tn is the time until the signal input to the output terminal PU1 is output to the output terminal PU1 and Tm is the time until the signal input to the output terminal PU2 is output to the output terminal PU2. By calculating, the gate (delay element) 1 inside the integrated circuit
The average delay time per stage can be determined accurately.

A technique similar to the technique for determining the operating speed of an integrated circuit using an AC chain is disclosed in Japanese Patent Application Laid-Open No. 64-846.
57, JP-A-1-500927, JP-A-1-18796
8 and JP-A-5-19027, the operating speed and AC delay of an integrated circuit are obtained by a circuit using a ring oscillator as shown in FIG. In FIG. 4, after a certain period of time after a signal is input to the input terminal PI1, the input terminal P
When a signal is input to I2, the higher the operating speed or AC delay of the integrated circuit is, the higher the transmission frequency of the ring oscillator OSC is, and the more pulses are generated in a certain time. Therefore, if the number of pulses generated by the ring oscillator OSC in a certain time is counted by the counter CT and the count value is read from the output terminal PU, the operation speed and AC delay of the integrated circuit can be predicted from the count value. it can.

[0009] None of the above-mentioned prior arts mentions a specific configuration of the delay element.

[0010]

Here, in recent years, the chip size of integrated circuits has been increased, and the circuits to be manufactured have been further miniaturized. When the chip size increases in this way, variations in operating speed and AC delay within the chip increase. Therefore, even if the above-mentioned AC chain is formed in a part of the integrated circuit chip, the operating speed of this AC chain and the A
The C delay no longer represents the entire integrated circuit chip.

Under such circumstances, Japanese Patent Application Laid-Open No. 63-186
163 and JP-A-4-40738, a plurality of AC chains are formed on an integrated circuit chip.

However, when a plurality of AC chains are configured in this manner, the number of circuit elements increases, which reduces the degree of integration and causes other circuit configuration failures such as wiring arrangement failures. turn into. When the operation speed of the circuit is improved and the delay time of the circuit element is shortened, A
In order to obtain the necessary delay time in the delay elements constituting the C chain, many circuit elements such as logic gates are required, and there is also a problem that the integration degree is reduced in this aspect as well. The tendency described above increases as the chip size of the integrated circuit increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and it is possible to suppress an increase in the number of circuit elements required for measuring an operation speed and an AC delay while suppressing an average operation speed and an average over an integrated circuit chip. An object of the present invention is to provide a scan cell capable of grasping the magnitude of the AC delay.

[0014]

According to the present invention, there is provided a test data comprising a flip-flop and a multiplexer for changing or reading data stored in a flip-flop of a scan cell used as a flip-flop of a normal circuit to be tested. At the time of access, the flip-flop is switched from a normal circuit connection to a shift register together with another scan cell by the multiplexer, and each flip-flop is externally accessed by a shift operation. A terminal for inputting an operation mode signal indicating a mode, and in the through mode indicated by the operation mode signal at the time of access to the test data, the data sent from the preceding stage is transferred to the next scan cell by a predetermined internal delay. By which is adapted and a circuit for implementing the immediately feeds data through function after time, which solves the above problems.

In the scan cell of the present invention, the flip-flop is constituted by using a plurality of clocked inverters, and the data through function is realized by controlling the on state or the off state of these clocked inverters. The provision of the operation state control signal circuit for supplying these clocked inverters realizes the above-described data through function relatively easily.

Hereinafter, the operation of the present invention will be briefly described.

Testing of a semiconductor integrated circuit or a circuit built on a printed circuit board is premised on setting and monitoring the internal signal state from pins and terminals provided for external connection. A test method called a scan path method is known in order to effectively change and read data from a limited number of pins and terminals to an internal circuit. This uses a scan cell having a flip-flop and a multiplexer. For a flip-flop that changes or reads data stored in a test target circuit when accessing test data, the scan cell flip-flop is used. I do. At the time of test data access, a plurality of scan cells and flip-flops included in the scan cells are switched from a normal circuit connection to a shift register by a multiplexer included in the scan cells, and the flip-flops of the scan cells are externally connected to the flip-flops of the scan cells by a shift operation. to access.

In the present invention, such a scan cell is called AC
It is also used for chains. Therefore, the number of new circuit elements required for forming the AC chain is very small, and the degree of integration can be improved. In addition, since such a scan cell is generally arranged in each section over the entire integrated circuit chip, if an AC chain is formed by such a scan cell, the average operation speed and the magnitude of the AC delay over the entire integrated circuit chip can be grasped. can do. Therefore, according to the present invention, it is possible to grasp the average operation speed and the magnitude of the AC delay over the entire integrated circuit chip while suppressing an increase in circuit elements required for measuring the operation speed and the AC delay.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

First, a conventional scan cell which is a premise of a first embodiment and a second embodiment to be described later to which the present invention is applied includes a multiplexer M and clocked inverters I1, I3, as shown in FIG. It comprises I4, I6 and inverters I2, I5, I7-I9.
Here, one flip-flop is formed by the inverter I2 and the clocked inverter I3, and another flip-flop is formed by the inverter I5 and the clocked inverter I6. Clocked inverter I
1, I3, I4 and I6, that is, the clocked inverters shown in FIG. 6 are all internal circuits as shown in FIG. 7 or are internal circuits as shown in FIG. Here, such a clocked inverter has the input Y
Is in the L state and the input Z is in the H state, it operates as a normal inverter. On the other hand, when the input Y is in the H state and the input Z is in the L state, the output U is in a high impedance state.

Such a scan cell is used, for example, as shown in FIG. 9 to enable a scan path test method.

In the test system of the scan path system, for example, as shown in FIG. 9, a circuit to be tested is divided into a plurality of circuit blocks such as circuit blocks BL1 to BL3. It is also performed to arrange scan cells S1, S2,. These scan cells S1, S2... Are also referred to as boundary scan registers, and are used to effectively set the input signals and read (monitor) the output signals of each of the circuit blocks BL1 to BL3. It can be carried out.

Here, at the time of system data access using scan cells S1 and S2 as ordinary flip-flops connected to circuit blocks BL1 to BL3, selection signal SEL is set to L state. On the other hand, a plurality of scan flip-flops are configured as shift registers, and the select signal SEL is set to the H state at the time of test data access for changing or reading data. In this conventional example, data is taken in at the time of rising of the clock signal CL.

When the signals input to the terminals corresponding to the inputs Y and Z shown in FIG. 6 are exchanged with each other in the clocked inverters I1, I3, I4 and I6, the clock signal CL is changed. This becomes a scan cell that takes in data at the falling edge, and is a conventional example which is a premise of a second embodiment described later.

FIG. 10 is a circuit diagram of a first embodiment of a scan cell to which the present invention is applied.

This embodiment is different from the conventional example shown in FIG. 5 and the like in that a terminal for inputting the selection signal A is provided, and a plurality of clocks are provided in accordance with the selection signal A in addition to the clock signal CL. Control signal to be supplied to the inverter,
In other words, the difference is that an operation state control signal circuit for generating clock signals CK, CKN, CKA, and CKNA is provided. This operation state control signal circuit includes an OR logic gate G1 and inverters I11 to I13. The operation of the operation state control signal circuit is as shown in the truth table of FIG.

The operation of this embodiment will be described. First, when the selection signal A is in the L state ("0"), as apparent from the truth table of FIG. The operation is the same as in the conventional example. That is, as shown in FIG. 12, the clock signal CKA becomes the same as the clock signal CK, the clock signal CKNA becomes the same as the clock signal CKN, and the basic operation as a scan cell is performed similarly to the conventional example shown in FIG. Do.

On the other hand, in the through mode, the selection signal A is H
In the state ("1"), when the clock signal CL is fixed to the L state, the circuit operates as shown in FIG. 13, and the circuit operation is substantially as shown in FIG.
That is, the signal input from the delay elements D1 and D2 is delayed by the multiplexer M, the clocked inverter I1, the inverter I2, the clocked inverter I4 and the inverter I5, and is output as the output Q in the same logical state.
Alternatively, the logic is further delayed and inverted by the inverter I7 and output as the output Q bar. Accordingly, since the output Q and the output Q bar are output with such a delay, the scan cell can be used as a delay element of the AC chain or a part of the delay element.

FIG. 15 is a time chart showing the operation of this embodiment. Before time t13, the selection signal A is L
The state is the normal mode. At time t11 and time t12, the signal of the shift data signal SIN is taken in at the rise of the clock signal CL, and the signal of the output Q changes. On the other hand, if the selection signal A is in the H state after time t13,
In the through mode, when the shift data signal SIN changes, for example, at times t15, t16, and t17, the output Q immediately changes after a predetermined internal delay time. That is,
Immediately after a predetermined internal delay time, which is the sum of the delay times of the multiplexer M, the clocked inverter I1, the inverter I2, the clocked inverter I4, and the inverter I5, it is output as the output Q. Alternatively, after a predetermined internal delay time further including the delay time of the inverter I7, the logic is inverted by the inverter I7 and output as the output Q bar. In this case, the shift data signal SIN is a signal used for obtaining the operation speed and the AC delay. However, when the scan cell is operated as a shift register, the shift data signal SIN becomes the signal as its name.

FIG. 16 is a circuit diagram of a scan cell according to a second embodiment of the present invention.

In this embodiment, the data is taken in by the internal flip-flop at the falling of the clock signal CL. The input Y and the input Z of FIG. 6 are the same as those of the first embodiment except that the clocked inverters I1, I3, I4,
For each of I6, the signals of input Y and input Z in FIG. 6 are interchanged.

The operation state control signal circuit according to the present embodiment includes an AND logic gate G2 and inverters I14 to I16. The circuit operation of the operation state control signal circuit is as shown in the truth table of FIG.

The operation of this embodiment will be described.
First, in the normal mode, when the selection signal A is in the L state, the clock signal CKA becomes the same as the clock signal CK, the clock signal CKNA becomes the same as the clock signal CKN, and the circuit operation state is as shown in FIG. Becomes Therefore, the present embodiment performs the same basic operation as a scan cell similar to the above-described conventional example shown in FIG.

Next, in the present embodiment, the through mode is set, so that when the selection signal A goes to the H state, the circuit operation is as shown in FIG. 19 if the clock signal CL is in the L state. This operation state is equivalent to the circuit of FIG. Therefore, the shift data signal SIN input to the delay element D1 is
Immediately after a predetermined internal delay time, which is the sum of the delay times of the multiplexer M, the clocked inverter I1, the inverter I2, the clocked inverter I4, and the inverter I5, it is output as the output Q. Alternatively, after a predetermined internal delay time further including the delay time of the inverter I7, the logic is inverted by the inverter I7 and output as the output Q bar. Therefore, the scan cell in such an operation state can be used as a delay element of an AC chain. In this case, the shift data signal SIN is a signal used for obtaining the operation speed and the AC delay. However, when the scan cell is operated as a shift register, the shift data signal SIN becomes the signal as its name.

FIG. 20 is a time chart showing the operation of this embodiment. In this time chart, before time t13, the selection signal A is in the L state, and thus the mode is the normal mode, and the logical state of the shift data signal SIN is taken in every falling of the clock signal CL, and the output Q changes accordingly. On the other hand, after time t13, the selection signal A is in the H state and thus the through mode is set. When the logical state of the shift data signal SIN changes, the output Q is immediately changed after a predetermined internal delay time, for example, at times t14 to t17. The logic state changes.

As described above, according to the first and second embodiments of the present invention, when the logic state of the shift data signal SIN changes in the through mode, the logic of the output Q or the output Q bar after a predetermined internal delay. The state changes, and it can be used as a delay element of a delay circuit of an AC chain.
Therefore, since the scan cell can be used for the AC chain, the utilization efficiency of the circuit element is improved and the degree of integration is improved. Also, since the scan cell is generally arranged over the entire integrated circuit chip, if the operation speed and the AC delay are measured using the scan cell of the present embodiment, the average operation speed and the AC delay over the entire integrated circuit chip can be obtained. Can be effectively grasped.

In this embodiment, the scan cells can be prepared as hard macro cells in both the first embodiment and the second embodiment. By preparing the hard macro cell as described above, the designer can form an AC chain simply by using the conventional scan cell in the same manner as in the conventional scan cell, and the design work efficiency is high. When preparing as a hard macro cell, if an inverter of a clock system, an OR logic gate G, and an AND logic gate are used as in this embodiment, the entire circuit area can be reduced because these gates are small. . This point is the same when the integrated circuit chip is large.

[0038]

As described above, according to the present invention, it is possible to suppress the increase in the number of circuit elements required for measuring the operation speed and the AC delay, and to reduce the average operation speed and A
The magnitude of the C delay can be grasped.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first example of the most basic conventional AC chain.

FIG. 2 shows a second example of a conventional AC chain with reduced measurement error.
Example circuit diagram

FIG. 3 is a circuit diagram of a third example of a conventional AC chain capable of measuring a delay time per gate.

FIG. 4 is a circuit diagram of a circuit using a ring oscillator for measuring an AC delay.

FIG. 5 is a circuit diagram of a conventional scan cell which is a premise of the embodiment of the present invention.

FIG. 6 is a diagram showing circuit symbol symbols of a clocked inverter used for the scan cell;

FIG. 7 is a circuit diagram of a first example of the clocked inverter.

FIG. 8 is a circuit diagram of a second example of the clocked inverter.

FIG. 9 is a circuit diagram showing a use form of the scan cell;

FIG. 10 is a circuit diagram of a scan cell according to a first embodiment of the present invention;

FIG. 11 is a diagram of a truth table showing an operation of the operation state control signal circuit used in the first embodiment.

FIG. 12 is a circuit diagram showing an operation state of the first embodiment in a normal mode.

FIG. 13 is a circuit diagram showing an operation state in the through mode of the first embodiment.

FIG. 14 is an equivalent circuit diagram in the through mode of the first embodiment.

FIG. 15 is a time chart showing the operation of the first embodiment.

FIG. 16 is a circuit diagram of a scan cell according to a second embodiment of the present invention;

FIG. 17 is a diagram of a truth table showing the operation of the operation state control signal circuit used in the second embodiment.

FIG. 18 is a circuit diagram showing an operation state in a normal mode of the second embodiment.

FIG. 19 is a circuit diagram showing an operation state in a through mode of the second embodiment.

FIG. 20 is a time chart showing the operation of the second embodiment.

[Explanation of symbols]

 PI, PI1, PI2 ... input terminals PU, PU1, PU2 ... output terminals B, B1 to B3 ... buffers D, D1, D2 ... delay elements FF ... flip-flops OSC ... ring oscillators CT ... counters SIN ... shift data signals D0 to D2 , X to Z ... input signals SEL, A ... selection signals SD1 to SD3 ... data signals CL, CK, CKN, CKA, CKNA ... clock signals BL1 to BL3 ... circuit blocks S1, S2 ... scan cells M ... multiplexers I1, I3, I4, I6: Clocked inverter I2, I5, I7 to I16: Inverter G, G1: OR logic gate G2: AND logic gate TP10 to TP12: P-channel MOS transistor TN10 to TN12: N-channel MOS transistor

Claims (2)

[Claims] 1. A test data access device comprising a flip-flop and a multiplexer, which is used as a flip-flop of a normal circuit to be tested, for changing and reading data stored in the flip-flop of the scan cell, together with other scan cells. In the scan cell in which the flip-flop is switched from a normal circuit connection to a shift register by the multiplexer, and each flip-flop is externally accessed by a shift operation, an operation mode signal indicating a through mode or a normal mode is input. And in the through mode indicated by the operation mode signal at the time of the test data access, the data sent from the preceding stage is immediately sent to the next scan cell after a predetermined internal delay time. Scan, characterized in that as and a circuit for implementing data through function. 2. The data processing system according to claim 1, wherein said flip-flop is constituted by using a plurality of clocked inverters. In order to realize said data through function by controlling on / off states of said clocked inverters. A scan cell comprising an operation state control signal circuit for supplying a clocked inverter.