JPH10154723A - Structure of wire bonding for resin packaged semiconductor device - Google Patents
Structure of wire bonding for resin packaged semiconductor deviceInfo
- Publication number
- JPH10154723A JPH10154723A JP8311016A JP31101696A JPH10154723A JP H10154723 A JPH10154723 A JP H10154723A JP 8311016 A JP8311016 A JP 8311016A JP 31101696 A JP31101696 A JP 31101696A JP H10154723 A JPH10154723 A JP H10154723A
- Authority
- JP
- Japan
- Prior art keywords
- island
- semiconductor element
- heat
- semiconductor device
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、樹脂封止型半導体
装置のワイヤボンド構造に関する。The present invention relates to a wire bond structure for a resin-sealed semiconductor device.
【０００２】[0002]
【従来の技術】一般に、半導体素子は、シリコンウエハ
ー上に様々な電気的回路が配線されている集積回路であ
る。半導体素子１と外部端子との電気的接続は、図３
（ａ）に示されるように、半導体素子１のボンディング
パットに一端を接続された一般に金ワイヤからなる金属
細線２の他端をインナーリード４に接続して行われてい
る。このインナーリード４は、リードフレームの樹脂封
止される部分である。2. Description of the Related Art Generally, a semiconductor device is an integrated circuit in which various electric circuits are wired on a silicon wafer. The electrical connection between the semiconductor element 1 and the external terminals is shown in FIG.
As shown in (a), the bonding is performed by connecting the other end of a thin metal wire 2 generally made of a gold wire having one end connected to a bonding pad of the semiconductor element 1 to an inner lead 4. The inner leads 4 are portions of the lead frame to be sealed with resin.
【０００３】半導体素子１は、その裏面に積層状態に設
けられた導電性ペースト３により、リードフレームのア
イランド５に接着されている。このアイランド５は半導
体素子１を搭載するリードフレームの中心部であり、上
記導電性ペースト３には一般にＡｇ入りエポキシ樹脂が
使用されている。The semiconductor element 1 is bonded to the island 5 of the lead frame by a conductive paste 3 provided on the back surface in a laminated state. The island 5 is the center of the lead frame on which the semiconductor element 1 is mounted, and the conductive paste 3 is generally made of an epoxy resin containing Ag.
【０００４】図３（ａ）の半導体素子とインナーリード
およびヒート駒の関係を詳細に示す図である図３（ｂ）
に示されるように、アイランド５を形成するリードフレ
ームには、金型で制作されることにより発生するダレか
らなる抜きバリ６が周縁部に形成されている。また、ヒ
ートコマ７上に半導体素子１及びインナーリード４が載
置状態に設けられているが、このヒートコマ７は、超音
波熱圧着ボールボンドする際に、半導体素子１及びイン
ナーリード４を加熱・固定する専用治具である。FIG. 3 (b) is a diagram showing in detail the relationship between the semiconductor element of FIG. 3 (a), inner leads and heat pieces.
As shown in FIG. 2, a lead frame forming the island 5 is provided with a punch burr 6 formed on the periphery of the lead frame, which is formed by sagging by being manufactured with a metal mold. Further, the semiconductor element 1 and the inner lead 4 are provided on the heat top 7 in a mounted state. The heat top 7 heats and fixes the semiconductor element 1 and the inner lead 4 when performing ultrasonic thermocompression bonding. It is a special jig to do.
【０００５】上記した例では半導体素子１をアイランド
５を介してヒートコア上に設けた構造について示した
が、図４（ａ）に示されるようにヒートコマ７上に直接
半導体素子１を設けた樹脂封止型半導体のＬＯＣ構造の
場合もある。そのワイヤボンド点の要部を拡大した断面
図である図４（ｂ）に併せて示されるように、この場合
には、アイランド５が無く、その抜きバリの影響はない
が、ウエハーから個々の半導体素子に分割する工程があ
り、半導体素子１裏面の周辺に切削によるシリコン屑８
が残る場合がある。In the above example, the structure in which the semiconductor element 1 is provided on the heat core via the island 5 is shown. However, as shown in FIG. In some cases, the LOC structure may be a fixed semiconductor. As shown in FIG. 4B, which is an enlarged sectional view of the main part of the wire bond point, in this case, there is no island 5 and there is no influence of the burrs. There is a step of dividing the semiconductor element 1 into silicon chips 8 by cutting around the back surface of the semiconductor element 1.
May remain.
【０００６】なお、この構造においては、半導体素子１
の上面にポリイミド絶縁テープ１１が取り付けられ、そ
のポリイミド絶縁テープ１１上に、インナーリード４の
端部が乗せられていると共にバスバーリード１２が取り
付けられている。このバスバーリード１２をかわすよう
にして、金属細線２が、半導体素子１とインナーリード
４とを接続している。In this structure, the semiconductor element 1
A polyimide insulating tape 11 is mounted on the upper surface of the substrate. On the polyimide insulating tape 11, the end of the inner lead 4 is mounted and a bus bar lead 12 is mounted. The metal wire 2 connects the semiconductor element 1 and the inner lead 4 in such a way as to bypass the bus bar lead 12.
【０００７】[0007]
【発明が解決しようとする課題】ところで、リードフレ
ーム製造方法としては、薬液でエッチングし製作する方
法と金型で打ち抜く方法がある。後者の場合には、上型
と下型のクリアランスの関係で上記した抜きバリ６が発
生する。抜きバリ６は、リードフレーム材料により異な
るが、銅系材料で約５０ミクロン、４２アロイ等の鉄系
材料で約３０ミクロン発生する。As a method of manufacturing a lead frame, there are a method of manufacturing by etching with a chemical solution and a method of punching with a die. In the latter case, the above-mentioned burrs 6 occur due to the clearance between the upper die and the lower die. The burrs 6 are generated by a copper-based material of about 50 microns and an iron-based material such as 42 alloy of about 30 microns, depending on the lead frame material.
【０００８】樹脂封止型半導体のワイヤボンドは、現在
超音波熱圧着方法が一般的である。そのワイヤボンド実
施時には、半導体素子１とアイランド３及びインナーリ
ード５とを加熱固定しなければならない。そのため、下
部からヒートコマ７で加熱しさらに上部より治具で押さ
えて固定する必要がある。この際、前記抜きバリ６があ
るためアイランド５の固定が不安定になり、超音波振動
が十分作用せず、金属細線ボンディングパットの良好な
接触が得られないという問題があった。[0008] Ultrasonic thermocompression bonding is generally used for wire bonding of resin-sealed semiconductors. When the wire bonding is performed, the semiconductor element 1, the island 3, and the inner lead 5 must be fixed by heating. Therefore, it is necessary to heat the lower part with the heat top 7 and to fix the upper part with a jig. At this time, there is a problem that the fixing of the island 5 becomes unstable due to the presence of the burrs 6, the ultrasonic vibration does not sufficiently act, and good contact of the metal fine wire bonding pad cannot be obtained.
【０００９】また、図４に示した樹脂封止型半導体のＬ
ＯＣ構造のワイヤボンドでは、前記したようにヒートコ
マが直接半導体素子１と接触するため、アイランド５の
抜きバリの影響がないが、ウエハーから個々の半導体素
子を分割する工程における切削によるシリコン屑８が半
導体素子１の周辺部の裏面側に残り、超音波振動が十分
働かずに金属細線２とボンディングパットとの良好な接
合が得られないという問題があった。Further, the L of the resin-encapsulated semiconductor shown in FIG.
In the wire bond having the OC structure, since the heat piece directly contacts the semiconductor element 1 as described above, there is no influence of the burrs of the island 5. However, the silicon dust 8 generated by the cutting in the step of dividing the individual semiconductor element from the wafer is reduced. There is a problem that the ultrasonic wave does not sufficiently act on the rear surface side of the peripheral portion of the semiconductor element 1 so that good bonding between the thin metal wire 2 and the bonding pad cannot be obtained.
【００１０】[0010]
【課題を解決するための手段】このような従来技術の課
題を有利に解決して、半導体素子とインナーリードとを
接続する金属細線の良好な接続を実現するために、本発
明に於いては、ヒートコマ上にアイランド及び導電性ペ
ーストを介して設置された半導体素子とインナーリード
とを金属細線で接続する樹脂封止型半導体装置のワイヤ
ボンド構造において、前記ヒートコマの前記アイランド
の周縁部に対応する部分に溝を設け、または、ヒートコ
マ上に直接設置された半導体素子とインナーリードとを
金属細線で接続する樹脂封止型半導体装置のワイヤボン
ド構造において、前記ヒートコマの前記半導体素子の周
縁部に対応する部分に溝を設けたものとした。SUMMARY OF THE INVENTION In order to solve the problems of the prior art advantageously and to realize a good connection of a thin metal wire for connecting a semiconductor element and an inner lead, the present invention provides In a wire bonding structure of a resin-encapsulated semiconductor device in which a semiconductor element and an inner lead provided on a heat piece via an island and a conductive paste are connected by a thin metal wire, the wire corresponds to a peripheral portion of the island of the heat piece. In a wire bond structure of a resin-encapsulated semiconductor device in which a groove is provided in a portion, or a semiconductor element directly mounted on a heat top and an inner lead are connected by a thin metal wire, the wire corresponds to a peripheral portion of the semiconductor element of the heat top A groove was provided at the portion where the heat treatment was performed.
【００１１】[0011]
【発明の実施の形態】以下に添付の図面に示された具体
例に基づいて本発明の実施の形態について詳細に説明す
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to specific examples shown in the accompanying drawings.
【００１２】図１（ａ）は、本発明が適用された半導体
装置のワイヤボンド構造を示す概要図であり、図１
（ｂ）は、図１（ａ）の半導体素子１とインナーリード
４及びヒートコマ７との関係を示す要部拡大図である。
図１において、従来例の図３で示したものと同様の部分
には同一の符号を付してその詳しい説明を省略する。FIG. 1A is a schematic diagram showing a wire bond structure of a semiconductor device to which the present invention is applied.
FIG. 2B is an enlarged view of a main part showing a relationship between the semiconductor element 1 of FIG.
In FIG. 1, the same parts as those of the conventional example shown in FIG. 3 are denoted by the same reference numerals, and the detailed description thereof will be omitted.
【００１３】この半導体素子１は、従来例と同様に、シ
リコンウエハー上に様々な電気的回路を配線してなる集
積回路である。樹脂封止型半導体のワイヤボンドにあっ
ては現在超音波熱圧着方法が一般的であり、半導体素子
１とアイランド３およびインナーリード５とを加熱固定
する。そのためには、ヒートコマ７で半導体素子１を下
部から加熱すると共に上部より治具で押さえて固定する
必要がある。なお、ヒートコマ７は、一般にＳＫ材から
なり、その形状によりボンダビリティーに影響を及ぼす
ため、重要なものである。The semiconductor element 1 is an integrated circuit formed by wiring various electric circuits on a silicon wafer, as in the conventional example. At present, an ultrasonic thermocompression bonding method is generally used for wire bonding of a resin-sealed semiconductor, and the semiconductor element 1, the island 3, and the inner lead 5 are fixed by heating. For that purpose, it is necessary to heat the semiconductor element 1 from below by the heat top 7 and to fix it by pressing it from above to the jig. The heat piece 7 is important because it is generally made of SK material and its shape affects bondability.
【００１４】ところで、従来例で示したように、リード
フレーム製造方法としては、薬液でエッチングし製作す
る方法と、金型で打ち抜く方法とがあるが、金型を用い
る場合には、アイランド５の周縁部に、金型制作におけ
る上型と下型のクリアランスの関係で発生する抜きバリ
６が形成されてしまう。抜きバリ６があると、アイラン
ド５の固定が不安定になり、超音波振動が十分働かず、
金属細線２とボンデイングパットとが良好に接続されな
い虞がある。By the way, as shown in the conventional example, there are a method of manufacturing by etching with a chemical solution and a method of punching out with a die as a method of manufacturing a lead frame. A punch burr 6 which is generated in the peripheral portion due to the clearance between the upper mold and the lower mold in the mold production is formed. If the burrs 6 are present, the fixing of the island 5 becomes unstable, and the ultrasonic vibration does not work sufficiently.
There is a possibility that the fine metal wire 2 and the bonding pad are not connected well.
【００１５】そこで本発明によれば、図１に良く示され
るように、ヒートコマ７のアイランド５の周縁部に対応
する部分に、上記抜きバリ６との接触を回避するための
溝９が、例えば放電加工にて設けられている。溝９の形
状は、リードフレームの搬送位置決め精度や抜きバリ６
の大きさ、及び半導体素子１のサイズを考慮して決定す
れば良い。Therefore, according to the present invention, as shown in FIG. 1, a groove 9 for avoiding contact with the punch burr 6 is formed in a portion of the heat piece 7 corresponding to the peripheral edge of the island 5, for example. It is provided by electric discharge machining. The shape of the groove 9 depends on the positioning accuracy of the lead frame transporting and the punching burr 6.
And the size of the semiconductor element 1 may be determined.
【００１６】例えば、従来例で示したように抜きバリ６
の高さが、リードフレームが銅系材料で約５０ミクロ
ン、４２アロイ等の鉄系材料で約３０ミクロンであるこ
とから、溝９の深さを０．１ｍｍ以上にすると良く、ま
た、溝９の内側の側壁の位置は、アイランド５の周縁よ
りも内側（アイランド５の中心側）に０．１５〜０．２
ｍｍ程度の所にすることが適当である。（インナーリー
ド側は、リード端面と同位置である。）For example, as shown in the conventional example,
Since the height of the lead frame is about 50 μm for a copper-based material and about 30 μm for an iron-based material such as 42 alloy, the depth of the groove 9 is preferably 0.1 mm or more. Of the inner side wall is 0.15 to 0.2 inward of the periphery of the island 5 (center side of the island 5).
It is appropriate that the distance is about mm. (The inner lead side is at the same position as the lead end face.)
【００１７】これにより、抜きバリ６の影響を受けるこ
となく、ヒートコマ７の溝９の内側に画定された島部７
ａの上面にアイランド５の底面が密着状態に載置可能に
なり、半導体素子１の固定状態が安定化して、ワイヤボ
ンドの超音波による接合が安定するため、ボンダビリテ
ィーが向上し得る。また、伝熱に関しても向上し、半導
体素子１のボンディングパッド（図示なし）の温度が均
一になり、低温ボンドが可能となる。また銅系リードフ
レームにあっては、低温化により酸化を抑制することが
でき、基板実装時の赤外線リフロー処理によるアイラン
ド裏面剥離を防止できる。Thus, the island portion 7 defined inside the groove 9 of the heat top 7 is not affected by the burr 6.
The bottom surface of the island 5 can be placed in close contact with the upper surface of “a”, the fixed state of the semiconductor element 1 is stabilized, and the bonding by ultrasonic bonding of wire bonds is stabilized, so that bondability can be improved. Further, the heat transfer is improved, the temperature of the bonding pad (not shown) of the semiconductor element 1 becomes uniform, and low-temperature bonding becomes possible. In the case of a copper-based lead frame, oxidation can be suppressed by lowering the temperature, and peeling of the back surface of the island due to infrared reflow processing at the time of mounting the substrate can be prevented.
【００１８】図２は、本発明の第２の実施形態を示すも
のであり、樹脂封止型半導体のＬＯＣ構造のワイヤボン
ド点の断面図であり、従来例の図４で示したものと同様
の部分には同一の符号を付してその詳しい説明を省略す
る。FIG. 2 shows a second embodiment of the present invention and is a cross-sectional view of a wire bonding point of a LOC structure of a resin-encapsulated semiconductor, which is the same as that shown in FIG. Are given the same reference numerals, and detailed description thereof is omitted.
【００１９】また、上記第１の実施の形態との相違点
は、ヒートコマ７上に半導体素子１が直接接触している
点である。この場合、上記のアイランド５が無く、した
がって抜きバリ６の影響を受けることがないが、ウエハ
ーから個々の半導体素子に分割する工程を経るため、図
に示されるように、半導体素子１の裏面の周辺に、上記
分割時の切削によるシリコン屑８が残る場合がある。The difference from the first embodiment is that the semiconductor element 1 is in direct contact with the heat top 7. In this case, there is no above-mentioned island 5 and therefore there is no influence of the punch burr 6. However, since the wafer is divided into individual semiconductor elements, as shown in FIG. In some cases, silicon dust 8 due to the cutting at the time of the division may remain around.
【００２０】このため第１の実施の形態と同様にヒート
コマ７に溝９を形成している。この場合の溝９の大き
さ、深さなどは前記第１の実施の形態で示したものと同
様であって良い。For this reason, a groove 9 is formed in the heat piece 7 as in the first embodiment. In this case, the size, depth, and the like of the groove 9 may be the same as those described in the first embodiment.
【００２１】これにより、半導体素子１の裏面の周辺部
に残ったシリコン屑８が溝９に落ち得るため、半導体素
子１とヒートコマ７の島部７ａとが面で密着し得るた
め、半導体素子１に曲げ応力が働かず、半導体素子１の
クラック発生を防止できる。また、ヒートコマ７と半導
体素子１との密着性が向上するので、金属細線２とボン
デイングパットとの接合状態がより一層安定する。As a result, the silicon chips 8 remaining on the peripheral portion of the back surface of the semiconductor element 1 can fall into the groove 9, and the semiconductor element 1 and the island portion 7 a of the heat piece 7 can be in close contact with each other on the surface. The bending stress does not act on the semiconductor element 1, and the occurrence of cracks in the semiconductor element 1 can be prevented. Further, since the adhesion between the heat piece 7 and the semiconductor element 1 is improved, the bonding state between the fine metal wire 2 and the bonding pad is further stabilized.
【００２２】[0022]
【発明の効果】このように本発明によれば、半導体素子
をワイヤボンドする際に加熱固定するべく、半導体素子
をアイランドを介してヒートコマ上に載置する場合には
アイランド裏面周辺に抜きバリが発生し、半導体素子を
ヒートコマ上に直接載置する場合には半導体素子の分割
時にシリコン屑が発生するが、抜きバリやシリコン屑を
溝に落として、それらの影響を受けずに、半導体素子と
インナーリードとを金属細線で接続することができるた
め、半導体素子のボンデイングパットと金属細線との接
合状態が向上し、低温接合が可能となると共に、ＬＯＣ
構造の半導体素子を製造する際に発生する半導体素子の
クラックを防止し得る。As described above, according to the present invention, when a semiconductor element is mounted on a heat top via an island in order to heat and fix the semiconductor element at the time of wire bonding, a burr is formed around the back surface of the island. When the semiconductor element is directly mounted on the heat top, silicon chips are generated when the semiconductor element is divided.Burrs and silicon chips are dropped into the grooves, and the semiconductor elements are not affected by these. Since the inner lead can be connected to the thin metal wire, the bonding condition between the bonding pad of the semiconductor element and the thin metal wire is improved, and low-temperature bonding is possible, and LOC is achieved.
It is possible to prevent cracking of the semiconductor element that occurs when manufacturing a semiconductor element having a structure.
【図１】（ａ）は、本発明の第１の実施形態であるワイ
ヤボンド点の断面図であり、（ｂ）は、（ａ）の要部拡
大断面図である。FIG. 1A is a cross-sectional view of a wire bonding point according to a first embodiment of the present invention, and FIG. 1B is an enlarged cross-sectional view of a main part of FIG.
【図２】（ａ）は、本発明の第２の実施形態であるワイ
ヤボンド点の断面図であり、（ｂ）は、（ａ）の要部拡
大断面図である。FIG. 2A is a sectional view of a wire bonding point according to a second embodiment of the present invention, and FIG. 2B is an enlarged sectional view of a main part of FIG.
【図３】（ａ）は、従来のワイヤボンド点の断面図であ
り、（ｂ）は、（ａ）の要部拡大断面図である。3A is a cross-sectional view of a conventional wire bond point, and FIG. 3B is an enlarged cross-sectional view of a main part of FIG.
【図４】（ａ）は、従来のＬＯＣ構造でのワイヤボンド
点の断面図であり、（ｂ）は、（ａ）の要部拡大断面図
である。4A is a cross-sectional view of a wire bonding point in a conventional LOC structure, and FIG. 4B is an enlarged cross-sectional view of a main part of FIG.
１ 半導体素子 ２ 金属細線 ３ 導電性ペースト ４ インナーリード ５ アイランド ６ 抜きバリ ７ ヒートコマ ７ａ 島部 ８ シリコン屑 ９ 溝 １１ ポリイミド絶縁テープ １２ バスバーリード REFERENCE SIGNS LIST 1 semiconductor element 2 thin metal wire 3 conductive paste 4 inner lead 5 island 6 punched burr 7 heat coma 7a island 8 silicon debris 9 groove 11 polyimide insulating tape 12 busbar lead
Claims (2)
ペーストを介して設置された半導体素子とインナーリー
ドとを金属細線で接続する樹脂封止型半導体装置のワイ
ヤボンド構造において、 前記ヒートコマの前記アイランドの周縁部に対応する部
分に溝を設けたことを特徴とする樹脂封止型半導体装置
のワイヤボンド構造。1. A wire bonding structure of a resin-encapsulated semiconductor device in which a semiconductor element and an inner lead provided on a heat top via an island and a conductive paste are connected by a thin metal wire, wherein a periphery of the island of the heat top is provided. A wire bond structure for a resin-encapsulated semiconductor device, wherein a groove is provided in a portion corresponding to a portion.
素子とインナーリードとを金属細線で接続する樹脂封止
型半導体装置のワイヤボンド構造において、 前記ヒートコマの前記半導体素子の周縁部に対応する部
分に溝を設けたことを特徴とする樹脂封止型半導体装置
のワイヤボンド構造。2. A wire bonding structure of a resin-encapsulated semiconductor device in which a semiconductor element and an inner lead directly mounted on a heat piece are connected by a thin metal wire, wherein a portion of the heat piece corresponding to a peripheral portion of the semiconductor element is provided. A wire bond structure of a resin-encapsulated semiconductor device, wherein a groove is provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8311016A JPH10154723A (en) | 1996-11-21 | 1996-11-21 | Structure of wire bonding for resin packaged semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8311016A JPH10154723A (en) | 1996-11-21 | 1996-11-21 | Structure of wire bonding for resin packaged semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10154723A true JPH10154723A (en) | 1998-06-09 |
Family
ID=18012112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8311016A Pending JPH10154723A (en) | 1996-11-21 | 1996-11-21 | Structure of wire bonding for resin packaged semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10154723A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007127673A (en) * | 2007-02-22 | 2007-05-24 | Matsushita Electric Ind Co Ltd | Rotation speed sensor |
| JP2014120544A (en) * | 2012-12-14 | 2014-06-30 | Mitsubishi Electric Corp | Light emitting device |
-
1996
- 1996-11-21 JP JP8311016A patent/JPH10154723A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007127673A (en) * | 2007-02-22 | 2007-05-24 | Matsushita Electric Ind Co Ltd | Rotation speed sensor |
| JP2014120544A (en) * | 2012-12-14 | 2014-06-30 | Mitsubishi Electric Corp | Light emitting device |
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