JPH10154709A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve embedding of Cu when forming fine contact holes in an ultra high-speed device using Cu. SOLUTION: For example, a fin connection hole 23 is formed in an interlayer insulation film 22 on an Si substrate 21. In addition, after a CD-TiN film 24 approx. 10nm thick is formed on the insulation film 22, a Cu film 25 of approx. 1μm thick is formed thereon. At this time, the condition of film formation is controlled in a manner that the concentration of oxygen and sulphur in the film 25 may be made lower than a specified concentration, thereby forming the film 25 with high purity. Thus, the surface diffusion property and fluidity of the film 25 which is heated through laser irradiation at the time of embedding to the hole 23 can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a pure copper wiring in a semiconductor device such as an ultra-high-speed device. It also relates to the formation of pure copper interconnects in semiconductor devices that can be used as certain primary devices, such as intelligent power devices (IPDs) that can be used in automobiles and other products.

[0002]

2. Description of the Related Art Generally, in a semiconductor device, when a wiring is made thinner, an operating speed is reduced as a result of an increase in wiring resistance. Attempts have been made to form wiring in ultra-high-speed devices by using Cu as a wiring material, which has lower electric resistance than a commonly used Al alloy.

Conventionally, wiring has been formed by reactive ion etching (RIE) using a resist as a mask material.
In the case of this method, a gas containing fluorine, chlorine, bromine, or the like is excited in plasma to etch Al in a halide form.

However, since Cu has a lower vapor pressure as a halide than Al, if Cu is used to obtain a practical etching rate by the above-mentioned RIE method, it is necessary to obtain a sufficient etching rate.
A high temperature of at least 300C is required. For this reason, there have been various difficulties in realizing a chamber capable of withstanding high temperatures, improving compatibility between etching and anisotropy, and selecting a mask material.

[0005] As an attempt to overcome these difficulties, studies have been actively made on the application of Cu to buried interconnects without using the RIE method. FIG. 7 schematically shows the most general method for forming a buried interconnect made of Cu.

First, a groove 3 is formed in an interlayer insulating film 2 on a Si substrate 1 in accordance with a desired wiring pattern (see FIG. 1A). Subsequently, a Cu film 5 is formed on the insulating film 2 through an adhesive layer 4 for preventing diffusion of Cu into Si.
Is formed and the inside of the groove 3 is buried (FIGS. 2B and 2C).
reference).

After that, an excess Cu film 5 remaining in a place other than the groove 3 is removed by a chemical mechanical polishing (CMP) method to form a buried wiring 6 of Cu (see FIG. 1D). ).

[0008] Now, in such a method of forming a buried wiring of Cu, together with the CMP technique, it is important and
What is very difficult is a technique for filling the groove 3 with Cu.

As a technique for embedding Cu, for example, a method of similarly depositing and embedding Cu on the side and bottom surfaces of a groove by a vapor phase growth (CVD) method, and a method of heat-treating Cu deposited by a sputtering method. This can be roughly divided into two methods of embedding in the groove.

However, the embedding of Cu using the CVD method is still largely unknown from a technical point of view such as mass production, and the embedding of Cu using the sputtering method is expected as the first mass production technique. .

As a method of heat treatment, there are a method of heating a Si substrate during Cu sputtering and a method of heating Cu deposited by sputtering.

The latter method of heating Cu after sputtering includes a heating furnace method in which the Si substrate is entirely heated within a certain time using a heating furnace, and a method in which Cu is reduced to Cu for an extremely short time of 1 millisecond or less. It is further classified into a laser irradiation method of irradiating a wavelength laser to heat Cu to a higher temperature than in a heating furnace method.

However, none of the above-mentioned methods has achieved the Cu filling property required for application to the next generation ultra-high-speed device having fine contact holes and the like.

FIG. 8 schematically shows a method for forming fine contact holes using Cu. First, a connection hole 7 having a depth reaching the surface of the Si substrate 1 is formed in the interlayer insulating film 2 on the Si substrate 1 (see FIG. 1A). The connection hole 7 has an opening size of, for example, 0.35 mm in diameter and 1.0 mm in depth.

Next, an adhesive layer 4 having a thickness of about 10 nm is formed on the insulating film 2 and then about 1 m thick by a sputtering method.
An m-thick Cu film 5 is formed (see FIG. 3B). Then, the Cu film 5 is heated by laser irradiation to bury Cu in the connection holes 7 (see FIG. 3C).

Thereafter, by removing the excess Cu film 5 and the like remaining in places other than the connection holes 7 by the CMP method, fine contact holes 8 made of Cu are formed (see FIG. 4D).

However, the thus formed Cu
The fine contact hole 8 has a problem that voids 9 are easily generated. This is because it is difficult to completely bury the inside of the connection hole having a high aspect ratio, which is the ratio of the depth to the diameter, due to the low burying property of Cu.

It has been confirmed that such voids 9 are reliably formed, for example, in the case of a connection hole having an aspect ratio of 1.25 or more, that is, a diameter of 0.8 mm or less with respect to a depth of 1.0 mm. ing.

As a result, the generation of the void 9 partially increases the density of the current flowing in the vertical direction of the fine contact hole 8 at the time of device operation, and causes a reduction in reliability. As described above, since the burying property of Cu is not sufficient, unfortunately, application of the buried wiring of Cu to the next-generation ultra-high-speed device has not been realized.

[0020]

As described above, it has been difficult to apply Cu-embedded wiring to next-generation ultra-high-speed devices because of insufficient Cu-embedding properties. Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device which can improve the burying property of Cu and can apply buried wiring using Cu to next-generation ultra-high-speed devices.

[0021]

In order to achieve the above-mentioned object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming an embedded wiring in an insulating film on a semiconductor substrate; Type wiring, oxygen concentration is 3pp
m or less using high-purity Cu.

In the method of manufacturing a semiconductor device according to the present invention, a step of forming a concave portion for forming a wiring in an insulating film on a semiconductor substrate is provided. Oxygen concentration is 3 through the barrier metal layer.
ppm or less, a step of forming a high-purity Cu film, a step of heat-treating the Cu film and embedding it in the recess, and removing an unnecessary Cu film remaining on the surface of the insulating film excluding the inside of the recess. Process.

Further, preferred embodiments of the method of manufacturing a semiconductor device according to the present invention include the following. (1) A step of forming a barrier layer including a first layer and a second layer in a recess provided in the insulating film is provided. (2) In manufacturing a semiconductor device, using a process chamber of two separate vacuum systems, allocating a first chamber in a first vacuum system for sputtering, and chemically depositing a second chamber in the first vacuum system. Allocating a third chamber in the second vacuum system for Cu or metal filling.

According to the method of manufacturing a semiconductor device of the present invention, it is possible to promote the surface diffusivity and fluidity of Cu. This makes it possible to satisfactorily bury Cu even in a fine concave portion in which a void has conventionally been generated.

In addition, the combination of high-purity Cu and a barrier layer makes it possible to use a lower-power laser, lower the annealing temperature, and perform high-temperature Cu sputtering.
The barrier layer can be formed from a double layer structure with characteristic properties, for example, Ti and TiN. It is also possible to employ other single or double layer structures with similar properties.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a sputtering apparatus according to an embodiment of the present invention.

This sputtering apparatus forms a Cu film on a Si substrate by a DC magnetron sputtering method or the like. For example, a sputtering chamber 11, a gas supply source 12, a gas purifier 13, and a DC power supply 14 Is configured.

In the sputtering chamber 11, the ultimate degree of vacuum is set to an ultra-high vacuum region (for example, 2 × 10 ⁻⁷ P).
The structure can be evacuated to a) and the penetration of oxygen and moisture during sputtering can be minimized.

The gas supply source 12 stores a sputtering gas to be supplied into the sputtering chamber 11. As the sputtering gas, 99.
Ar with a high level of purity of 9999% is used.

The gas purifier 13 is provided immediately before the gas inlet of the sputtering chamber 11 and limits the oxygen concentration and the moisture concentration of the sputtering gas from the gas supply source 12 in Ar at the point of use. For example, if the oxygen concentration is 0.1 ppb (parts-per-billion)
In addition, the water concentration is reduced to 0.7 ppb).

The DC power supply 14 is used for supplying power to the holder 11 in the sputtering chamber 11 during sputtering.
A positive voltage is applied to the Si substrate 21 held on the substrate a, and a negative voltage is applied to the Cu target 15 as a target material.

The Cu target 15 has 99.99
Materials having a high level of purity of 99% and having a low oxygen concentration (for example, an oxygen concentration of 0.1 ppm (parts-per-
million)) and a sulfur concentration of about 0.05 ppm).

The Cu film formed using the sputtering apparatus having such a configuration under the above-described film forming conditions has an oxygen concentration in the Cu film of about 0.5 ppm (for example, 0.1 ppm).
2 to 0.8 ppm) and a sulfur concentration of about 0.06 ppm (for example, 0.02 to 0.08 ppm).

Next, a method for forming a buried wiring using a Cu film, which is formed by using the above-described sputtering apparatus, will be described. FIG. 2 schematically shows a method of forming a fine contact hole as an example.

First, the interlayer insulating film 22 on the Si substrate 21
Then, a connection hole (recess) 23 having a depth reaching the surface of the Si substrate 21 is formed (see FIG. 3A). This connection hole 2
3 has an opening size of, for example, 0.35 mm in diameter,
The depth is 1.0 mm.

Next, a CVD-TiN (barrier metal layer) film 24 as an adhesive layer is formed on the insulating film 22 by 10 n.
m, and then DC under the above film forming conditions
About 1 μm thick Cu by magnetron sputtering
A film 25 is formed (see FIG. 3B).

That is, by preparing a chamber 11 capable of controlling a high-purity atmosphere and forming a Cu film 25 using a high-purity Cu target 15, an oxygen concentration of 0.5
A high-purity Cu film 25 having a sulfur concentration of about 0.06 ppm or less at a ppm level or less is formed.

Then, the Cu film 25 is heated by laser irradiation to completely fill the inside of the connection hole 23 (see FIG. 3C). In this case, the high-purity Cu film 25 has a low oxygen concentration and a low sulfur concentration.
The surface diffusivity and fluidity of u are promoted. As a result, the Cu filling property is improved, so that the inside of the connection hole 23 can be completely filled with the Cu film 25.

Thereafter, by removing the unnecessary (unnecessary) Cu film 25 and the like remaining in places other than the connection holes 23 by the CMP method, a fine contact hole 26 made of Cu without voids is formed. FIG. (D)).

As described above, by controlling the oxygen concentration and the sulfur concentration in the Cu film 25, the Cu is also formed in the fine connection hole 23 having an aspect ratio of 1.25 or more, in which a void has been generated conventionally. Can be reliably embedded.

Therefore, the fine contact hole 26 made of Cu can be obtained without voids, and it can be easily applied to the next-generation ultrahigh-speed device. FIG. 3 illustrates the dependence of void generation on the aspect ratio (correlation between void formation and aspect ratio).

FIG. 3A shows a high-purity Cu film having a thickness of 1 mm (the average oxygen concentration is 0.5 ppm,
The average sulfur concentration is 0.06 ppm), oxygen is implanted by changing the acceleration energy by the ion implantation method, and the contained average oxygen concentration is 1 ppm, 2 ppm, 3 ppm, and 4 ppm, respectively.
Each of the Cu films having pm and 5 ppm was heat-treated by laser irradiation to have a hole depth of 1.0 mm and hole diameters of 0.1 mm, 0.2 mm, and 0.35 m, respectively.
This is a result of observing the generation of voids in the sample holes when the sample holes are buried in the sample holes of m, 0.5 mm, and 0.65 mm by SEM (scanning electron microscope).

Similarly, FIG. 2B shows that a high-purity Cu film formed to a thickness of 1 mm is implanted with sulfur by changing the acceleration energy by an ion implantation method, and the average sulfur concentration is 1 ppm. Each of the Cu films of 2, 3 ppm, 4 ppm, and 5 ppm was subjected to heat treatment by laser irradiation to have a hole depth of 1.0 mm and hole diameters of 0.1 mm, 0.2 mm, 0.35 mm, and 0 mm, respectively. .
This is a result of observing the occurrence of voids in the sample holes when the sample holes are buried in the sample holes of 5 mm and 0.65 mm by SEM.

As is clear from these figures, when the hole diameter is 0.2 mm or more, that is, the aspect ratio is 5.0 or less, the oxygen concentration and the sulfur concentration in the Cu film are 3 ppm.
At or below this, no voids are observed and the inside of the hole is reliably filled with Cu (see circles in the figure).

On the other hand, when the oxygen concentration and the sulfur concentration are 4
Above ppm, voids were observed regardless of the aspect ratio (see x in the figure). When the hole diameter was 0.1 mm, that is, when the aspect ratio was 10.0, voids were observed regardless of the oxygen concentration and the sulfur concentration. However, this is considered to be the result of factors completely different from the oxygen concentration and the sulfur concentration in the Cu film, such as the limit of film formation in a fine hole by the sputtering method, becoming dominant.

As described above, by controlling the oxygen concentration and the sulfur concentration in the Cu film to be 3 ppm or less, the surface diffusivity and fluidity of Cu can be promoted, and the aspect ratio becomes 5.0.
The following connection holes can be filled with Cu without voids.

That is, in the above-described embodiment, the oxygen concentration and the sulfur concentration in the Cu film formed by the sputtering method are controlled. This allows
Since the heat treatment improves the surface diffusivity and fluidity of the Cu film, it is possible to reliably bury Cu even in a fine connection hole having a high aspect ratio where a void has conventionally been generated. Therefore, the burying property of Cu is greatly improved, and it is possible to easily apply the buried wiring of Cu to a next-generation ultra-high-speed device having fine contact holes and the like.

In the above-described embodiment of the present invention, a case has been described in which Cu is heat-treated by a method using laser irradiation so as to be embedded in the connection hole. However, the present invention is not limited to this. The same effect can be obtained by a method of sometimes embedding the Si substrate by heating, or a heating furnace method of heat-treating the Cu after sputtering together with the Si substrate.

Further, the present invention is not limited to embedding Cu in a wiring connection hole for forming a contact hole connecting a substrate and a wiring. For example, a connection hole for forming a through hole or a via hole for connecting wirings to each other. It can also be applied to embedding Cu in the (through hole).

Further, the present invention can be similarly applied to embedding in a groove for embedding wiring or embedding in a recess having a dual damascene structure including a groove and a connection hole. Furthermore, a high-purity Cu film can be formed by a sputtering apparatus other than the DC magnetron sputtering method.

FIG. 4 schematically shows a multi-chamber sputtering CVD apparatus according to another embodiment of the present invention. FIG. 2A shows a pre-processing step of Cu sputtering by the first sputtering apparatus.

First, a Ti layer (first layer) having a thickness of about 10 nm is formed in the chamber 31 by sputtering (processing (1)). Next, in the chamber 32, about 10 nm
(Second layer) is formed by chemical vapor deposition (processing (2)).

The chambers 33 and 34 are called “load lock” chambers, and are used for loading and unloading (processing (3)) a wafer for processing in the chambers 31 and 32. For example, when a group of wafers is first loaded into chamber 31, chamber 31 is locked and the interior of the sputtering apparatus is evacuated. While the wafers in the chamber 31 are still being processed, the already processed wafers in the chamber 32 can be replaced with a new set of wafers to be processed.

FIG. 4B shows the final step of Cu sputtering by the second sputtering apparatus. Cu is sputtered in the chamber 32 '(process (1)). The wafer is then removed from the chamber 33 '.
Transported to

If the sputtering (processing (1)) in the chamber 32 'is high-temperature Cu sputtering, the high-purity Cu film is effectively annealed during the sputtering, so that the high-purity Cu film is used. No additional heat treatment is required to obtain However, even if high-temperature Cu sputtering is performed, it is desirable to perform further annealing or laser processing in order to obtain a higher-purity Cu film.

If the sputtering (processing (1)) in the chamber 32 'is not high-temperature sputtering, Cu must be separately heat-treated by annealing or laser irradiation. In that case, for example, if the wavelength is 30
Xe-C with 5 nm, output 1.5-2.5 J / cm ²
An l-type excimer laser can be used.

In the case of the Ti layer / TiN layer, the lower Ti layer has a lower resistivity, and the upper TiN layer has a lower oxidation rate. Since the oxidation rate of the upper TiN layer is low, the wafer can be transferred between the sputtering apparatuses.

That is, since the oxidation rate of the TiN layer is low, the formation of the barrier layer (Ti layer / TiN layer) by the first sputtering apparatus and the formation of the high-purity Cu film by the second sputtering apparatus are required. This is made possible by transporting the wafer between different sputtering devices.

FIG. 5 shows the structure of a semiconductor device formed by the apparatus having the structure shown in FIG. The semiconductor device includes an SiO ₂ layer 39, an interlayer insulating film 40, a T
i layer 41, TiN layer 42, and high-purity Cu film 43
Consists of The thickness of the Ti layer 41 is, for example, 5 to 20 nm. The thickness of the TiN layer 42 is, for example, 5 to 15 nm.

The structure shown is in the same processing stage as that shown in FIG. High purity C in the recess
In order to bury the u film 43, this structure requires a further heat treatment, for example, by laser irradiation or annealing. However, if high-temperature Cu sputtering is used to form the high-purity Cu film 43, Cu is automatically embedded in the concave portion during sputtering.

FIG. 6 shows an alternative structure of the semiconductor device shown in FIG. Here, a semiconductor device having a structure having no sidewall by the Ti layer 41 is shown as an example.

In this case, the Ti layer 41 is composed of the SiO ₂ layer 39
And plays a role as a barrier to the high-purity Cu film 43. The barrier layer must have certain general properties. That is, when the barrier layer has a double layer structure of the first layer and the second layer, the first layer must have low resistivity. The second layer must have the property of preventing the diffusion of Cu and have a low oxidation rate.

For example, the first layer and the second layer are not limited to the Ti layer / TiN layer, but may be made of TiN. In this case, the concentration of N in the first TiN layer must be 0 or more, and must be lower than the concentration of N in the second TiN layer.

Further, TiSiN can be used for each of the first layer and the second layer. In this case, the concentration of Si in the first TiSiN layer must be 0 or more, and must be lower than the concentration of Si in the second TiSiN layer. In this case, the first layer T
The concentration of N in the iSiN layer must be 0 or more, and must be lower than the concentration of N in the TiSiN layer of the second layer.

Further, when Ti is used for the first layer, TiSiN is used instead of TiN for the second layer.
Can also be used. If Ti or W is used as the first layer, WSiN can be used as the second layer.

In addition, as the barrier layer, for example, oxide, nitride, silicon oxynitride, silicon carbide, Mo, MoN, Ta, TaN, W, WN, V, V
It can be configured using N, Nb, NbN, Ti, TiN, or the like.

High purity Cu films can be used with single or double barrier structures. In general, any single or double barrier structure having a similar high resistivity can be employed.

As described above, the present invention enables a heat treatment at a lower annealing temperature than generally required by the prior art by using a high-purity Cu film. For example, in the case of a general prior art, an annealing temperature of 450 ° C. to 600 ° C. is required, whereas in the case of the present invention, 380 ° C.
Heat treatment at an annealing temperature in the range of ５550 ° C. becomes possible.

In the case of the prior art using an excimer laser together with impure Cu, the evaporation of Cu frequently occurs. In the case of the present invention, a low-power laser which does not cause evaporation of Cu can be used. Becomes

Further, in the present invention, the relationship between the aspect ratio and the oxygen concentration in the high-purity Cu film is preferably defined by the following equation. Zo × AR ≦ 13 Here, Zo is the oxygen concentration in ppm, and AR is the aspect ratio.

The Cu embedded wiring technology of the present invention can be similarly applied to other high aspect ratio structures. Of course, various modifications can be made without departing from the scope of the present invention.

[0072]

As described above in detail, according to the present invention, the embedding property of Cu can be improved, and the embedding wiring using Cu can be applied to a next-generation ultra-high-speed device. A manufacturing method can be provided.

[Brief description of the drawings]

FIG. 1 is a configuration diagram schematically showing a sputtering apparatus according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view similarly illustrating a method of forming a fine contact hole by way of example.

FIG. 3 is a schematic diagram showing the dependence of generation of voids on the aspect ratio.

FIG. 4 is a schematic view showing a sputtering apparatus according to another embodiment of the present invention.

FIG. 5 is a schematic sectional view of a main part showing the structure of the semiconductor device.

FIG. 6 is a schematic cross-sectional view of a main part showing another structure of the semiconductor device.

FIG. 7 is a schematic cross-sectional view showing a typical method of forming a buried wiring of Cu in order to explain a conventional technique and its problems.

FIG. 8 is a schematic cross-sectional view showing a conventional method for forming a fine contact hole using Cu.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Sputtering chamber 11a ... Holder part 12 ... Gas supply source 13 ... Gas purifier 14 ... DC power supply 15 ... Cu target 21 ... Si substrate 22 ... Interlayer insulating film 23 ... Connection hole 24 ... CVD-TiN film 25 ... Cu film 26 ... fine contact holes 31, 32, 33, 34 ... chamber (first sputtering apparatus) 31 ', 32', 33 ', 34' ... chamber (second sputtering apparatus) 39 ... SiO ₂ layer 40 ... interlayer insulation film 41 ... Ti layer 42 ... TiN layer 43 ... High purity Cu film

Claims (10)

[Claims] 1. A method of manufacturing a semiconductor device, wherein an embedded wiring is formed in an insulating film on a semiconductor substrate, wherein the embedded wiring has an oxygen concentration of 3 ppm or less.
A method for manufacturing a semiconductor device, wherein the method is formed using high-purity Cu. 2. The Cu used for forming the wiring has a sulfur concentration of 3 ppm or less.
13. The method for manufacturing a semiconductor device according to item 5. 3. The method according to claim 1, wherein Cu used for forming the wiring is buried in a recess formed in the insulating film by heating by laser irradiation. 4. The semiconductor device according to claim 1, wherein excess Cu among Cu used for forming the wiring is removed from a surface of the insulating film by polishing by CMP. Method. 5. A step of forming a concave portion for forming a wiring in an insulating film on a semiconductor substrate; and forming an oxygen concentration of 3 ppm or less via a barrier metal layer on a surface of the insulating film in which the concave portion is formed. High purity C
forming a u film; heat treating the Cu film to bury the Cu film in the concave portion; and removing unnecessary Cu remaining on the surface of the insulating film except for the inside of the concave portion.
A method of manufacturing a semiconductor device, comprising: removing a film. 6. The Cu film embedded in the recess has a sulfur concentration of 3 ppm or less.
13. The method for manufacturing a semiconductor device according to item 5. 7. The method according to claim 5, wherein the heat treatment of the Cu film is performed by laser irradiation. 8. The method according to claim 5, wherein the removal of the unnecessary Cu film is performed by CMP. 9. The method according to claim 3, wherein the recess is a wiring groove. 10. The method according to claim 3, wherein the recess is a wiring connection hole.