JPH10153760A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a large screen size or high resolution without increasing the frame size and manufacture cost unnecessarily. SOLUTION: The liquid crystal display device is equipped with a liquid crystal panel, which has scanning lines and signal lines, and a display control circuit, which selects one line of liquid crystal pixels through each scanning line and controls the voltage of liquid crystal pixels in a selected line through signal lines, and the display control circuit includes a signal line driver, which drives those signal lines in order, and the signal line driver has driver ICs 1 which supply pixel data signals to a specific number of signal lines in synchronism with respective clock signals cascaded by a crossover transmitting clock signals and pixel data signals. Specially, each driver IC 1 has a duty cycle regulator 6, which shapes the clock signal waveform by adjusting the duty ratio of the clock signal outputted to a trailing stage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device in which a plurality of liquid crystal pixels are arranged in a matrix, and more particularly to a driving circuit for controlling the voltage of these liquid crystal pixels for displaying an image.

[0002]

2. Description of the Related Art Generally, an active matrix type liquid crystal display device has a liquid crystal panel in which a liquid crystal layer is held between an array substrate and a counter substrate. Each of the array substrate and the counter substrate is formed based on a transparent glass plate, and the liquid crystal layer is formed of a liquid crystal composition filled in a gap between the array substrate and the counter substrate. The array substrate includes a matrix array of a plurality of pixel electrodes, a plurality of scanning lines respectively formed along the rows of the pixel electrodes, a plurality of signal lines respectively formed along the columns of the pixel electrodes, A plurality of thin film transistors (TFTs) formed near the intersections of the scanning lines and the signal lines, each functioning as a switching element for electrically connecting one signal line to one pixel electrode in response to a selection signal from one scanning line; , A scanning line driver supplying a selection signal to each of the plurality of scanning lines, and a signal line driver supplying a pixel data signal to the plurality of signal lines. In this liquid crystal display device, an image is displayed corresponding to the potential difference between the pixel electrode and the common electrode.

For example, a signal line driver is composed of a plurality of driver ICs arranged as shown in FIG. These driver ICs include a power supply line VDD, a power supply line GND,
It is connected to a common bus line including the data line DATA and the control signal line CNT, and is arranged on the driver board adjacent to the outer periphery of the liquid crystal panel together with the common bus line.

In the liquid crystal display device having the above-described driver substrate, it is necessary to increase the frame size of the liquid crystal panel in order to obtain a larger screen size or higher resolution. For this reason, COG (Chip On)
Glass) mounting technology has been proposed to eliminate the need for a driver substrate. In this technique, thin-film wiring is formed in contact with connection terminals exposed on the glass surface of the array substrate, and bare chips of a plurality of driver ICs are soldered to the thin-film wiring.

[0005]

However, the thin film wiring formed by the current COG mounting technology has a relatively high resistance value, so that it is difficult to reduce the width of the wiring. This causes an increase in the frame size of the liquid crystal panel. Further, in manufacturing a liquid crystal panel, generally, a plurality of array substrates are manufactured from one glass plate. That is, the circuit components of each array substrate are formed in one area obtained by dividing this glass plate. When all the thin film wirings are arranged in the array substrate, the area occupied by each array substrate increases, and a larger glass plate is required. In other words, the number of array substrates obtained from one glass plate is reduced. This results in an increase in the manufacturing cost of the liquid crystal panel. Although it is conceivable to form only a thin film wiring corresponding to the common bus line on an external printed wiring board, the use of this printed wiring board may increase the manufacturing cost. For example, if the common bus line becomes longer,
This increases the parasitic capacitance that dulls the waveform of the transmission signal, making high-speed signal transmission difficult. Further, unnecessary radio waves are easily radiated from the common bus line on the printed wiring board. Therefore, it is necessary to additionally provide a shield layer or a terminating resistor in order to reduce the radiation of the unnecessary radio wave.

In order to prevent an increase in frame size and manufacturing cost, a plurality of driver ICs may be formed on an array substrate by COG mounting technology, and a thin film of wiring may be formed between the driver ICs. The crossover wiring connects these driver ICs in cascade, and each driver IC
The signal is transmitted via. However, with such a configuration, only a low signal transmission speed with a clock frequency of about 5 MHz can be obtained. According to the experiment, the pulse width of the clock signal is reduced by 40 ns at the worst every time the clock signal passes through one driver IC. Therefore, to ensure normal signal transmission,
The number of cascaded driver ICs must be limited to a maximum of about ten.

An object of the present invention is to provide a liquid crystal display device capable of obtaining a larger screen size or higher resolution without unnecessarily increasing the frame size and manufacturing cost.

[0008]

According to the present invention, a matrix array of a plurality of liquid crystal pixels, a plurality of scanning lines formed along rows of the liquid crystal pixels, and a plurality of scanning lines formed along a column of the liquid crystal pixels. A liquid crystal panel having a plurality of signal lines, and a drive circuit for selecting one row of liquid crystal pixels via each of the scanning lines and controlling the voltage of the selected row of liquid crystal pixels via the plurality of signal lines. The driving circuit includes a signal line driver for sequentially driving a plurality of signal lines, and the signal line driver is cascaded by a crossover wire for transmitting at least a clock signal and a display signal, and sequentially outputs the display signal in synchronization with each clock signal. It has a plurality of driver ICs for supplying a predetermined number of signal lines, and each driver IC adjusts the duty ratio of the clock signal output to the next stage together with the display signal. The liquid crystal display device having a clock waveform shaping circuit for shaping the lock signal waveform is provided.

In this liquid crystal display device, the clock waveform shaping circuit of each driver IC shapes the clock signal waveform by adjusting the duty ratio of the clock signal.
Transmission capacity can be maintained regardless of the increase in the number of driver ICs. For example, when a plurality of driver ICs are incorporated into a liquid crystal panel by COG mounting and are cascaded by high-resistance thin film crossover wiring, the width of the crossover wiring is kept narrow so as not to unnecessarily increase the frame size and manufacturing cost of the liquid crystal panel Even so, normal signal transmission becomes possible.

More specifically, the liquid crystal display device can obtain a high signal transmission rate with a clock frequency of about 25 MHz to 65 MHz. Therefore, ten or more driver ICs can be cascaded to obtain a larger screen size or higher resolution.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An active matrix type liquid crystal display according to one embodiment of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows a planar structure of the liquid crystal display device 20. The liquid crystal display device 20 includes a liquid crystal panel 22 in which a liquid crystal layer is held between an array substrate and a counter substrate, and a display control circuit that controls a voltage of a liquid crystal pixel of the liquid crystal panel 20. Each of the array substrate and the counter substrate is formed based on a transparent glass plate, and the liquid crystal layer is formed of a liquid crystal composition filled in a gap between the array substrate and the counter substrate. The array substrate includes a matrix array of a plurality of pixel electrodes, a plurality of scanning lines respectively formed along the rows of the pixel electrodes, a plurality of signal lines respectively formed along the columns of the pixel electrodes, A plurality of thin film transistors (TFTs) each formed near the intersection of the scanning line and the signal line and functioning as a switching element; Each TFT has a gate connected to one scanning line, a current path connected to one signal line and one pixel electrode,
It is used to electrically connect a signal line to a pixel electrode in response to a selection signal from a scanning line. The display control circuit receives an interface unit 25 for inputting a power supply voltage, a pixel data signal, a clock signal, and other control signals supplied from an external liquid crystal controller, and a power supply voltage and a control signal from the interface unit 25. A scanning line driver 24 that performs an operation of sequentially supplying a selection signal to a plurality of scanning lines under a power supply voltage under the control of And a pair of signal line drivers 23 that perform an operation of sequentially supplying a pixel data signal to a plurality of signal lines in synchronization with a clock signal under control of a control signal under a power supply voltage. These drivers 23 and 24 are formed on a driver substrate arranged adjacent to the outer periphery of the liquid crystal panel 22. The scanning line driver 24 is connected to a plurality of scanning lines, and the pair of signal line drivers 23 are connected to odd-numbered signal lines and even-numbered signal lines, respectively. In this liquid crystal display device, an image is displayed corresponding to a potential difference between a plurality of pixel electrodes and a common electrode facing each other via a liquid crystal layer in order to form a matrix array of liquid crystal pixels.

FIG. 2 schematically shows the structure of the signal line driver 23. Each signal line driver 23 includes a plurality of driver ICs 1 arranged as shown in FIG. A plurality of driver ICs 1 are connected to a power supply line VD
D and the power supply line GND,
The semiconductor bare chips are cascade-connected by the crossover wiring 10 formed between the driver ICs 1. The crossover wiring 10 is used for transmitting a pixel data signal, a clock signal, and various control signals via each driver IC 1. Each driver IC 1 receives these signals via the input pad section 2 and supplies pixel data signals to a predetermined number of signal lines sequentially in synchronization with a clock signal under control of a control signal. These signals are waveform-shaped for output to the driver IC1.
Incidentally, the bare chips of the plurality of driver ICs 1 are covered with an insulating layer together with the power supply lines VDD and GND on the driver substrate.

FIG. 3 shows the configuration of each driver IC 1 in detail. The crossover wiring 10 includes a clock line CLK for transmitting a clock signal, a plurality of data lines DATA for transmitting a pixel data signal, and a plurality of control lines C for transmitting a control signal.
It is composed of NT. The driver IC1 has a clock line C
A first buffer amplifier 4 for amplifying a signal supplied to the input pad section via each of the LK, the data line DATA, and the control line CNT; and a first buffer amplifier for outputting a pixel data signal and a control signal output from the first buffer amplifier 4 to the first buffer amplifier. A first latch circuit for simultaneously latching in response to a clock signal output from the amplifier, a duty cycle regulator for adjusting a duty ratio of the clock signal output from the buffer amplifier, a first latch circuit;
The pixel data signal output from the first buffer amplifier 4
A control logic CT which sequentially supplies a predetermined number of signal lines to a predetermined number of signal lines in synchronization with a clock signal output from the first latch circuit 5, and converts a pixel data signal and a control signal output from the first latch circuit 5 into a clock signal output from the duty cycle regulator 6. A second latch circuit 7 for simultaneously latching in response to the pixel data signal and the control signal output from the second latch circuit 7 and a clock signal output from the duty cycle regulator 6 to be supplied to the output pad section 3 And a second buffer amplifier 8.

That is, the pixel data signal, the clock signal, and various control signals are supplied from the input pad section 3 to the inside of the driver IC 1 and are further distributed to two transmission paths. One transmission path is used for supplying these signals to the control logic CT, and the other transmission path is used for shaping these signals and supplying the output pad section 3 to the subsequent driver IC 1. For example, the control logic CT shifts a start pulse supplied as a control signal in synchronization with a clock signal, thereby sequentially selecting a predetermined number of signal lines, and a signal line selected by the shift register circuit as pixel data. And an output circuit for setting a voltage corresponding to the signal. The pixel data signal and the control signal are shaped by the latch circuits 5 and 7, and the clock signal is shaped by the duty cycle regulator 6. Latch circuit 5
In and 7, the pixel data signal and the control signal are latched based on the timing of the clock signal to repair signal distortion due to transmission. The duty cycle regulator 6 shapes the clock signal, for example, while following the threshold value to the average value of the voltage of the clock signal, and maintains the duty ratio of the clock signal at approximately 1: 1 to output the duty ratio to the next-stage driver IC 1. I do.

The duty cycle regulator 6 is formed using, for example, a PLL circuit as shown in FIG. This PLL circuit includes an edge operation frequency phase comparison circuit 6A, a low pass filter 6B, and a voltage controlled variable frequency oscillation circuit 6C. The edge operation frequency phase comparison circuit 6A receives the input clock signal from the buffer amplifier 4 and the oscillation circuit 6C.
And outputs an error voltage based on the phase difference. This error voltage is supplied to the oscillation circuit 6C via the low-pass filter 6B as a control voltage, and shifts the phase of the output clock signal.

The above-described voltage-controlled variable frequency oscillation circuit 6C includes a plurality of CMOs connected in series as shown in FIG.
Includes S inverter. These CMOS inverters are biased by the control voltage supplied from the low-pass filter 6B, and adjust the discharge current of the output terminals P1-P8, PF.
The output terminal PF of the last CMOS inverter including the OS transistor is connected to the input terminal of the first CMOS inverter to feed back the output clock signal. Thereby, all the CMOS transistors periodically output the output clock signal as shown in FIG.
Generated from PF. The phases of these output clock signals change at a constant rate following changes in the control voltage.

The duty cycle regulator 6 is constituted by using, for example, a DLL circuit as shown in FIG. This DLL circuit includes a 1/2 frequency divider 6F, an exclusive OR 6G, a voltage control delay 6H, a multiplication type phase comparator 6
I, and a low-pass filter 6J. The 分 frequency dividing circuit 6F divides the frequency of the input clock signal from the buffer amplifier 4 by 、 and supplies it to the exclusive OR 6G, the voltage control delay circuit 6H, and the multiplication type phase comparison circuit 6I. The delay circuit 6H delays the clock signal from the frequency divider 6F,
It is supplied to the phase comparison circuit 6I and the exclusive OR 6G.
The phase comparison circuit 6I compares the clock signal from the frequency dividing circuit 6F with the clock signal from the delay circuit 6H, and generates an error voltage based on the phase difference. This error voltage is supplied to the delay circuit 6H via the low-pass filter 6J as a control voltage for increasing or decreasing the delay time. The exclusive OR 6G generates an output clock signal corresponding to the exclusive OR of the clock signal from the frequency divider 6F and the clock signal from the delay circuit 6H.

The voltage control delay circuit 6H includes, for example, a plurality of CMOS inverters connected in series as shown in FIG. These CMOS inverters are low-pass filters 6J
And a MOS transistor biased by a control voltage supplied from the divider circuit to adjust the discharge current at each output terminal.
It is supplied to the input terminal of the MOS inverter. This allows
All CMOS transistors periodically generate output clock signals from their respective output terminals. The phases of these output clock signals change at a constant rate following changes in the control voltage.

In the DLL circuit described above, FIG. 9 shows the 1/2 frequency divider 6F, the exclusive OR 6G, the voltage control delay circuit 6H, the multiplication type phase comparator 6I, and the outputs S1-S6 of the low-pass filter 6J. To change. As a result,
The duty ratio of the clock signal is maintained at approximately 1: 1 and output to the driver IC 1 at the next stage.

According to the liquid crystal display device of the present embodiment, the timing of the clock signal is optimized while the distortion of the pixel data signal is reduced, so that the signal transmission capability can be maintained regardless of the increase in the number of driver ICs 1. Can be. Also,
Since the liquid crystal display device transmits pixel data signals, clock signals, and various control signals using the crossover wiring 10, the wiring area required for signal transmission can be reduced. Therefore, a larger screen size or higher resolution can be obtained without unnecessarily increasing the frame size and manufacturing cost.

In the above embodiment, the signal line driver 2
3 are formed on the outer periphery of the array substrate 9 by the COG mounting technique as shown in FIG.
0 thin film can also be formed. The crossover wiring 10 cascade-connects these driver ICs 1 and transmits a pixel data signal, a clock signal, and various control signals via each driver IC1. In this case, the liquid crystal display device can obtain a high signal transmission speed with a clock frequency of about 25 MHz to 65 MHz. Therefore, to obtain a larger screen size or higher resolution,
More than one driver IC can be cascaded.

The crossover wiring may be applied not only to the signal line driver 23 but also to the scanning line driver 24. Further, in the above-described embodiment, the power supply line VD
Although only the power supply voltage commonly supplied to the circuit components of the driver IC 1 via D and GND has been described, in practice, in addition to this common power supply voltage, a pixel electrode driving power supply voltage corresponding to the pixel data signal and A reference power supply voltage for the common electrode is also required.

If the voltage drop due to the external dimensions of the liquid crystal panel 20 and the wiring resistance is relatively small, the transition wiring 10
However, the present invention can also be applied to a power supply line for supplying these power supply voltages. In this case, as shown in FIG.
2 is added to each driver IC 1 together with the power input pad section 11 and the power output pad 13. Various power supply voltages are input to the driver IC 1 via the power supply input pad section 11, and the buffer amplifier 4, the latch circuit 5, the duty cycle regulator 6, the latch circuit 7, the buffer amplifier 8,
And to the voltage stabilizer 12 as well as to circuit components such as control logic CT. These power supply voltages are stabilized by the voltage stabilizing circuit 12, respectively.
It is output to the driver IC of the next stage through the power output pad. Incidentally, the voltage stabilizing circuit 12 described above is
C1 may be provided independently for each power supply voltage.

The above-mentioned voltage stabilizing circuit 12 is connected to each driver IC.
In addition, if the crossover wiring 10 is configured to include all power supply lines in addition to the signal lines for the clock signal, the pixel data signal, and other control signals after being incorporated in The wiring area of the signal driver 23 can be reduced as compared with the case where a bus line is used.

Further, a plurality of driver ICs 1 arrange the input pad section 2 and the power input pad section 11 on one short side, and the output pad section 3 and the power output pad section 13
Are arranged on the other short side and have a rectangular shape with an aspect ratio of 1: 5 or more, and are arranged on the outer periphery of the array substrate 9 as shown in FIG. Can be effectively reduced.

In FIG. 12, a plurality of transfer wiring chips 100 each having a transfer wiring 10 formed on a flexible resin film are arranged between a plurality of driver ICs 1, and these driver ICs 1 are mounted on the transfer wiring chip 100. Cascade connection is performed by the crossover wiring 10.

If the voltage drop due to the external dimensions of the liquid crystal panel 20 and the wiring resistance is relatively large, only the driving power supply voltage for the pixel electrode and the reference power supply voltage for the common electrode are applied to each driver IC using an external common bus line. What is necessary is just to supply directly. Even in such a case, the number of external common bus lines is reduced. That is, since many areas are not occupied by the common bus line, an increase in frame size can be suppressed.

In the above modification, the signal line driver IC 1
Are configured to transmit signals without using external bus lines as much as possible. When a plurality of driver ICs 1 are connected in cascade by crossover wiring, the transmission signal is distorted every time it passes through each driver IC 1. This distortion is eliminated by shaping the transmission signal waveform in each driver. Therefore, the number of driver ICs 1 is not restricted by the distortion generated in the transmission signal.

Further, the voltage stabilizing circuit 12 is connected to each driver IC.
1 to stably maintain the power supply voltage against voltage fluctuations caused by external factors of the driver IC1 and voltage fluctuations generated by the internal load of the driver IC1. This allows
As for the supply of the power supply voltage, the wiring can be used instead of the common bus line.

[0030]

According to the present invention, a larger screen size or higher resolution can be obtained without unnecessarily increasing the frame size and manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing an active matrix liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram schematically showing a structure of a signal line driver shown in FIG. 1;

FIG. 3 is a circuit diagram showing a configuration of each driver IC shown in FIG. 2 in detail.

FIG. 4 is a circuit diagram showing a configuration of a PLL circuit used as the duty cycle regulator shown in FIG.

FIG. 5 is a circuit diagram showing a configuration of a voltage-controlled variable frequency oscillation circuit shown in FIG.

FIG. 6 is a time chart illustrating an operation of the voltage controlled variable frequency oscillation circuit illustrated in FIG. 5;

FIG. 7 is a circuit diagram showing a configuration of a DLL circuit used as the duty cycle regulator shown in FIG. 5;

FIG. 8 is a circuit diagram showing a configuration of a voltage control delay circuit shown in FIG. 7;

FIG. 9 is a time chart illustrating an operation of the DLL circuit illustrated in FIG. 7;

10 is a perspective view showing a wiring state when the driver IC shown in FIG. 2 is mounted on an array substrate.

11 is a circuit diagram for explaining a voltage stabilizing circuit added to each driver IC when the crossover wiring shown in FIG. 2 is also applied to a power supply line.

FIG. 12 shows a driver I having the voltage stabilizing circuit shown in FIG.
It is a perspective view which shows the wiring state when C is mounted on an array board.

FIG. 13 is a block diagram schematically showing a structure of a signal line driver of a conventional liquid crystal display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Driver IC 2 ... Input pad part 3 ... Output pad part 4 ... Buffer amplifier 5 ... Latch circuit 6 ... Duty cycle regulator 7 ... Latch circuit 8 ... Buffer amplifier 9 ... Array board 10 ... Transition wiring 22 ... Liquid crystal panel 23 ... Signal Wire driver CT ... Control logic

Claims (7)

[Claims] 1. A liquid crystal display device comprising: a matrix array of a plurality of liquid crystal pixels; a plurality of scanning lines formed along rows of the plurality of liquid crystal pixels; and a plurality of signal lines formed along a column of the plurality of liquid crystal pixels. A driving circuit for selecting one row of liquid crystal pixels via each of the plurality of scanning lines, and controlling the voltage of the liquid crystal pixels on the selected row via the plurality of signal lines. The circuit includes a signal line driver for sequentially driving the plurality of signal lines, and the signal line driver is cascaded by a crossover wire for transmitting at least a clock signal and a display signal, and sequentially supplies a predetermined number of display signals in synchronization with the clock signal. And a plurality of driver ICs for supplying a signal line to each of the driver ICs. The liquid crystal display device having a clock waveform shaping circuit for shaping the waveform. 2. The liquid crystal display device according to claim 1, wherein the liquid crystal panel has a glass plate on which the plurality of signal lines are formed, and the crossover wiring is formed on the glass plate. 3. The liquid crystal display device according to claim 2, wherein the plurality of driver ICs are semiconductor bare chips connected to the crossover wiring by the glass plate. 4. The liquid crystal according to claim 1, wherein the liquid crystal panel has a glass plate on which the plurality of signal lines are formed, and the crossover wiring is formed on a flexible substrate disposed on the glass plate. Display device. 5. The liquid crystal display device according to claim 1, wherein the clock waveform shaping circuit includes a duty cycle regulator for adjusting a duty ratio of a clock signal to 1: 1. 6. The duty cycle regulator includes a PLL.
2. The liquid crystal display device according to claim 1, which is configured by a circuit. 7. The duty cycle regulator may be a DLL.
2. The liquid crystal display device according to claim 1, which is configured by a circuit.