JPH10149946A - Method for manufacturing capacitor and substrate including capacitor - Google Patents

Abstract

(57) Abstract: Provided is a method of manufacturing a capacitor capable of forming a capacitor with an accurate capacitance value, and a substrate including the capacitor. SOLUTION: A plurality of rectangular extension portions 36a for adjusting a capacitance value formed of a Ti thin film layer are formed on the outer periphery of an upper electrode layer 50. Here, the capacitance value of the thin film capacitor is measured, and when exceeding the target value, some of the rectangular extending portions 36a are removed by etching, so that the capacitance value of the thin film capacitor can be easily adjusted. it can. For this reason, it becomes possible to manufacture a thin film capacitor having an accurate capacitance value by using the anodizing treatment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor using anodizing treatment and a substrate having the capacitor.

[0002]

2. Description of the Related Art When a capacitor is formed on a ceramic substrate or the like, for example, a Ta film layer is formed, and the upper portion of the Ta film layer is oxidized by an anodizing method or anodizing treatment to form tantalum oxide (TaO). , Ta ₂ O ₅ ) film to form a dielectric layer of the capacitor. Then, a conductive layer serving as an upper electrode is formed on the dielectric layer.

The formation of a dielectric by the anodic oxidation treatment will be described in more detail. First, a mask (resist) having a predetermined opening is provided in the Ta film layer, and the substrate on which the Ta film layer is formed is immersed in a chemical conversion solution of about 0.01% citric acid. By applying an electric potential so as to be positive, the Ta film layer exposed from the opening of the mask is subjected to anodizing treatment, and tantalum oxide is formed to a desired thickness, that is, a set thickness, thereby forming a dielectric. Form.

[0004]

However, the thickness of the dielectric cannot be adjusted with high accuracy, and it has been difficult to make the capacitance of such a capacitor constant. In the chemical conversion treatment, a current is not applied while measuring the thickness of the anodized layer, but a voltage-current is applied according to a preset profile so as to obtain a constant thickness. Therefore, if part of the current that should flow through the anodized layer leaks through other unnecessary parts,
Since the processing is terminated when the target amount of current is applied, the processing ends when the thickness of the anodic oxide layer is small.
That is, it is necessary to eliminate the leakage current in order to accurately make the thickness constant, but it is impossible to completely eliminate the leakage current even if the leakage current can be actually reduced. The thickness of the dielectric deviates from a target value depending on the magnitude of the current amount, and the capacitance value of the capacitor cannot be accurately kept constant.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method of manufacturing a capacitor capable of forming a capacitor with an accurate capacitance value and a substrate having the capacitor. It is in.

[0006]

According to a first aspect of the present invention, there is provided a method of manufacturing a capacitor, comprising the steps of: forming a lower electrode layer of the capacitor; and forming a dielectric layer on the lower electrode layer by anodizing. Forming a body layer; forming an upper electrode layer of the capacitor on the dielectric material, the upper electrode layer having a plurality of extended portions for capacitance adjustment on the outer periphery; Adjusting the capacitance value of the capacitor by removing some of the plurality of extended portions by etching.

According to a second aspect of the present invention, there is provided a method of manufacturing a capacitor, comprising: forming a lower electrode layer of the capacitor; forming a dielectric layer on the lower electrode layer by anodizing; Forming a thin film layer to be a part of the upper electrode of the capacitor, forming a remaining portion of the upper electrode on the thin film layer, and forming a plurality of extending portions for adjusting the capacitance value on the outer periphery of the remaining portion of the upper electrode. As a technical feature, the method includes a step of exposing the thin film layer and a step of adjusting a capacitance value of the capacitor by removing some of the plurality of extending portions by etching.

A substrate provided with a capacitor according to a third aspect of the present invention comprises a lower electrode layer, a dielectric layer formed on the lower electrode layer by anodization, and an upper electrode formed on the dielectric layer. And a thin film layer having a plurality of extended portions for adjusting the capacitance value on the outer periphery.

[Effects]

In the method of manufacturing a capacitor according to the first aspect, since a plurality of extending portions for adjusting the capacitance value are formed on the outer periphery of the upper electrode layer, some of the plurality of extending portions are removed by etching. By doing so, the capacitance value of the capacitor can be easily adjusted. Therefore, it is possible to manufacture a capacitor having an accurate capacitance value while using the anodizing treatment.

In the method of manufacturing a capacitor according to the second aspect, since a plurality of extended portions for adjusting the capacitance value formed of a thin film layer which is a part of the upper electrode are formed on the outer periphery of the upper electrode, a plurality of extended portions formed of the thin film layer are formed. By removing some of the extending portions by etching, the capacitance value of the capacitor can be easily adjusted. For this reason, it is possible to manufacture a capacitor having an accurate capacitance value by using the anodizing treatment. Also,
Since the plurality of extending portions are formed only of the thin film layers and there is no need to remove the entire upper electrode, the extending portions can be easily removed by etching.

[0011] In the substrate having the capacitor according to claim 3,
Since a plurality of extended portions for adjusting the capacitance value are formed on the outer periphery of the upper electrode layer, the capacitance value of the capacitor is easily adjusted by removing some of the extended portions by etching. be able to.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described below with reference to the drawings. Here, a process for forming a capacitor on the ceramic substrate 10 will be described with reference to FIGS. First, as shown in FIG. 1A, a Ti layer 20 having a thickness of 0.2 μm and a Cu layer 2 having a thickness of 0.5 μm
2 are formed by sputtering. This Ti layer 20
The Cu layer 22 serves as a plating base layer for forming the lower electrode of the capacitor by plating.

Next, after uniformly applying a photoresist on the ceramic substrate 10, the area around the lower electrode of the capacitor is exposed and developed to form an opening as shown in FIG. 1B. A resist 24 having 24a is formed. Subsequently, as shown in the step (C) of FIG. 1, the plating underlayer (Ti layer) 20 and the (Cu layer)
A current flows through the Cu plating layer 26 (14 μm).
m), a Ni plating layer 28 (0.2 μm) is formed, and a lower electrode layer 30 of a capacitor carrying a dielectric layer is formed. Thereafter, as shown in step (D) of FIG. 1, the resist 24 is removed. Then, as shown in the step (E) of FIG. 1, the Cu layer 22 other than the portion immediately below the Cu plating layer 26-Ni plating layer 28 is removed with an ammonia-based etching solution for Cu etching.

The formation of a capacitor will be described with reference to FIGS. 2 to 7
In each step, the cross section of the substrate is shown on the left side of the figure,
In addition, a plan view of the substrate is shown on the right side in the drawing. As shown in the step (F) of FIG. 2, the entire substrate including the Cu plating layer 26-Ni plating layer 28 is sputtered by sputtering.
A Ta layer 31 of μm is formed, and a lower electrode 30 composed of the Cu plating layer 26-Ni plating layer 28-Ta layer 31 is formed. When a TaN thin film resistor is present on the substrate, partial sputtering may be performed using a mask so that a Ta layer is not formed on the resistor. Next, as shown in step (G) of FIG. 2, a photoresist is uniformly applied, and then the area around the part to be a dielectric layer of the capacitor is exposed and developed, and as shown in step (G) of FIG. So that the opening 32a
Is formed.

Thereafter, the ceramic substrate 10 is immersed in a chemical conversion treatment solution of about 0.01% citric acid, and a potential is applied through the Ta layer 31 so that the Ta layer 31 side becomes positive. By flowing a predetermined amount of current based on the set current-voltage profile, the Ta layer 31 exposed from the opening 32a of the resist 32 is anodized by a predetermined thickness (0.5 to 0.6 μm). To tantalum oxide (TaO, Ta ₂ O ₅ ), and the step (H) of FIG.
A dielectric layer 35 is formed as shown in FIG. In this step (H), after forming the dielectric layer 35, the resist 32 is formed.
Is removed and the surface is cleaned with plasma.

Next, as shown in step (I) of FIG. 3, a 0.2 μm thick Ti layer 3 is formed on the ceramic substrate 10.
6 and a 0.5 μm Cu layer 38 are formed by sputtering. The Ti layer 36 and the Cu layer 38 are part of the upper electrode of the capacitor, and serve as a plating underlayer for plating. At the same time, the Ti layer 3
Reference numeral 6 is used for adjusting the capacitance value of the capacitor.

Next, after uniformly applying a photoresist to the ceramic substrate 10, the area around the upper electrode of the capacitor is exposed and developed, and as shown in step (J) of FIG. A resist 40 having 40a is formed. Subsequently, the plating underlayer (Ti
4) and (Cu layer) 38,
As shown in the step (K), the Cu plating layer 42 (2 μ
m) After forming the Ni plating layer 44 (1 μm), the resist 40 is removed. Thereafter, the Cu layer 38 is etched using the Ni plating layer 44 as a mask, and a resist layer is formed again in the same pattern as in the step (J).
An Au plating layer 46 (2 μm) is formed, and this resist layer is removed to form an upper electrode 50 (see step (L)).

Then, after a photoresist is applied to the ceramic substrate 10, as shown in a step (M) of FIG. 5, in addition to the square upper electrode layer 50, a capacitance adjustment is performed on the outer periphery of the upper electrode layer 50. The resist 52 is patterned so as to leave a rectangular extension portion 52a for use. Each of the rectangular extending portions 52a is, for example, a square upper electrode layer 5.
It is formed so as to be about 2% of the area of 0, and the capacity can be reduced to a maximum of 8% at the four rectangular extending portions 52a.

Then, as shown in step (N) of FIG.
The Ti sputter layer 36 in a portion other than immediately below the resist 52 is removed with a hydrofluoric acid-based etchant. This allows
Around the upper electrode layer 50 (Ti layer 36-Cu layer 38-Cu plating layer 42-Ni plating layer 44-Au plating layer 46), a Ti sputtering layer 36 (rectangular extending portion 36a) which is a part of the upper electrode is provided. ) Remains. Further, by removing the Ti sputtered layer 36 uniformly provided on the substrate surface, the lower electrode layer 30, the dielectric layer 35, and the upper electrode layer 50 are insulated from each other.

Here, the distance L1 from the outer periphery of the lower electrode layer 30 to the outer periphery of the dielectric layer 35 is about 0.1 mm, and from the outer periphery of the dielectric layer 35 to the outer periphery of the upper electrode layer 50. Is about 0.1 mm, and the length L3 of one side of the upper electrode layer 50 is about 0.2 mm. On the other hand,
The width L4 of the rectangular extending portion 36a is about 0.16 mm, and the extending length L5 is about 0.05 mm.

Next, the capacitor is covered with a resist having a pattern larger than the lower electrode 30 by about 30 μm on one side by applying, exposing, and developing a resist. Ta layer 3 on substrate 10 by RIE (reactive ion etching)
1 is removed, and the Ti layer 20 under the Ta layer 31 is further removed.
Is also removed with a nitric hydrofluoric acid-based etchant. This is preferable because the Ta layer 31 remains so as to cover the side surfaces of the Cu plating layer 26 and the Ni plating layer 28 of the lower electrode layer 30 (see step (O) in FIG. 6).

Here, since the capacitance of the capacitor depends on the area of the upper electrode, it is determined by the total area of the upper electrode layer 50 and the four rectangular extending portions 36a. For this reason, the capacitance value of the manufactured capacitor is measured, and what percentage is larger than the target value is measured. In this embodiment,
Since the capacitance is set to be larger than the target value in the above-described capacitor manufacturing stage, the measured capacitance value is always equal to or larger than the target value.

Next, the step of adjusting the capacitance value of the capacitor will be described with reference to FIG. Here, the description is continued on the assumption that the capacity is 4% larger than the target value in the above measurement. The rectangular extension 36 as described above
Since a is set at 2% for each, the capacitance value can be adjusted to the target value by removing two rectangular extending portions 36. Therefore, as shown in step (P) of FIG. 7, two rectangular extending portions 36a (left and lower sides in the figure) are exposed, and at least two rectangular extending portions 36a are exposed.
a (a right side and an upper side in the figure) is coated, exposed and developed with a photoresist to form a resist 54. In this example, the left and lower rectangular extending portions 36a in the figure are used.
The entire surface of the substrate was covered with a resist 54 such that only the substrate and its vicinity were exposed in a substantially L shape. Then, the resist 5
The Ti sputter layer 36 where no 4 is formed, that is, the left and lower rectangular extending portions 36a are removed by a hydrofluoric acid-based etchant to remove the resist 54.
By performing the adjustment so as to be 4% smaller in this way, it is possible to obtain the thin film capacitor 1 whose capacitance value is sufficiently close to the target value (step (Q)).

In this embodiment, twenty ceramic substrates 10 are formed by cutting one multi-piece worksheet. Here, since the influence of the leakage current is uniform in one worksheet, the thickness of the dielectric layer 35 formed on the 20 ceramic substrates 10 is substantially equal, and each of the dielectric layers 35 on the multi-piece worksheet is different. Are almost uniform in capacitance. For this reason, measure the capacitance of one capacitor,
As described above, when the value is larger than the target value by 4%, the capacity of all the capacitors on the worksheet for multiple mounting is reduced by 4%.
By performing the etching so as to decrease each time, the capacitance of all the capacitors can be adjusted. That is, in the present embodiment, since the etching can be performed for each worksheet, there is an advantage that the productivity is high.

In this embodiment, the upper electrode layer 50 (T
Around the i-sputtering layer 36-Cu-sputtering layer 38-Cu-plated layer 42-Ni-plated layer 44-Au-plated layer 46), a Ti-sputtered layer 36 (rectangularly extending portion 36a) serving as a part of the upper electrode is left. is there. In other words, it is sufficient to remove only a very thin one-layer rectangular extension portion 36a, so that it can be easily removed by etching using one kind of solution for metal (for Ti). The electrode layer 50 is hardly affected. Also,
Since the rectangular extending portion 36a is formed so as to protrude from the outer periphery of the upper electrode layer 50, the position of the resist pattern may be determined so that only the unnecessary rectangular extending portion 36a and the vicinity thereof are opened. That is, since it is not necessary to perform masking with high accuracy, formation of a resist pattern is easy.

In this embodiment, the upper electrode layer 5
Although the capacitance value was adjusted by removing only one layer of the Ti sputter layer 36 (rectangular extension portion 36a) disposed around 0 by etching, the configuration of the rectangular extension portion 36a was the same as that of the upper electrode layer 50. After the resist 54 is formed, the rectangular extending portion 36a may be removed by etching in the order of Au, Ni, Cu, and Ti.

In the above embodiment, the upper electrode layer 5
0 is a Ti layer 36, a Cu layer 38, a Cu plating layer 42, Ni
Although the upper electrode layer is composed of the plating layer 44 and the Au plating layer 46, for example, the upper electrode layer may be composed of, for example, a Cr-Ti-Cu-Ni-Au layer. Further, the upper electrode layer is formed of a Cr—Cu—Ni—Au layer,
-Pd-Au layer may be used. Where N
When removing i by etching, it is preferable to use an alkaline etching solution.

[Brief description of the drawings]

FIG. 1 is a process chart showing each step of a method for manufacturing a capacitor according to a first embodiment of the present invention.

FIG. 2 is a process chart showing each step of a method for manufacturing a capacitor according to the first embodiment of the present invention.

FIG. 3 is a process chart showing each step of a method for manufacturing a capacitor according to the first embodiment of the present invention.

FIG. 4 is a process chart showing each step of a method for manufacturing a capacitor according to the first embodiment of the present invention.

FIG. 5 is a process chart showing each step of a method for manufacturing a capacitor according to the first embodiment of the present invention.

FIG. 6 is a process chart showing each step of the method for manufacturing a capacitor according to the first embodiment of the present invention.

FIG. 7 is a process chart showing each step of the method for manufacturing a capacitor according to the first embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 ceramic substrate 30 lower electrode layer 31 Ta layer 35 dielectric layer 36 Ti layer 36a rectangular extending portion 50 upper electrode layer

Claims (3)

[Claims] A step of forming a lower electrode layer of the capacitor; a step of forming a dielectric layer on the lower electrode layer by anodization; and an upper electrode layer of the capacitor on the dielectric. Forming an upper electrode layer having a plurality of extended portions for adjusting the capacitance value on the outer periphery; removing some of the plurality of extended portions of the upper electrode layer by etching to reduce the capacitance value of the capacitor. Adjusting the capacitor. A step of forming a lower electrode layer of the capacitor; a step of forming a dielectric layer on the lower electrode layer by anodizing; a part of an upper electrode of the capacitor on the dielectric layer; Forming a thin film layer to be formed on the thin film layer, forming a remaining portion of the upper electrode on the thin film layer, and exposing the thin film layer as a plurality of extending portions for adjusting the capacitance value on the outer periphery of the remaining portion of the upper electrode. A method for manufacturing a capacitor, comprising: a step of adjusting a capacitance value of a capacitor by removing some of the plurality of extending portions by etching. 3. A lower electrode layer, a dielectric layer formed on the lower electrode layer by anodization, and a thin film layer formed on the dielectric layer and serving as a part of an upper electrode. A thin film layer having a plurality of extended portions for adjusting the capacitance value on the outer periphery thereof.