JPH10149694A - Semiconductor memory and data rewriting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relieve faulty cells even when faulty cells are detected in a packaged state by providing a faulty address writing mode capable of writing faulty addresses to EEPROM elements for storing faulty addresses of a memory redundancy circuit from the outside. SOLUTION: This semiconductor memory is provided with plural EEPROM elements 10 for storing faulty addresses, plural address input pads 11 to which an address signal is inputted from the outside and a faulty address writing circuit 12 controlling the writing of the faulty signal to be inputted from the outside via an address input pad 25 when an faulty address writing mode with respect to the EEPROM elements 10 is specified from the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory and a data rewriting circuit, and more particularly, to a memory redundancy circuit using an EEPROM element as a defective address storage element and an E-memory.
The present invention relates to a data rewriting circuit using an EPROM element.

[0002]

2. Description of the Related Art A memory redundant circuit of a semiconductor memory detects a defective row or a defective column when it detects that an address (defective address) corresponding to a defective row or a column in which a defective cell of a memory cell array exists is specified. Is replaced with a spare row or spare column. A polysilicon fuse and an aluminum wiring whose connection can be changed by selecting a mask pattern are used as the storage element of the defective address.

FIG. 4 is a flowchart showing an example of a flow from a lot rise to a final test in manufacturing a conventional semiconductor memory using a polysilicon fuse as a storage element of a defective address.

[0004] After the lot is lifted, a first die sort test is first performed. The address data to be replaced is obtained for a chip which may become a good product among the defective ones. And
The fuse is blown based on the address data, a second die sort test is performed, and a good product and a defective product are confirmed. Here, there is no problem if all the chips using the redundant circuit are good products, but if there are many defective products, it is necessary to analyze the cause. As a result of the analysis, address data to be replaced for a chip that may become a non-defective product is obtained. Then, the fuse is blown based on the address data, and a third die sort test is performed. Hereinafter, the above-described analysis, fuse blowing, and die sort test are slightly repeated. If the cause is unknown, the die sort test may be stopped.

On the other hand, there is a technique in which an EEPROM (electrically erasable programmable read only memory) element, which is a non-volatile memory element, is used as a defective address storage element instead of a polysilicon fuse or aluminum wiring.

However, E is used as a storage element for a defective address.
A conventional memory redundancy circuit using an EPROM element is:
If a defective cell is detected in a package (for example, resin-sealed) state after the assembly of the semiconductor memory, the defect cannot be remedied, so that it has been difficult to improve the yield.

Therefore, in order to increase the yield of the reliability test in the package state of the semiconductor memory, the die sort test in the wafer state is strictly required, but this leads to an increase in test time.

Recently, improvement in yield by adopting a memory redundant circuit, increase in chip size and increase in test cost due to adoption of a memory redundant circuit have been considered.
Cost-equivalent, 1Gbit class D
In a RAM, the advantage of the memory redundancy circuit is diminished.

[0009]

As described above, the conventional memory redundancy circuit of a semiconductor memory has a problem that it cannot be remedied when a defective cell is detected in a package state. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has a defective address write mode in which a defective address can be externally written to an EEPROM element for storing a defective address of a memory redundant circuit, and a defective cell is detected in a package state. It is an object of the present invention to provide a semiconductor memory which can be relieved even in the case where it is performed, and which can reduce costs by shortening the process, reducing the chip size, improving the yield, and the like. It is another object of the present invention to provide a data rewriting circuit that can easily rewrite data stored in an EEPROM element by external control.

[0010]

SUMMARY OF THE INVENTION A semiconductor memory according to the present invention comprises a plurality of EEPROM elements for storing a defective address;
A plurality of address input pads to which an address signal is input from the outside, and write control of a defective address signal input from the outside via the address input pad to the EEPROM element when a defective address write mode for the EEPROM element is designated from the outside. And a defective address writing circuit.

A data rewriting circuit according to the present invention is connected to a stack gate type transistor for storing data and a control gate of the stack gate type MOS transistor, and a conduction / non-conduction state is controlled according to a predetermined write control signal. A write switch MOS transistor, and a drain / source connected to the drain / source of the stack gate type transistor, the conduction / non-conduction state of which is controlled according to a mode control signal supplied from outside. A transfer MOS transistor, a read MOS transistor having a drain and a source connected between the source of the stack gate type transistor and a second power supply potential, and a predetermined read control signal applied to the gate; The drain node of the stacked gate transistor is charged in a precharge period. A precharge circuit for precharging to a first power supply potential, a power supply switching node to which a plurality of power supply voltages including a high voltage for writing are switched and supplied, and a drain node of the stack gate type transistor; A write voltage supply circuit whose operation is controlled according to the mode control signal.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a part of a memory redundant circuit formed on a memory chip according to a first embodiment of the semiconductor memory of the present invention.

In FIG. 1, reference numeral 10 denotes a plurality of EEPROM elements for storing a defective address, 11 denotes a plurality of address input pads to which an address signal is inputted from the outside, and 12 denotes the EEPROM.
When a defective address writing mode for an EPROM element is designated externally, a defective address signal input from the outside via the address input pad 11 is transmitted to the EEPROM.
This is a defective address writing circuit that controls writing to the OM element 10.

As means for externally designating the defective address write mode, (1) an external terminal 25 dedicated to mode control input is provided, and a logic is provided from this external terminal 25 in accordance with the normal read mode / defective address write mode. A method of inputting mode control signals having different levels, (2)
One or more existing external terminals (eg, data output terminals) are also used as mode control input terminals, and a control voltage or control signal different from that in normal use is input from the external terminals (defective address write mode). There is a method in which a mode discriminating circuit (not shown) is provided for discriminating whether or not the mode is determined, and generating a mode control signal having a different logic level according to the discrimination result.

According to the EEPROM having the memory redundancy circuit of FIG. 1 as described above, the EEPROM for storing the defective address is used.
Since the PROM element 10 is provided with a defective address writing mode in which a defective address can be written from the outside, the chip size can be reduced, and the quality of the EEPROM chip can be determined by using a redundant circuit during a die sort test in a wafer state. Become.

In addition, not only at the time of the die sort test but also at the time of the test in the package state after the assembly, when a defective cell is detected or when an error in data stored in the defective address storage element is found, Since the stored data can be erased and the defective address data can be rewritten from the outside, it is possible to rewrite the data with correct data, and the cost can be reduced by shortening the process and improving the yield.

FIG. 2 shows an example of a defective address storage circuit and a defective address writing circuit of a memory redundant circuit formed on an EEPROM chip according to a second embodiment of the semiconductor memory of the present invention.

In FIG. 2, reference numerals 101 to 108 denote a plurality (eight in this example) of EEPROM elements for storing defective addresses, each of which is a stacked gate type MOS transistor having a double-layered structure of a floating gate and a control gate. Consists of

There are various methods for performing a data write operation / data erase operation of the stacked gate type MOS transistor. In the following, charge injection / accumulation charge discharge to a floating gate by a tunnel current is performed. The method will be described as an example.

Address input pads 111 to 118 are connected to external terminals of the package correspondingly.
Address signals Add1 to Add8 are input from outside. 13 denotes a plurality of the stacked gate type transistors 101 to 108
Is a precharge circuit that precharges each drain common connection node A to the power supply potential Vcc during the precharge period. The precharge circuit 13 has a normal power supply voltage Vcc.
Between the source and the drain between the Vcc power supply node supplied with the common gate and the common connection node A of the drains of the stacked gate type MOS transistors 101 to 108, and the precharge signal PRCH is supplied to the gate. Of PMOS transistors 131.

Reference numerals 211 to 218 denote NMs for a write switch.
OS transistors, corresponding to the address input pads 111 to 118 and the stacked gate type MOS.
It is connected between the control gates of the transistors 101 to 108.

Reference numerals 221 to 228 denote NMOS transistors for transmitting potential. The stacked gate type MOS transistors 101 to 108 are connected to the drains and the sources.

Reference numerals 231 to 238 denote NMOs for inputting addresses.
S transistor, corresponding to the source of the stacked gate type MOS transistor 101-108 and the second
Power supply potential (ground potential Vss in this example).

Address input buffers 241 to 248 correspond to the address input pads 111 to 118, respectively.
Address signals Add1 to Add8 are input from the NMOS transistor 23 corresponding to the address input.
1 to 238.

Reference numeral 25 denotes a mode control input pad to which a mode control signal MODE having a different logic level according to the normal read mode / defective address write mode is applied. The mode control signal MODE can be applied in various ways, for example, as described below.

(1) An external terminal dedicated to mode control input is provided in the package and connected to the mode control input pad 25, and a mode control signal having a different logic level depending on the normal read mode / defective address write mode is supplied to the external. To the mode control input pad 25 via the external terminal.

(2) One or more existing external terminals (eg, data output terminals) of the package are also used as a mode control input terminal, and a control voltage or control signal different from that in normal use is input from the external terminal. (In a defective address writing mode), and a mode discriminating circuit (not shown) for generating a mode control signal having a different logic level according to the discrimination result is provided. It is supplied to the input pad 25.

The mode control input pad 25 is connected to the NMOS transistors 211 to 218 for the write switch.
Of each gate, NMOS transistor 221 for transmitting potential
To 228 and the address input buffer 2
41 to 248 are connected to the respective control input nodes.

Reference numeral 26 denotes a power supply switching node to which a plurality of power supply voltages including a high voltage Vpp for writing data to the stacked gate type MOS transistors 111 to 118 are switched and supplied, and a common drain for each of the plurality of stacked gate type transistors. The write voltage supply circuit is connected between the connection node A and controls whether or not operation is possible in accordance with the mode control signal.

The write voltage supply circuit 26 includes a PMOS transistor 261 having a source and a drain connected between the power supply switching node and the common connection node A;
It comprises a first inverter circuit 262 inserted between the mode control input pad 25 and the gate of the PMOS transistor 261.

Reference numeral 27 denotes a latch circuit, which is a PMOS transistor 2 for pull-up whose source and drain are connected between the Vcc power supply node and the common connection node A.
71, the node A and the PMOS transistor 27
2nd inverter circuit 2 inserted between the first and second gates
72.

Reference numerals 28 and 29 denote a third inverter circuit connected in two stages to the output side of the latch circuit 27 and a fourth inverter circuit.
Of the inverter circuit. The write switch NMOS transistors 211 to 218, the potential transfer NMOS transistors 221 to 228, and the write voltage supply circuit 26 are configured such that the defective address write mode for the stacked gate type MOS transistors 101 to 108 is externally designated. The defective address signal input from the outside via the address input pads 111 to 118 when the
.. Constitutes a part of a defective address writing circuit having a function of writing to.

Next, the operation of the circuit of FIG. 2 will be described. In the defective address write mode, an “H” level is applied to the mode control input pad 25. By the mode control input "H", the address input buffers 241 to 248
Are disabled and output “L” level respectively, and the NMOS transistors 231 to 231 for address input are output.
238 turns off.

At this time, the first inverter circuit 2 of the write voltage supply circuit 26 is controlled by the mode control input "H".
The output of 62 is "L", the PMOS transistor 261 is turned on, and the potential of the node A becomes the potential of the power supply switching node.

At this time, the mode control input "H"
As a result, the NMOS transistors 221 and 2 for transmitting the potential
Reference numeral 28 indicates a conductive state, and transmits the potential of the node A to the sources of the corresponding stacked gate type MOS transistors 101 to 108.

At this time, the mode control input "H"
As a result, the NMOS transistor 21 for the write switch
1 to 218 become conductive and transmit the potentials of the corresponding address input pads 111 to 118 to the respective control gates of the corresponding stacked gate type MOS transistors 101 to 108.

Here, "1" is assigned to a desired EEPROM element.
A case where data is to be written will be described. In this case, high voltage Vpp for writing is applied to the power supply switching node, and the potential of node A attains the "H" level.

For example, when it is desired to write "1" data into the stacked gate type MOS transistor 101, an "L" level is applied to the address input pad 111 corresponding to the MOS transistor 101, and other stacked gate type MOS transistors 101 “H” level is applied to the address input pads corresponding to the transistors 102 to 108.

As a result, the control gate of the stacked gate type MOS transistor 101 to which "1" data is to be written becomes "L" level, and the "H" level is applied to the substrate of the MOS transistor 101. Then, a predetermined potential difference is generated between the source and the substrate, electrons are injected into the floating gate by a tunnel effect, and a "1" write state is set.

At this time, other stacked gate type M
The control gates of the OS transistors 102 to 108 are “H”
Level and its source is “H” level,
"1" is not written to the floating gate.

On the other hand, a case where "0" data is to be written in a desired EEPROM element will be described. In this case, for example, the power supply potential Vcc is applied to the power supply switching node, and the potential of the node A becomes "L" level.

For example, when writing "0" data to the stacked gate type MOS transistor 102, the address input pad 112 corresponding to the MOS transistor 102 is set to "L" level, and other stacked gate type MOS transistors are used. “H” level is applied to the address input pads corresponding to the transistors 101 and 103 to 108.

As a result, the control gate of the stacked gate type MOS transistor 102 to which "0" data is to be written becomes "H" level, and the "L" level is applied to the MOS transistor 102 substrate. Then, a potential difference occurs between the source and the substrate in the direction opposite to that at the time of writing "1", and electrons of the floating gate are emitted.
The state becomes "0" write state (erase state).

At this time, other stacked gate type M
Since the control gates of the OS transistors 101 and 103 to 108 are at "L" level and their sources are at "L" level, "0" is not written to the floating gate.

That is, in the address write mode for the stacked gate type MOS transistors 101 to 108, desired data can be stored by using the above-described operation principle.

When the memory redundancy circuit is not used, the stacked gate type MOS transistor 101
To 108 are set to the "1" write state.
The stacked gate type MOS transistor in the "1" write state is in the ON state because the drain current flows even when the control gate is at 0V.

On the other hand, when the memory redundancy circuit is used, the stacked gate type MOS transistor 1
01 to 108 are set to "0" write state or "1" write state corresponding to each bit data "1" or "0" of the defective address. The stacked gate type MOS transistor in the "0" write state (erase state) is in the off state because no drain current flows when the control gate is at 0V.

On the other hand, in the normal read mode for the stacked gate type MOS transistors 101 to 108, the precharge control signal PRCH goes low during the precharge period, the PMOS transistor 271 turns on, and the node A Are precharged to the Vcc level.

The mode control input pad 25 has "L"
Level is applied, and the mode control input “L”
First inverter circuit 262 of write voltage supply circuit 26
Is "H", the PMOS transistor 261 is turned off, and the NMOS transistors 211 to 218 for writing switches and the NMOS transistors 221 to 228 for transmitting potential are turned off, and the stacked gate type MOS transistor is turned off. Each control gate of the transistors 101 to 108 is electrically floating.

Also, the mode control input "L"
The address input buffers 241 to 248 are enabled, and address signals Add1 to Add8 input from the address input pads 111 to 118 are input to the gates of the address input NMOS transistors 231 to 238 via the address input buffers 241 to 248. .

Then, the NMOS transistor for address input corresponding to the address input pad to which "1" data is input is turned on, and the corresponding stacked gate type M transistor is turned on.
The source of the OS transistor is at ground potential (“L” level)
become. Also, the address input NMOS transistor corresponding to the address input pad to which "0" data is input is turned off.

When the memory redundancy circuit is not used (stacked gate type MOS transistors 101 to 1)
08 is set to "1" write state)
The stacked gate type MOS transistor 1
01 to 108 are on independently of the potentials of the control gates. Therefore, when any one of the address input NMOS transistors 231 to 238 is turned on, the potential of the node A is discharged and the The output of the circuit 27 is “H”, the output of the third inverter circuit 28 is “L”, and the output of the fourth inverter circuit 29 is “H”. Thereby, a normal address decoder (not shown) is activated to select a normal memory cell, and the spare address decoder (not shown) is deactivated.

On the other hand, when a memory redundancy circuit is used (a stacked gate type MOS transistor 101).
In the case where the "0" write state or the "1" write state is set corresponding to each bit data "1" or "0" of the defective address in .about.108, the stacked gate type MOS transistor 101 is used. -108 and bit data previously stored in the stacked gate type M
NMOS transistors 231 to 238 for address input connected in series to OS transistors 101 to 108
When the bit data of the address signal input to each of the gates matches, the potential of the node A is not discharged.

That is, the stacked gate type MOS transistor is in the "0" write state (off state), and "" is added to the gate of the address input NMOS transistor connected in series to the stacked gate type MOS transistor. Even if the address input NMOS transistor is turned on when "1" is applied (bit coincidence), the potential of the node A is not discharged.

On the other hand, a stacked gate type MO
The S transistor is in a "0" write state (off state), and an NMO for address input connected in series to this is
When "0" is applied to the gate of the S transistor (bit mismatch), the NMOS transistor for address input is turned off, so that the potential of the node A is not discharged.

When the stacked gate type MOS transistor is in the "1" write state (ON state), the gate of the address input NMOS transistor connected in series to the stacked gate type MOS transistor is connected to "1". When "0" is applied (at the time of bit matching), the NMOS transistor for address input is turned off, so that the potential of the node A is not discharged.

On the other hand, a stacked gate type MO
The S transistor is in a "1" write state (ON state), and an NMO for address input connected in series to this is
When "1" is applied to the gate of the S transistor (bit mismatch), the NMOS transistor for address input is turned on, and the potential of the node A is discharged.

As described above, when the potential of the node A is not discharged (bit coincidence), the third inverter circuit 2
The output signal RSP of No. 8 and the output signal BRSP of the fourth inverter circuit 29 correspond to “H” / “L” state (active state).

The complementary signals RSP and BRSP in this state are:
A normal row address decoder or a column address decoder (not shown) is deactivated, and a spare row address decoder or a column address decoder (not shown) is activated to select a normal memory cell. Is used as a control signal for selecting (replacing) a spare row or spare column in place of the selection.

FIG. 3 is a flow chart showing an example of the flow from a lot up to the final test when manufacturing the EEPROM provided with the memory redundancy circuit shown in FIG. 1 or FIG.

In the wafer state after the lot, first, a die sort test (for example, 850 ° C., an applied power supply voltage of 5
V including a burn-in test). At this time, when a defective memory cell is detected, the corresponding defective address is written to the defective address storage circuit, and the defective memory cell is replaced with a spare memory cell.

Next, a reliability test is performed on the package after assembly. As a result, when a defective memory cell is detected, a defective address corresponding to the defective memory cell is rewritten into the defective address storage circuit and replaced with a spare memory cell, thereby enabling a non-defective product.

Although not shown in the above flow chart, a sample in which a 2-bit defective cell that is not adjacent to each other is repaired by one redundant circuit for repairing a defective row and one redundant circuit for repairing a defective column is described. According to the present invention, according to the present invention, if a defective row is relieved in a reliability test in a package state and a defective column is accelerated and a defective column is generated and the defective column is detected, a defective product is conventionally obtained. The defective address corresponding to the column can be rewritten and remedied, and a good product can be obtained.

That is, E having the memory redundancy circuit of the present invention
According to the EPROM, the quality of the EEPROM chip can be determined by using a redundant circuit during a die sort test in a wafer state.

In addition to the die sort test, the data stored in the defective address storage circuit can be erased and the defective address data can be rewritten from outside not only at the time of testing in a package state after assembly but also at the time of external testing. If an error is found in the data stored in the defective address storage circuit, the data can be rewritten to correct data.

By arranging a plurality of spare circuits as spare circuits corresponding to an arbitrary memory area, if one of the temporarily replaced spare circuits is found to be defective, the spare circuit is placed in an inactive state. Then, it is possible to replace the spare circuit with another normal spare circuit, and the remedy rate of defective products is remarkably improved.

Incidentally, the defective address storage / rewrite circuit of FIG. 2 includes, as a basic configuration, a data rewrite circuit capable of easily rewriting the storage data of the EEPROM element by external control.

That is, this data rewriting circuit is a stack gate type transistor (eg, 101) for storing data.
Connected to the control gate of the stack gate type MOS transistor, and turned on / off in response to a predetermined write control signal.
A write switch MOS transistor (for example, 211) whose non-conduction state is controlled, and a drain / source connected to the drain / source of the stack gate type transistor, and a mode control signal M supplied from the outside.
A potential transmitting MOS transistor (for example, 221) whose conduction / non-conduction state is controlled in accordance with the ODE, and a drain and a source connected between a source of the stack gate type transistor and a second power supply potential; A read MOS transistor (for example, 231) to which a predetermined read control signal is applied to the gate, and a drain node of the stack gate type transistor are firstly charged during a precharge period.
Circuit 13 for precharging to the power supply potential of
Is connected between a power supply switching node to which a plurality of power supply voltages including a high voltage for writing are switched and supplied and a drain node of the stack gate type transistor, and the availability of operation is controlled according to the mode control signal. And a write voltage supply circuit 26.

[0069]

As described above, according to the semiconductor memory of the present invention, the EEP memory for storing the defective address of the memory redundant circuit is provided.
A defective address write mode that can write a defective address to a ROM element from the outside is provided, so that even if a defective cell is detected in a package state, it can be relieved, and the cost can be reduced by shortening the process, reducing the chip size, and improving the yield. Down can be planned.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a part of a redundant circuit of a semiconductor memory according to a first embodiment of the present invention.

FIG. 2 shows an EEPROM according to a second embodiment of the present invention.
FIG. 2 is a circuit diagram showing an example of a defective address storage circuit and a defective address rewriting circuit of a redundant circuit formed on the chip of FIG.

FIG. 3 is a flowchart showing an example of a flow from a lot rise to a final test when manufacturing the semiconductor memory provided with the redundant circuit shown in FIG. 1 or FIG. 2;

FIG. 4 is a flowchart showing an example of a flow from a lot rise to a final test in manufacturing a conventional semiconductor memory.

[Explanation of symbols]

 10: EEPROM element, 11: address input pad, 12: defective address writing circuit, 25: mode control input pad.

Claims (7)

[Claims] A plurality of EEPROMs for storing a defective address.
An M element, a plurality of address input pads to which an address signal is externally input, and a defective address signal externally input via the address input pad when a defective address writing mode for the EEPROM element is designated from the outside.
A semiconductor memory, comprising: a defective address writing circuit that controls writing to a ROM element. 2. The semiconductor memory according to claim 1, wherein said means for externally specifying said defective address write mode is for inputting a mode control signal having a different logic level according to a normal read mode / defective address write mode. A semiconductor memory having an external terminal dedicated to mode control input. 3. The semiconductor memory according to claim 1, wherein said means for designating said defective address write mode from outside is provided with a control voltage or control signal different from that in normal use from one or more existing external terminals. A semiconductor memory, comprising: a mode discriminating circuit for discriminating whether or not an input has been made, and generating a mode control signal having a different logic level according to the discrimination result. 4. A plurality of address input pads to which an address signal is input from outside, a plurality of stack gate type transistors for storing a defective address, and address signals from the plurality of address input pads correspondingly input; A plurality of address buffer circuits whose operation is controlled depending on a mode control signal having a different logic level depending on a normal read operation mode / defective address write operation mode for the stack gate type transistor; Each of the plurality of stacked gate type MOS transistors is inserted and connected correspondingly to each control gate, and is turned on / off in response to the mode control signal.
MO for multiple write switches whose non-conducting state is controlled
An S transistor; a precharge circuit for precharging each drain common connection node of the plurality of stacked gate transistors to a first power supply potential during a precharge period; and a plurality of power supply voltages including a high voltage for writing are switched and supplied. Connected between the power supply switching node to be connected and each drain common connection node of the plurality of stacked gate transistors,
A write voltage supply circuit whose operation is controlled in accordance with the mode control signal; and a drain / source corresponding to each drain / source of the plurality of stacked gate transistors, wherein the mode control signal A plurality of potential transmitting MOS transistors whose conduction / non-conduction state is controlled in accordance with the following; and a drain-thorn connection between each source of the plurality of stacked gate transistors and a second power supply potential; And a plurality of address input MOS transistors to which respective output signals from the plurality of address buffer circuits are applied corresponding to the respective gates. 5. The semiconductor memory according to claim 4, wherein
The semiconductor memory further includes a mode control input pad for receiving the mode control signal from an external terminal. 6. The semiconductor memory according to claim 4, wherein
Further, a mode discriminating circuit for discriminating whether or not a control voltage or a control signal different from that in normal use has been input from one or more existing external terminals and generating the mode control signal is provided. Semiconductor memory. 7. A stack gate type transistor for data storage, and a write switch MOS connected to a control gate of the stack gate type MOS transistor, the ON / OFF state of which is controlled according to a predetermined write control signal. A potential transmission MOS transistor having a drain and a source connected corresponding to a drain and a source of the stack gate type transistor, and having a conduction / non-conduction state controlled according to a mode control signal supplied from outside; A drain M is connected between the source and the second power supply potential of the stacked gate transistor, and a predetermined read control signal is applied to the gate of the read gate M.
An OS transistor; a precharge circuit for precharging a drain node of the stack gate transistor to a first power supply potential during a precharge period; and a power supply switching node for switching and supplying a plurality of power supply voltages including a high voltage for writing. And a write voltage supply circuit connected between the stack gate type transistor and a drain node of the stack gate type transistor, the operation of which is controlled in accordance with the mode control signal.