JPH10149341A - Asymmetric single-chip dual multiprocessor matching and synchronization - Google Patents

Abstract

An integrated multiprocessor structure for simplifying synchronization of a multiprocessor is disclosed. A multiprocessor includes a general processor and a vector processor having a single instruction multiple data system.
20. The vector processor 12
All multi-parallel processors in 0 process instructions simultaneously. The general-purpose processor 110 controls the vector processor 120 and the vector processor 120.
Is activated to form pork in the program flow. The two processors 110 and 120
Executes the parallel separated program until the control processor stops the vector processor 120, or when an exception occurs, or the vector processor 120 follows the program and enters an idle state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention is a partial continuation application for "single instruction, multiple data processing of a multimedia signal processor", filed in the United States on August 19, 1996 and currently pending. The present invention relates to a multiprocessor,
In particular, separate program threads (progr
systems and methods for coordinating or synchronizing am thread).

[0002]

2. Description of the Related Art A multiprocessor includes a plurality of processors working together to complete a task. A relatively simple multiprocessor system is 80386
A co-processor, such as a processor, and
Includes a floating point processor such as the 80387 math coprocessor. In such a system, when the processor receives an instruction that requires floating point operation, the processor activates a coprocessor that executes the instruction. Math coprocessors such as the 80387 processor have many limitations in executing a single instruction when the instruction is directed or idle between floating point instructions. Also, the processing capacity (pr) provided by the coprocessor
There are many limitations to increasing the ocessing power.

[0003] Other multiprocessor schemes have also been used that execute separately but include two or more identical processors that coordinate program threads. However, such multiprocessor schemes vary the time required to complete a portion of the program thread, thus maintaining the program threads in a consistent or synchronized state, e.g., To pass through. For example, cache hits and misses, and instruction dependent variables can delay the execution path and change the number of cycles required to follow an instruction. Therefore, there is a problem that the instruction sequences in other program threads are sometimes not synchronized with each other.

[0004] To maintain proper synchronization, hardware coupled between the processors delays or idles the processors so that the program threads can be synchronized with each other. In a system having a plurality of identical processors, each program thread plays a role of delaying itself or delaying another program. Such systems often have complex synchronization hardware and require complex software to maintain program thread synchronization and alignment. Hardware having such a complicated synchronization scheme increases the size of a chip in an integrated system. Also, complex synchronization makes software development longer and more difficult.

[0005]

SUMMARY OF THE INVENTION Accordingly, the present invention is directed to overcoming the problems in the prior art, which aims to provide a high degree of processing power and to allow multiple embedded program threads to be compatible. It is an object of the present invention to provide a multiprocessor system which has a characteristic and can synchronize and match programs by a simple method.

[0006]

According to one embodiment of the present invention, there is provided an integrated asymmetric program-controlled multiprocessor including two processors. The first processor, named the control processor, runs the program thread continuously, causing the second program thread on the second processor, named the coprocessor, to run or stop.
Both processors share an extension register set that facilitates communication for synchronization. The control processor accesses the coprocessor registers so that initialization of the coprocessor is possible for a program thread to be activated later. The coprocessor has no circuitry and the first
No circuitry is required to control or access the processor.

[0007] The processor has an asymmetric instruction set and structure. For example, the control processor may read or write a register of the coprocessor, a command to access the extension register, a command to start the coprocessor, and a command to interrupt the coprocessor. Execute The coprocessor executes an instruction to access the extension register, but cannot access the control processor register. The coprocessor instruction to terminate the program thread transmits a signal transition of the program thread to the control processor via an interrupt by setting a status flag in the extension register indicating that the coprocessor is idle.

[0008] The control processor polls the extension register or uses an interrupt mechanism to determine when the coprocessor has a transitioned task. The synchronization flag in the extension register is polled by the control processor or the coprocessor to determine whether or not another processor has a necessary condition for continuously executing a program thread. It can be so. By using polling, the control processor and coprocessor can be synchronized without stopping the coprocessor. Special control processor instructions that can test and set flags in the extension register facilitate polling for synchronization.

According to one embodiment of the present invention, the control processor is a general purpose processor, and the coprocessor is a vector processor having a single instruction multiple data system. According to the present invention, the computational power that appears inefficiently when performing the synchronization function can be enhanced by the vector processor, and the control processor that realizes the synchronization has a smaller data path than the data path of the vector processor. It is very efficient because it can have a path. The dual processor structure of an embodiment according to the present invention uses a multiprocessor in a vector processor, provides a high degree of processing power capable of processing a wide range of data paths, and is compatible with two separate program threads. Software synchronization, which is preferentially provided via the control processor, can be simplified.

[0010]

Embodiments of the present invention will be described below with reference to the accompanying drawings, and the same reference numerals are used for the same portions throughout the drawings. The multiprocessor described as an embodiment of the present invention includes a set of processors executing program threads that are separated in parallel. Execution control and synchronization is performed asymmetrically, with one processor becoming the main or control processor and the other becoming the slave or controlled processor. The control processor executes a continuous program thread, and the continuous program thread issues a parallel processing instruction by executing a second parallel program thread on the controlled processor. When the controlled processor has completed the second program thread and is idle, the second program thread is combined with the program thread. The instruction set of the controlled processor includes instructions indicating that the second program thread has been completed by terminating the second program thread during execution and transmitting an interrupt request to the control processor.

[0011] Information can pass between program threads through a distribution channel. The distribution paths are as follows: a shared address space and memory of the processor, a register set of the controlled processor which the control processor can access when the controlled processor is idle, and an "extended" register which can access both processors. One example of the extension register is one or more flag bits set by the controlled processor to indicate that a specific operation has been completed. The other flag bits indicate whether the controlled processor is executing a task started with priority or is in an idle state. By using the flag bit, the control processor's program thread
ait loop). The wait loop polls a flag bit to determine if a result from the controlled processor is available. The controlled processor generally does not require software synchronization within its own program thread. Thus, software synchronization requires only minimal overhead.

FIG. 1 shows a block diagram of a multiprocessor 100 shown as an embodiment of the present invention. The multiprocessor 100 includes a general-purpose processor 110 and a vector processor 120 integrated on a monolithic semiconductor chip. The general processor 110 and the vector processor 120
Cache subsystem 130 including RAMs 160 and 190, ROM 170, and cache control unit 180
Through the other on-chip (on-
chip) element. Multiprocessor 100
Arranges the SRAM 160 in the form of an instruction cache 162 and a data cache 164 for the general-purpose processor 110, and stores the SRAM 190 in the vector processor 120.
192 and 194. SRAM 160, 19
The zero component causes the scratch pad memory to be formed alternately in the shared address space of the general purpose processor 110 and the vector processor 120.

The on-chip ROM 170 has data and firmware for the general purpose processor 110 and the vector processor 120 and can be accessed by a cache. ROM 170 generally includes a reset and initialization sequence, a self-test diagnostic sequence, and interrupt and exception handling. In one embodiment of the present invention, the multiprocessor 100 is used for signal processing in multimedia, and is also referred to herein as a multimedia signal processor or MSP. According to one embodiment of the present invention, a ROM
170 is a subroutine for sound card emulation, a subroutine for modem signal processing, a subroutine for general telephone functions, a 2-D and 3-D graphic subroutine library, and an MPEG-
1, MPEG-2, H.264. 261, H .; 263, G.R. 72
8, and G. It additionally includes a subroutine library for audio and video encoding and decoding standards, such as 723.

[0014] filed with the United States Patent Office on August 19, 1996, entitled "Multiprocessor Operation in Multimedia Signal Processors."
The invention entitled "a Multimedia Signal Processor" additionally describes the use of a multiprocessor in multimedia. The general contents of said invention are described herein by reference. 130 connects the general processor 110 and the vector processor 120 to two system buses 140 and 150, and connects the general processor 110 and the vector processor 1 to each other.
20 and acts as a cache and switching station for the devices coupled to the two system buses 140,150. System bus 150 operates at a higher clock frequency than system bus 140.
The system bus 150 includes a memory controller 158 that provides an interface for an external local memory, a local bus interface 156, and a DM bus.
A (direct memory access) controller 154 and device interface 152, and a local bus of the host computer, direct memory access, and A / D,
It is connected to a high-speed device such as a D / A converter. System timer 142, UART (universal asynchronou)
s receiver transceiver) 144, bit stream processor 146, and interrupt controller 14
A low speed device such as 8 is connected to the system bus 140. The invention entitled "Multiprocessor Operation in a Multimedia Signal Processor", which is described by reference in the present invention, includes the cache subsystem 13
The operation of the general processor 110 and the vector processor 120 will now be described in detail with respect to an exemplary device in which the general purpose processor 110 and the vector processor 120 access the cache subsystem 130 via the system bus 140 and the system bus 150.

The invention filed in the United States on August 19, 1996, entitled "Apparatus and Method for Video Data Processing" encodes a bit stream having a variable length in accordance with the MPEG standard. And a bitstream processor 146 for decoding. Said invention is also described in its entirety herein by reference. General-purpose processor 110
The vector processor 120 and the vector processor 120 have different structures so as to execute the separated program threads and execute the specific tasks more effectively. The general processor 110 includes a real-time operating system, a general processor 110 and a vector processor 1.
Exceptional routines for 20 and those steps that do not require a lot of iterative calculations are preferentially performed. General processor 11
0 is also the initialization, start,
And stop. The vector processor 120 mainly performs number crunching, including iterative processing on data blocks commonly used in multimedia processes.

FIG. 2 shows a block diagram illustrating the interaction between general purpose processor 110 and vector processor 120. The general processor 110 includes:
It includes an instruction decoder 260 having control logic, an execution data path 270, a recording register 280, and a read register 290. The general purpose processor 110 has a general scalar data value. Execution data path 270 in FIG.
The register file 272 includes a 32-bit data register set and a status register set, and the processing unit 276 has a 32-bit bus for operating operands having a size of up to 32 bits. In an embodiment, the general purpose processor 110 operates at 40 MHz and has a 32-bit R that conforms to the architecture of an ARM7 processor.
An ISC processor. The structure and instruction set of the ARM7 RISC processor is "ARM DDI 0010G," document number ARM DDI 0010G, available from Advance RISC Machines Ltd.
7DM data sheet ". A.
The RM7DM data sheet is described herein by reference. Appendix A describes the interaction between the general purpose processor 110 and the vector processor 120 or the ARM for the cache subsystem 130 described in the embodiment.
Represents the extension of 7 instructions.

In the embodiment shown in FIG. 2, the vector processor 120 has a single instruction multipl
e data) structure, and an instruction fetch unit (instruction fetc
h unit) 210, decoder 220, scheduler 2
30, the execution data path 240, and the loading / storage device (L
SU) 250. The instruction fetch unit 210 fetches process flow control instructions such as instructions and branches. The decoder 220 decodes one instruction per cycle according to the order of arrival from the instruction fetch unit 210, and records the field values decoded by the instruction transmitted to the FIFO 234 in the scheduler 230. The issue control logic 232 in the scheduler 230 selects the execution data path 240 and the field values recorded in the load / store unit (LSU; 250) to complete the operation. Execution data path 24
0 executes logical / arithmetic instructions that operate on vector data or scalar data. Loading / Storage Unit (LSU)
The 250 executes a load / store instruction that accesses the shared address space of the general processor 110 and the vector processor 120. The exception control logic 215 is coupled to the instruction fetch unit 210, the decoder 220, and the scheduler 230, and applies an interrupt to the general processor 110 when decoding or execution of the vector processor instruction causes an exception.

In the embodiment, the execution data path 24
0 has a parallel processing unit 246 that includes eight 32-bit floating point units, eight 36-bit integer multipliers, and eight 36-bit arithmetic logic units (ALUs). Each 36-bit integer multiplier can perform one operation on the 36-bit data element, and can perform two operations on the 16-bit data element simultaneously,
Four operations can be performed simultaneously on 8-bit or 9-bit data elements. The parallel processing device 246 includes:
Process 288 bit vector operands and 32 bit scalar operands. The register file 242 for the execution data path 240 stores the vector register 24
Four. Most of the data paths within the vector processor 120 are 32 8 bit or 9 bit data elements, 16 16 bit elements or 8 32 bit elements.
It has a width of 288 or 576 bits to support simultaneous operation of bit elements. With the SIMD structure, the parallel processing unit 246 in the vector processor 120 can execute and complete the same instruction simultaneously.

The vector processor 120 has eight
It consists of a pipeline RISC engine operating at 0 MHz. The registers of the vector processor 120 include a special register 245, a return address stack (not shown), a 32-bit scalar register 2
43, two banks of vector registers 244, and two double-sized (ie, 576 bits) vector accumulator registers (not shown). Register file 242 has a range of 0 to 31
It includes 32 scalar registers identified in the instruction word by the number of bit registers, and 64 288 bit vector registers organized in two banks of 32 vector registers.

Each vector register is identified by a 1-bit bank number (0 or 1) and a 5-bit vector register number ranging from 0 to 31. Most of the instructions are controlled by control bits (CBAN) stored in a special register (VCSR) of the vector processor 120.
As indicated by K), only the vector registers in the active bank are accessible. The second control bit (VEC64) indicates whether the default number of registers represents a double size vector register containing one register from each bank.
The instruction syntax distinguishes the number of registers representing a vector register from the number of registers representing a scalar register.
The instruction syntax distinguishes the number of registers representing a vector register from the number of registers representing a special register.

The vector register 244 may be divided into data elements of a programmable size.
For example, a 288 bit vector register has 32 8
Bit or 9 bit integer data element, 16 32
It may have a bit integer data element, or eight 32-bit integer data elements, or 32 floating point data elements. Two vector registers logically connected in the form of a double-size register can store a vector having about twice as many data elements. According to the embodiment of the present invention, the setting control bit VE
The C64 positions the vector processor 120 in the mode VEC64 in which the double size (576 bits) is the set value for the vector register. The invention entitled "Single Instruction Multiple Data Processing Method in Multimedia Signal Processor" filed with the U.S. Patent Office on Aug. 19, 1996 has a structure and instruction word set related to the vector processor 120 of this embodiment. Is additionally explained.
The invention is described herein by reference.

Multiprocessor 100 also includes a set of 32-bit extension registers 115 accessible to general purpose processor 110 and vector processor 120. The extension register 115 includes a privilege extension register and a user extension register. The privilege extension register controls and indicates a general operation mode for the multiprocessor 100. The user extension register includes a register that synchronizes a program thread executed by the general processor 110 and the vector processor 120. In one embodiment, the user extension register includes a vector processor status flag (VPSTATE).
And a synchronization flag (VASYNC). The status flag (VPSTATE) has two values (VP_RUN and VP_IDLE), and the vector processor 120
Is running a program thread or is idle. In an embodiment, the vector processor 120 regards the extension register (VASYNC) as its own special register, and a vector processor instruction, for example, an instruction such as VMOV, reads or records the register (VASYNC). Allows access. Other instruction words always approach the special extension register.

For example, a command such as VCINT or VCJOIN, or another command that causes an exception (EXCEPTION), sets the status flag (VPSTATE) to the VP_IDLE state when the program thread is completed or stopped due to the exception. To change. The vector processor status flag (VPSTATE) and the synchronization flag (VASYNC) of the extension register are stored in the general processor 110.
And two ports so that the vector processor 120 can read the registers simultaneously. When the vector processor 120 is in the VP_IDLE state, the general processor 110 can read or record the scalar register and the special register of the vector processor 120. However, the vector processor 120
Reads or records the registers of the vector processor 120 during the VP_RUN state.
Is not clear. AR for general processor 110
The extensions of the M7 instruction set include the instructions (MFER and MTER) approaching the extension register 115 and the instructions (MFVP and MTVP) approaching the scalar and special registers of the vector processor 120.
The condition command (TESTSET) reads the extension register and sets bit 30 of the extension register to 1 if the existing condition is satisfied. Command word (TEST
SET) reads the value erased by the vector processor 120 so that it can represent a synchronization point, and resets bit 30 to provide the next synchronization point, thereby synchronizing the user / producer. To facilitate.

The general-purpose processor 110 has a command word STA.
It can perform RTVP and INTVP, activate and deactivate the vector processor 120, and access the scalar and special registers of the vector processor 120, as mentioned above. In contrast, the vector processor 120 cannot activate and deactivate the general purpose processor 110 and the general purpose processor 11
Cannot access the zero register. Such asymmetric control division between the general purpose processor 110 and the vector processor 120 simplifies the synchronization of the general purpose processor 110 and the vector processor 120. According to an aspect of the present invention, the vector processor 120 generates an interrupt request signal to the general purpose processor 110 every time the vector processor 120 enters an idle state. For example, at the end of a general program thread, the vector processor 120 generates an interrupt request signal and executes a command (VCJOIN or VCINT) for setting the vector processor 120 to the VP_IDLE state. The general purpose processor 110 can use the interrupt handling routine to transmit the results and restart the vector processor 120. Accordingly, the interrupt operator can synchronize the general processor 110 and the vector processor 120.

"System and Method for Handling Software Int" filed with the United States Patent Office on August 19, 1996, "Argument Passing and Software Interrupts".
an invention named errupts with Argument Passing,
“System and method for handling interrupts and events in asymmetric multiprocessors
nd Method for Handling Interrupts and Exception Ev
ents in an Asymmetric Multiprocessor Architectur
The invention entitled "e" describes the handling of exceptions and interrupts as described in the embodiments of the invention. The general content of said invention is described herein by reference. The polling process is used to synchronize on behalf of an interrupt operation, and is a flow diagram illustrating an example of a dual threaded process 300 according to one embodiment of the present invention of Figure 3. Vector processor 120.
Before starting the program thread at, the general processor 110 executes a waiting loop 315 comprising steps 310 and 320 for determining a register (VPSTATE) value, so that the vector processor 120 is active or Determine if you are idle. After the multiprocessor 100 is started or reset, or the vector processor 120
Executes an instruction that causes an exceptional situation, then the vector processor 120 goes into an idle state.

"Efficient Saving and Restoring"
in Multiprocessors), August 1, 1996
The invention filed in the United States on the 9th is a processor 11
The content modification methods usable at 0, 120 are disclosed and are referred to throughout the present application. In the method of storing the contents, the vector processor 120 includes an extension register (VIMSK).
When the flag bit (CSE) is set, the content storage command (V
CCS) is executed periodically. When the content storage subroutine is terminated, the vector processor 120
Execute a command (VSCINT or VCJOIN),
The VP_IDLE state can be entered. Thus, in the preferred content storage method, the general purpose processor 110 sets the flag bit (CSE) and waits for the vector processor 120 to enter an idle state, as in the wait loop 315.

The general-purpose processor 110 executes the standby loop 3
Wait at 15 and continue polling the extension register (VPSTATE) until the vector processor 120 is idle. First, the vector processor 120
Is idle, the general purpose processor 110 proceeds to step 3
Execute 30 to set up the vector processor 120 for the new program thread. At step 330,
The general processor 110 is a special register (VPC) of a program counter of the vector processor.
Record the program address. The processor 1
The 10 can also record parameters in other scalar and special registers of the vector processor 120 for sending to the vector processor 120. When the vector processor 120 is initialized, the general processor 110 sends an instruction (STARTVP) to step 345.
Processor 1 that executes a program thread by using
Step 340 of activating 20 is performed. Command word (ST
ARTVP) sets the register (VPSTATE) to VP_
After setting to the RUN state, the vector processor 120 reads out the VP_RUN value, extracts and executes the instruction. At this time, the general-purpose processor 110 continues to execute its program thread so that the processors 110 and 120 can operate in parallel.

At step 300, the general purpose processor 110
Continues to execute its program thread, but in step 3
80 must be synchronized with the result from the vector processor 120. The vector processor 120 executing the program thread completes the result in step 355 and causes the instruction (VCINT or VCJOI) in step 365 to abort execution in step 375.
N). In order for step 380 to occur after step 355, the general processor 110
Executes a wait loop including steps 360 and 370, and waits until the vector processor 120 is idle. Before the vector processor 120 performs step 365, the general purpose processor 110 performs step 360.
Is also one possible order. In this case, the general processor 110 repeatedly executes the instructions 360 and 370 until the vector processor 120 enters an idle state. Further, the general processor 11
Before 0 reaches step 360, the processor 120 may perform step 365. In this case, the general processor 110 determines in steps 360 and 37
And 0 are performed simultaneously.

In step 380, the general processor 1
10 manipulates the result and simply initializes and restarts the vector processor 120 with another STARTVP instruction. If there is a content switch for the previous program thread, the general processor 110 may restore the previously stored content and restart the interrupted program thread as a subroutine address:
The vector processor 120 can be initialized.

FIG. 4 illustrates yet another example of a dual threading process 400 that uses polling for synchronization, as shown in one embodiment of the present invention. The step 400 includes:
It begins as described in the process 300 illustrated in FIG. In particular, the general-purpose processor 110 executes a standby loop 315 until the vector processor 120 enters an idle state.
And the vector processor 120 eventually returns to step 34.
Depending on whether to start running the program thread at 5
In step 340, the vector processor 120 is started. In step 400, before the general processor 110 performs step 480,
The vector processor 120 requests that the result of step 355 be completed. Step 400 differs from step 300 in that the vector processor 120 does not enter an idle state according to the execution of step 455 and the register (VPSTATE) is not used for synchronization. Instead, loop 460 polls the extension register (VASYNC) to synchronize stages 480 and 355.

In a loop 460, a first step 462 reads the extension register (VASYNC). In a preferred embodiment, the general processor 110 reads an extension register and sets a flag bit (bit <30>) of the extension register.
Using the instruction to set (TESTSET),
The extension register can be read. Number of registers 15
Is used as the destination of the instruction (TESTSET), the flag bit is
Is transmitted to the Z bit (zero bit) in the status register. Since the process 400 relies on a vector processor to clear the flag bit to signal that step 355 has been completed, step 355 returns to step 462 if the instruction 468 does not have the status bit Z equal to zero. Determine whether it is completed by branching. If the flag bit is 0, the general processor 110 moves to step 480 and continues to perform the process. Using the command (TESTSET) in step 462 has the advantage that the flag bit in the extension register (VASYNC) is automatically reset for the same future synchronization loop as the loop 460.

Control processor instruction word (VPSTART)
Utilizing the vector processor instruction word (VCJOIN), the multiprocessor 100 of FIG. 1 supports typical parallel execution and sequential execution programming. 5 and 6 show two cases of typical parallel execution. In FIG. 5, the general-purpose processor 110 executes an instruction stream 510 that causes the execution thread 520 for the vector processor 120 to branch. Command word (STARTVP; 51)
2) specifies a target address at which the vector processor 120 starts fetching instructions. Therefore, the first instruction 522 executed by the vector processor 120
Follows the instruction 512 and is performed in parallel with the instruction executed by the general purpose processor 110. The general purpose processor 110 continues to execute its instruction stream until it reaches the wait loop 514 as described above with reference to FIGS. The vector processor 120 clears a register (VASYNC) and places an instruction (VC
Execute the instruction stream until it arrives at JOIN (524). In another embodiment, the vector processor 120 requests an interrupt from the general processor 110, and the interrupt handler executed by the general processor 110 stores a register (V
Clear (PSTATE). In FIG. 5, before the vector processor 120 reaches the command VCJOIN 524, the general processor 110 waits for a standby loop 51.
4 and the general processor 110 spins:
Wait until the vector processor 120 completes its assigned task.

Optionally, as shown in FIG. 6, the vector processor 120 completes the instruction stream 540 and before the general processor 110 reaches the wait loop 534, starting at instruction 542 and executing the instruction VCJOIN.
Ends in In this case, the general-purpose processor 110 spends time waiting for the spin, but instead passes through the waiting loop 524. However, when the general processor 110 restarts the vector processor, the vector processor 120 executes the instruction VCJOIN564.
Is idle from the point in time that is executed after the standby loop 524.

The parallel programming paradigm provides a high level of performance because a multi-threaded parallel program utilizes the power of the vector processor 120 while performing calculations on the scalar portion in parallel on the general purpose processor 110. I do. The data exchange between the processors 110, 120 originates from a synchronization point indicated by a waiting loop performed by the general purpose processor 110. No spin waiting is required for the vector processor 120. FIG. 7 shows the multiprocessor 10 of FIG.
1 illustrates a typical sequential programming for zero.
In typical sequential execution programming, the general purpose processor 110 branches the execution thread as the instruction word STARTVP 552 and immediately enters the waiting loop 554. The general processor 110 includes the vector processor 120.
Waits in a loop 554 until it completes the program sequence 560 from instruction 562 to instruction VCJOIN 564. The vector processor 120 executes the instruction VCJO
After performing IN564 and entering the idle state, the general purpose processor 110 exits the standby loop 554 and starts executing instructions sequentially following instructions 562 to 564.
The typical sequential execution programming is less effective than the typical parallel execution programming, but is logically simpler.

A change in the exemplary sequential execution programming of FIG. 7 or the exemplary parallel execution of FIG. 6 is that the unique function of the general processor 110 causes the vector processor 120 to start, causing interrupts and exceptional situations. While operating, the vector processor 120 is able to execute the entire program. Such a change is useful in exemplary embodiments where the vector processor 120 operates at twice the operating frequency of the general purpose processor 110 and is much more powerful than the general purpose processor 110. While the invention has been illustrated and described with respect to certain preferred embodiments, it will be understood that the invention is capable of various modifications and changes within the spirit and scope of the invention as defined by the following claims. Is readily apparent to those of ordinary skill in the art.

[0036]

Embodiment 1 In an embodiment, the processor 110 is
This is a general processor conforming to the standard for the RM7 processor. For details of the ARM7 processor and the instruction set, refer to the ARM7 data sheet (document number ARM7 DDI 0020C, published in December 1994).
See The extension for the ARM7 instruction set is
Activate and deactivate the vector processor 120; test the state of the vector processor, such as the state for synchronization; transmit data between registers in the vector processor 120 to registers or extension registers in the general purpose processor 110 By doing so, the general processor 110 interacts with the vector processor 120. To enable transmission between the general register and the vector register, an intermediate storage such as a local memory is required. Table 1 shows the extensions to the ARM7 instruction set for the general purpose processor 110 to disclose the interaction with the vector processor 120 and the cache subsystem 130.

[0037]

[Table 1]

Table 2 shows the ARM7 exception list. This is detected and recorded before executing the wrong faulting instruction. The exception vector address is 1
Given in hexadecimal.

[0039]

[Table 2]

Next, the extension syntax for the ARM7 instruction set will be described. The ARM7 structure provides three instruction formats for the coprocessor interface: 1. Coprocessor data (CDP) format 2. Coprocessor data transmission (LDC / STC) format Coprocessor Register Transfer (MRC / MCR) Format The CDP format command is an ARM7 processor and is used for tasks that do not communicate back. Table 3 shows that the C
Defines the field of DP format command.

[0041]

[Table 3]

Coprocessor data transmission format (LDC / S
TC) loads or stores a subset of coprocessor registers from or directly to memory. ARM
The seven processors supply word addresses, and the coprocessor supplies or accepts data and controls the number of words transmitted. Table 4 defines the fields in the LDC / STC format.

[0043]

[Table 4]

Coprocessor register transmission format (MRC,
MCR) is used to communicate information directly between ARM7 registers and coprocessor registers. Table 5 defines the fields of the instruction word having the MRC / MCR format.

[0045]

[Table 5]

Extended ARM Command The extended ARM command is as follows: Cache (cache work) type: LDC / STC L = 0; CRn = OPc; CP # = 1111. Assembly syntax: STC {cond} p15, cOpc, <Addr
ess> Cache \ cond \ Opc, <Address
> Where cond = {eq, ne, cs, cc,
mi, pl, vs, vc, hi, ls, ge, lt, g
t, le, al, nv} and Opc = {0, 1,
It is 2,3｝. LDC / ST for instruction cache
The C format field CRn contains an opcode (opcode).
e; Opc). Thus, when the decimal notation of the opcode is performed in the first syntax, the letter 'c' is added before the number (ie, use c0 instead of 0). In this regard, ARM7 for address mode syntax
Refer to the data sheet. Description : The instruction cache is only executed if Cond is true. Field Opc <3: 0> represents the following operations.

[0047]

[Table 6]

For the calculation method of EA, refer to the ARM7 data sheet. Exception: ARM7 protection violation INTVP (Interrupt Vector Processor)
Vector processor) format: CDP where Opc = 0001; 0; CP # = 01
11; and CRn, CRd, CP and CRm are not used. Assembler syntax: CDP \ cond \ p7, 1, c
0, c0, c0 where cond = {eq, ne, cs, cc,
mi, pl, vs, vc, hi, ls, ge, lt, g
t, le, al, nv}. Bits 19:12,
7:15 and 3: 0 are reserved.

Description: If Cond is true, the instruction INTV
P transmits a stop instruction to the vector processor. In one embodiment, instruction INTVP causes bit CSE to be set. The setting of such a bit CSE indicates that the vector processor must store its current context and then stop, and then execute the store conditional context instruction VCCS. The ARM7 processor continuously executes the next instruction without waiting for the halt state of the vector processor. ARM
The 7 processor executes the MFER use-wait loop to determine whether the vector processor has been stopped since the INTVP instruction. The INTVP instruction has no effect if the vector processor is already in the VP_IDLE state.

Exception: Unusable MFER (movement from extension register) of vector processor Form: MRC where Opc = 010; L = 1 CRn = C
P; CP # = 0111; CP not used; CRm
= ER. Assembler syntax: MRC {cond} p7, 2, Rd, cP, cER,
O MFER ｛cond｝ Rd, RNAME where cond = ｛eq, ne, cs, cc,
mi, pl, vs, vc, hi, ls, ge, lt, g
t, le, al, nv}, Rd = {r0,. . . , R1
5}, P {0,1}, ER = {0,. . . . , 15｝,
RNAME then refers to the extension register.

Description: The instruction word MFER is executed only when Cond is true. Hereinafter, P: ER <described in Table 7
The data output from the extension register (ER) defined by 3: 0> is moved to the ARM7 register (Rd).

[0052]

[Table 7]

Exception: Protection violation MFVP (movement from vector register) when trying to approach PERx in the middle of user mode: MRC / MCR where Opc = 001; L = 1; CP # = 01
11; and no CP is used. Assembler syntax: MRC ｛cond｝ p7, Rd, CRn, cRm, OMFVP ｛cond｝ Rd, RNAME where cond = ｛eq, ne, cs, cc,
mi, pl, vs, vc, hi, ls, ge, lt, g
t, le, al, nv}, Rd = {r0,. . . , R1
5}, CRn = {c0,. . . . , C15}, CRm =
{C0,. . . . , C15} and RNAME refers to a scalar or special purpose register in the vector processor.

Description: The instruction MFVP is executed only when Cond is true. CRn <1: 0>: CRm <3:
The data output from the scalar register of the vector processor defined by 0> or the special register is moved to the ARM7 register (Rd). Bit C
Rn <1: 0>: CRm <3: 0> are reserved.
Table 8 shows that, from CRn <1: 0>: CRm <3: 0>, a scalar register (SR0-SR
15) and mapping to special registers (SP0-SP15).

[0055]

[Table 8]

SR0 always reads 32 bits of zero, and recording in SR0 is ignored. Exception: Vector processor unavailable MTER (move to extension register) Format: MRC / MCR where Opc = 010; L = 0; CRn = c
P; CP # = 0111; CP is not used. CRm =
ER. Assembler syntax: MRC ｛cond｝ p7,2, Rd, Cp, cER, O MFER ｛cond｝ Rd, RNAME where cond = ｛eq, ne, cs, cc,
mi, pl, vs, vc, hi, ls, ge, lt, g
t, le, al, nv}, Rd = {r0,. . . , R1
5}, P = {0,1}, ER = {0,. . . . , 1
5}, and RNAME refers to the register associative symbol (ie, PER0).

Description: The instruction word MFER is executed only when Cond is true. The data from the ARM7 register (Rd) is P; ER <3:
0> move to the extension register (ER) defined by Exception: Protection violation MTVP (movement to vector register) when trying to approach PERx in the middle of user mode: MRC / MCR where Opc = 1; L = 0; CP # = 011
1; and no CP is used.

Assembler syntax: MRC {cond} p7,1, Rd, CRn, cRm,
O MFVP {cond} RNAME, Rd where cond = {eq, ne, cs, cc,
mi, pl, vs, vc, hi, ls, ge, lt, g
t, le, al, nv}, Rd = {r0,. . . , R1
5}, CRN = {c0,. . . . c15｝, CRm =
{C0,. . . . , C15}, and RNAME refer to the register associative symbol (ie, SP0 or VCSR).

Description: The instruction MTVP is executed only when Cond is true. The data from the ARM7 register (Rd) is moved to the scalar / special registers CRn <1: 0>: CRm <3: 0> of the vector processor. The mapping from CRn: CRm to the scalar and special registers of the vector processor is illustrated in Table A10 above. Exception: Unusable vector processor PFTCH (prefetch) Format: LDC / STC where N = 0; L = 1; CRn = 0010; C
P # = 1111 Assembler syntax: LDC {cond} p15, 2, <address> PFTCH {cond} <address> where cond = {eq, ne, cs, cc,
mi, pl, vs, vc, hi, ls, ge, lt, g
For the t, le, al, nv @ address mode syntax, refer to the ARM7 data sheet.

Description: The instruction word PFTCH is executed only when Cond is true. The cache line specified by the EA is prefetched in the ARM7 data cache. For the calculation of EA, refer to the ARM7 data sheet. Exception: None STARTVP (start vector processor) format: CDP format where Opc = 0000; CP # = 0111;
And CRn, CRd, CP and CRm are not used. Assembler syntax: CDP {cond} p7,0, c0, c0, c0 STARTVP {cond} where cond = {eq, ne, cs, cc, cc
mi, pl, vs, vc, hi, ls, ge, lt, g
For the t, le, al, nv @ address mode syntax, refer to the ARM7 data sheet.

Explanation: The instruction word STARTVP is a command
Is executed only if is true. The instruction word STARTVP is
The execution signal is transmitted by the vector processor, and V
Erase ISRC <vjp> and VISRC <vip>. The ARM7 processor continuously executes the next instruction word without waiting for the execution of the vector processor to start. The vector processor is initialized to a preferred state before such an instruction is executed. Command STARTTV
P has no effect if the vector processor is already in the VP_RUN state.

Exception: Vector processor unusable TESTSET (test set) format: MRC / MCR where Opc = 000; L = 1; CRn = 0;
CP # = 0111; CRm = ER; and no CP is used. Assembler syntax: MRC ｛cond｝ p7,0, Rd, c0, cER, O TESTSET ｛cond｝ Rd, RNAME where cond = ｛eq, ne, cs, cc,
mi, pl, vs, vc, hi, ls, ge, lt, g
t, le, al, nv}, Rd = {r0,. . . , R1
5}, ER = {0,. . . . , 15｝, and RNAM
E is the register associative symbol (ie, UER1 or VA
SYNC).

Description: The command word TESTSET is equivalent to Cond
Is executed only if is true. The instruction word TESTSET stores the contents of the extension register (UERx) in the general register (R
D) and restore the extension register (UERx <30
>) Is set to 1. If ARM7 register 15 is designated as a receive register, UERx <30> restores bit (Z) of the register (CPSR) so that a short wait loop can be provided. Exception: None

[0064]

[Embodiment 2] In this embodiment, the command words VCINT and VCJO are used.
IN, ALC Describes VMOV. In an embodiment of the invention, these instructions are used by the vector processor to support synchronization to the control processor. As a related application, 1996 as referred to above
"Single Instruction Multiple Data Processing in Multimedia Signal Processor," filed in the United States on August 19,
An overall instruction set for a vector processor is described. Instruction work is defined as using a structure defined as the C programming language. VCINT (conditional interrupt ARM7)

[0065]

[Table 9]

Assembler syntax: VCINT. cond #ICODE where cond = {un, lt, eq, le,
gt, ne, ge, ov} Description: If Cond is true, stop execution and, if interrupts are enabled, cause the ARM7 processor to interrupt. Operation: Condition: ((Cond == VCSR [SO, GT, EQ,
LT]) 1 (Cond == un)) {VISR <vip> = 1; VIINS = [VCINT. VEPC = VPC; (VIMSK <vie> == 1) signal ARM7 interrupt; VP_STATE--VP_IDLE;｝ Other VPC = VPC + 4; Exception; VCINT interrupt VCJOIN (conditional association with ARM7 task)

[0067]

[Table 10]

Assembler syntax: VCJOIN. cond #Offset where cond = {un, lt, eq, le,
gt, ne, ge, ov} Description: If Cond is true, stop execution and, if interrupts are enabled, cause the ARM7 processor to interrupt. Actuation:

Condition: ((Cond == VCSR [SO,
GT, EQ, LT]) l (Cond == un)) ｛VISR <vjp> = 1; VIINS = [VC. JOIN. cond # Offse
t Instruction]; VEPC = VPC; (VIMSK <vje> == 1) signal ARM7 interrupt; VP_STATE - VP_IDLE;} other VPC = VPC + 4; exception; VCJOIN interrupt VMOV (movement)

[0070]

[Table 11]

Assembler syntax: VMOV. dt Rb, Rd where dt = {b, b9, h, w, f}, Rd
And Rb indicate the name of the register. Suffix. w and. f
Indicates the same operation. Auxiliary mode: int8 (b), int9 (b9), in
t16 (h) and int32 (w) Description: The contents of register (Rb) are moved to register (Rd). The field groups indicate source and receive registers as defined in Table 12.

[0072]

[Table 12]

In Table 12, the notation of register groups is as follows: VR: Bank vector register in operation VRA: Alternative bank vector register SR: Scalar register SP: Special register RASR: Recovery address stack (stack) register VAC: Vector accumulator register (Table B.5)
(See Reference.) The vector register cannot be moved to the scalar register by the instruction word VMOV, but can be moved by the instruction word VEXTRT. Table 13 defines the number encoding of the VAC registers.

[0074]

[Table 13]

Operation: Rd = Rb exception; setting an exception status bit in VCSR or VISRC can result in a corresponding exception. Programming Note: Command VMOV is Element Mask
Not affected by (element mask). Since the alternative bank concept is not in the VEC64 mode, the instruction word VMOV
Is not used to move to or from the alternate bank register in VEC64 mode.

[0076]

According to the present invention, a multiprocessor that provides a high degree of processing power, has a large number of built-in separated program threads compatible, and can synchronize or match programs in a simple manner. System can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a multiprocessor shown as an embodiment of the present invention.

FIG. 2 is a block diagram showing an interface between a control processor and a vector processor shown as an embodiment of the present invention.

FIG. 3 is a flow diagram illustrating a method for synchronizing parallel program threads according to an embodiment of the present invention.

FIG. 4 is a flow diagram illustrating another method of synchronizing parallel program threads according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a parallel software method and a sequential software method for the multiprocessor of FIG. 1;

FIG. 6 is a diagram illustrating a parallel software system and a sequential software system for the multiprocessor of FIG. 1;

FIG. 7 is a diagram showing a parallel software system and a sequential software system for the multiprocessor of FIG. 1;

[Explanation of symbols]

 100: Multiprocessor 110: General Processor 115: Extension Register 120: Vector Processor 130: Cache Subsystem 140: System Bus 142: System Timer 146: Bitstream Processor 148: Interrupt Controller 150: System Bus 154: DMA Controller 156: Local Bus interface 180: Cache control 244: Vector register 245: Special register 246: Parallel processing unit 260: Instruction decoder 270: Execution data path 272: Register file 276: Processing unit 280: Record register 290: Read register

 ──────────────────────────────────────────────────の Continued on front page (72) Inventor Le Tron Nguyen United States of America California 95030 Monte Sereno Daniel Place 15095

Claims (14)

[Claims] 1. a first processor; a second processor operable in a first state for executing a sequence of program instructions and a second state in an idle state; and the first and second processors being accessible. And a register coupled to the first and second processors and storing a value indicating whether the second processor is in the first state or the second state. . 2. The method according to claim 1, wherein the first processor includes a first execution data path for operating an operand having a predetermined width that does not exceed a first maximum width, and the second processor includes a first execution data path that does not exceed a second maximum width. 2. The integrated multiprocessor of claim 1, further comprising a second execution data path for enabling operands having a width of ?????, wherein said second maximum width is greater than said first maximum width. . 3. The integrated multiprocessor according to claim 2, wherein the second processor includes a plurality of processing units operated in parallel. 4. The integrated multiprocessor according to claim 3, wherein said second processor has a single instruction multiple data system. 5. A method of operating a multiprocessor, the method comprising: executing a first program thread on a first processor; causing a second processor to disclose a second program thread in response to an instruction executed by the first processor. Executing a loop in the first program thread, wherein the register accessible by the first and second processors in the loop is stored in the first program thread.
Reading on a processor; wherein the second processor is
Recording a value in the register indicating completion of at least a first portion of the program thread; and wherein the second processor
Responsive to the first processor reading the value indicating that a portion has been completed, comprising exiting the loop. 6. The method of claim 1, further comprising the step of executing a portion of the first program thread when the first portion of the second program thread has been completed after exiting the loop. 5. The method according to 5. 7. The method of claim 5, wherein the register stores a value indicating whether the second processor is active or idle. 8. The method of claim 2, wherein the second processor stops execution of the second program thread and records the value in the register during a process of executing a command to put the second processor in an idle state. The method of claim 7, wherein 9. The method of claim 5, wherein the second processor records the value in the register and continuously executes the second program thread. 10. The method of claim 5, wherein said first processor has a narrower data path than said second processor. 11. The method of claim 10, wherein said second processor has a single instruction multiple data scheme. 12. The method of claim 11, wherein the first processor has a general purpose structure. 13. Prior to executing said loop,
The method according to claim 5, wherein the value is recorded. 14. The method of claim 5, wherein the execution of the loop is performed primarily before recording the value and is repeated until after recording the value.