JPH10145226A - Counter output value determining circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit scale forming an entire circuit by inputting a signal directing the value preceding by one to the first value and a signal directing the value next to the last value by two AND gates to a flip flop circuit. SOLUTION: A signal A8, directing the first value to output a signal specifying between from a certain value (the first value) to another certain value (the last value), and a signal A105 specifying the value next to the last value are generated in two 8-input AND gates 2, and the signal A8 is inputted to the set (S) terminal of the RS flip flop circuit 4, and the signal S105 is inputted to a reset (R) terminal. The RS flip flop circuit 4 is a flip flop device, having the set terminal S and the reset terminal R, and if a signal of logic H is added to the S terminal, thereafter its output Q holds the state of logic H, while if the signal of logic H is added to the R terminal, thereafter, the output Q holds the state of logic L. When the S terminal and the R terminal simultaneously turn to logic H, the input to the R terminal is prioritized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for judging a range of an output value designated in advance with respect to an output value of a counter constituted by a digital circuit.

[0002]

2. Description of the Related Art Conventionally, in order to output a signal which designates an output value of a counter by a digital circuit from a certain value (the first value) to another certain value (the last value), a conventional method is used. The method shown in FIG.

FIG. 4 shows a counter output value judging circuit showing an example of generating a control signal to be supplied to a frequency synthesizer circuit of a radio terminal device such as a pager. The circuit is 8
It comprises a bit counter 1, an 8-input AND gate 2 (the same thing has a total of 97 elements), and a 97-input OR gate 3.

[0004] T is a clock signal for the counter 1, Q
0 to Q7 are the outputs of the counter 1, B0 to B7 are the positive phase outputs of the respective stages of the counter 1, C0 to C7 are the inverted outputs of the respective stages of the counter 1, and A8 to A104 are the logical values of the output values of the counter 1. From 8th clock to 10
A signal indicating that it is the fourth clock, Q is a signal A8
論理 Take the logical OR of A104 to 104 from the 8th clock
This is a signal that outputs a logic H during the clock.

In this example, during the operation of the 8-bit counter 1 at the clock T, 10-
It is assumed that an output Q that is output continuously for the time of the fourth clock is required.

A signal A indicating the eighth clock
8 is created by the following logical expression. A8 = (C0 * C1 * C2 * B3 * C4 * C5 * C6 *
C7) The symbol * indicates a logical AND.

By combining 97 such logical expressions, a signal A104 can be obtained from the signal A8, and these signals A8 to A8 are output by the 97-input OR gate 3.
By taking the logical OR of A104, the intended predetermined output signal Q has been obtained.

FIG. 5 is a timing chart showing the above-described series of operations, and also shows a signal A7 indicating the value immediately before the head and a signal A105 indicating the next value after the end.

[0009]

In the prior art described above, the signals A8 to A104 indicating the 8th clock to the 104th clock are separately generated, and the logical OR of these signals is determined. In addition, since the final desired signal Q is obtained, there is a disadvantage that the circuit scale becomes enormous.

Here, when the circuit scale is shown by specific numerical values, an 8-input AND gate 2 corresponds to 5 gates in terms of a basic gate in which one 2-input AND gate is used. The 97-input OR gate 3 corresponds to 60 gates. From these conditions, the number of gates excluding the 8-bit counter 1 represented in the conventional example is (5 × 97) + 60 = 545.
Had become a gate.

[0011]

According to the first aspect of the present invention, a signal designating a first value and a signal designating a last next value are created, and the signals are respectively sent to the RS type flip-flop circuit in the S type. A predetermined output signal is obtained by inputting to a (set) terminal and an R (reset) terminal.

According to the second aspect of the present invention, a signal designating a value immediately before the head and a signal designating the next value at the end are created, and the signals are respectively connected to a D terminal of a D-type flip-flop circuit. A predetermined output signal is obtained by inputting the signal to an R (reset) terminal.

[0013]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. Components and signals having the same functions as those in FIG. 4 are denoted by the same reference numerals.

In the circuit shown in FIG. 1, in order to output a signal designating a range from a certain value (the first value) to another certain value (the last value), a signal A8 indicating the first value and a last signal A8 indicating the last value are output. A signal A105 indicating the next value is generated by two 8-input AND gates 2, the signal A8 is input to the S terminal of the RS flip-flop circuit 4, and the signal A105 is input to the R terminal.

The RS flip-flop circuit 4 is a flip-flop element having a set terminal S and a reset terminal R. When a logic H signal is applied to the S terminal, the output Q keeps a logic H state thereafter. When a signal of logic H is applied to the R terminal, the output Q thereafter maintains the state of logic L. When the S terminal and the R terminal are simultaneously set to logic H, the input to the R terminal has priority. Here, the operation will be described assuming that the initial value of the RS flip-flop circuit 4 is logic L.
The signal A8 indicating the eighth clock is obtained by the logical expression described in the related art.

When this signal A8 is input to the S terminal of the RS flip-flop circuit 4,
Output Q changes to logic H. Since the RS flip-flop circuit 4 keeps the output state until the next signal is input, the output Q remains at logic H.

Here, a signal A105 indicating the 105th clock is generated by the following logical expression. A105 = (B0 * C1 * C2 * B3 * C4 * B5 * B
6 * C7) When this signal A105 is input to the R terminal of the RS flip-flop circuit 4, the output Q of the RS flip-flop circuit 4
Changes from logic H to logic L.

In this way, a predetermined output signal Q shown in FIG. 5 which is completely equal to that described in the prior art can be obtained.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. In FIG. 2, the same components as those in FIG.
The D type flip-flop circuit 5 is used in place of the RS type flip-flop circuit 4 described above.

In the circuit shown in FIG. 2, a signal A7 designating the value immediately before the head and a signal A105 designating the next value at the end are generated by two 8-input AND gates 2, and the signal A7 is D flip-flop. The signal 105 is input to the R terminal, and the clock signal T is input to the clock terminal CK.

The operation will be described below with reference to FIG. 5 and its detailed diagram. First, a signal A7 indicating the seventh clock is generated by the following logical expression. A7 = (B0 * B1 * B2 * C3 * C4 * C5 * C6 *
C7) When this signal A7 is input to the D terminal of the D flip-flop circuit 5, it appears as an output Q at the next eighth clock.

If there is no change in the input of the D terminal, the D flip-flop circuit 5 holds its output state similarly to the RS flip-flop circuit 4, so that the output Q remains at logic H.

Next, when a signal A105 indicating the 105th clock is input to the R terminal of the D flip-flop circuit 5 as in the case of FIG. 1, the output Q immediately returns to logic L.

In the process described above, a predetermined output signal Q completely equal to that described in the prior art can be obtained.

FIG. 3 shows these states in an 8-bit counter 1
2 and the element delay of the D flip-flop 5 are shown in detail.

Although the above embodiment has been described with reference to an 8-bit counter and an 8-input AND gate, it is needless to say that the present invention is not limited to eight.

By the way, in the case of an 8-input AND gate,
The circuit which required 545 gates in the conventional example can be realized by two 8-input AND gates in the present invention.
In the embodiment, when the RS flip-flop circuit is converted into 5 gates, it can be configured with 15 gates.

In the second embodiment, the D flip-flop circuit can be constituted by 18 gates in terms of 8 gates.

[0029]

As described above in detail, according to the present invention, a range from a certain value (the leading value) of the output value of the counter by the digital circuit to another certain value (the last value) is designated. In order to output such a signal, two AND gates are used to input a signal indicating the first value or the value immediately before the first and a signal indicating the next next value to the flip-flop circuit. It has become possible to remarkably reduce the circuit scale constituting the entire circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a timing explanatory diagram of the second embodiment of the present invention.

FIG. 4 is a diagram showing a conventional counter output value determination circuit.

FIG. 5 is a timing chart of a counter output value determination circuit.

[Explanation of symbols]

Reference Signs List 1 8-bit counter 2 8-input AND gate 4 RS-type flip-flop circuit 5 D-type flip-flop circuit A7 to A105 Signal indicating the 7th to 105th clocks Q Output signal S Set terminal RS Reset terminal DD D-type flip-flop circuit D terminal

Claims (3)

[Claims] 1. A circuit for outputting a signal that designates a range from one value of a counter output value to another value by a digital circuit, wherein a signal indicating a leading value and a last next value are provided. And a signal indicating the first value is input to the S terminal of the RS type flip-flop circuit, and the signal indicating the last next value is input to the S terminal of the RS type flip-flop circuit. A counter output value judging circuit, wherein a predetermined output signal is obtained by inputting to an R terminal of an RS type flip-flop circuit. 2. A circuit for outputting a signal which designates a range from one value of a counter output value to another value by a digital circuit. And a signal indicating the next value of the counter is created based on the output value of the counter. A signal indicating the value immediately before the head is input to the D terminal of the D-type flip-flop circuit, A predetermined output signal is obtained by inputting a signal instructing the value of R to the R terminal of the D-type flip-flop circuit. 3. A signal for designating the first value or a value immediately before the first value and a signal for designating the last next value by two AND gates. A counter output value judging circuit according to claim 2.