JPH10145198A - Temperature compensation circuit for delay circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To compensate a temperature of a delay in the delay circuit by observing a change in a signal passing time of a delay element due to a temperature fluctuation, so as to accurately recognize the signal propagation delay time. SOLUTION: In the delay circuit that has a plurality of gates 31-3n, connected in cascade and having a prescribed propagation delay time between input and output and a selector 20 selecting an output from an optional gate among the gates with respect to an input signal, a correlation device 42 conducts correlation arithmetic operation between an output, selected by the selector and an input signal delayed by a flip-flop 41, by a time which is equivalent to a prescribed clock period. A control circuit 43 controls a delay in the delay circuit, based on the result of the correlation arithmetic operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit for selecting outputs from a plurality of delay elements having a predetermined propagation delay time between input and output, and more particularly to a temperature compensation circuit for a delay circuit for performing temperature compensation of the delay circuit. About.

[0002]

2. Description of the Related Art Conventionally, this type of delay circuit has a plurality of cascade-connected delay elements 11 to 1n each having a predetermined propagation delay time between an input and an output called a delay line, as shown in FIG. In some cases, the outputs of the delay elements 11 to 1n are taken into the selector 20. Note that n
Is an arbitrary integer according to the purpose of use of the delay circuit.

In the above delay circuit, each of the delay elements 11 to 1n
Is selected by the selector 20 based on a selector signal for controlling the number of gates to pass, and output, thereby adjusting the propagation delay time of the input signal.

[0004]

However, in the above delay circuit, the propagation delay time of each cascaded delay element is
There is a possibility that it may change due to temperature fluctuations, and therefore, there has been a problem that the signal propagation delay cannot be performed accurately. Therefore, in general, it is conceivable to select and use a delay element having a small change in propagation delay time that satisfies the temperature change within a certain range. When used in a radar apparatus using spread spectrum, which is mounted on a vehicle, the propagation delay time of an input signal (pseudo-noise signal) cannot be accurately adjusted, resulting in a decrease in radar performance. was there.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems. By observing a change in a signal transit time of a delay element due to a temperature change, a signal propagation delay time can be accurately recognized, and a delay amount in a delay circuit can be recognized. It is an object of the present invention to provide a temperature compensation circuit of a delay circuit which can perform the temperature compensation of the above.

[0006]

According to the present invention, there is provided a delay element comprising a plurality of gates which are cascaded in series and have a predetermined propagation delay time between an input and an output. A delay unit comprising a flip-flop for delaying the input signal by a time corresponding to a predetermined clock cycle. An operation unit including a correlator that performs a correlation operation between the output selected by the selector and the signal delayed by the flip-flop; and a control circuit that controls a delay amount of the delay circuit based on the correlation operation result. A temperature compensation circuit of a delay circuit including a temperature compensation unit having a delay amount control unit.

That is, the temperature compensating means is provided by a signal for controlling the number of gates determined based on the correlation between the output of the predetermined delay amount selected by the selector and the input signal delayed by the flip-flop. The temperature of the delay circuit is compensated by controlling the delay amount of the delay circuit. According to claim 5, the temperature compensating means detects a pulse edge from the pulse generator, a pulse generator for generating a pulse for a predetermined time, a selector for selecting the generated pulse as an input signal of the delay element. And, while monitoring the state of the output selected by the selection means, based on the monitored output state when detecting the rectangular wave edge,
A control circuit for controlling a delay amount of the delay circuit.

That is, the delay amount of the delay circuit is determined by a signal controlling the number of gates determined based on the pulse edge detection from the pulse generator and the output state of the predetermined delay amount selected by the selection means. To perform temperature compensation of the delay circuit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A temperature compensation circuit for a delay circuit according to the present invention will be described with reference to FIGS. FIG.
FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of a delay circuit and a temperature compensation circuit according to the present invention. In the figure, a delay circuit 30
Is composed of n gates 31 to 3n. The temperature compensation circuit 40 performs a correlation operation between the delayed input signal and the output signal selected by the selector 20 with the flip-flop 41 for delaying the input signal by a clock. Correlator 4 to perform
2 and a control circuit 43 that outputs a select signal for controlling the number of gates passed to the selector 20 and controls the delay amount of the delay circuit 30 based on the calculation result of the correlator 42.

In this embodiment, the input signal is composed of a pseudo-noise signal (hereinafter referred to as "PN code"), and is used for, for example, a radar apparatus using spread spectrum mounted on an automobile and used for despreading. PN code to delay circuit 3
The case of delaying by a predetermined amount at 0 will be described below. In this embodiment, in order to satisfy the distance accuracy (1 m), the delay circuit 3
A device whose delay time t per gate of 0 is about 6 ns is selected. Also, the number of gates must satisfy n × t ≧ rough delay amount. In the present embodiment, the rough delay amount is a time corresponding to one chip of a PN code operating at 24 MHz, that is, 41. Since it is set to 6 ns, n ≧ 7 is required. In this embodiment, n is set to 14 in consideration of the margin for temperature compensation.

The input receiving PN code is supplied to the selector 2
0, the gate 31, and the flip-flop 41. The PN code input to the gate 31 is output by the gate 31 after being delayed by the time required for passing through the gate, and is supplied to the selector 20 and the gate 32. Similarly, after the output signal delayed by the gate is supplied to the selector 20 and the next-stage gate, it is supplied to the selector 20 after passing through the final-stage gate 3n, that is, the gate 314.

FIG. 2 is a waveform diagram of the PN code of each of the representative portions of the circuit shown in FIG. 2, (a) is an input PN code, (b) is an output signal passing through the gate 31, (c) is an output signal passing through the gate 32, (d)
Is the output signal passing through the gate 36, and (e) is the output signal
, An output signal passing through the gate 314, and (g) an output signal from the flip-flop 41. FIG. 2 shows an example of a PN code composed of 255 chips as one epoch.

As described above, the selector 20 receives the input PN code, the output signals from the gates 31 to 314, and the select signal from the control circuit 43. The clock input to the flip-flop 41 is P
This is the same as the reference clock used to generate the N code, and in this embodiment, is a signal having a clock frequency of 24 MHz. The output signal of the flip-flop 41 has a time longer than the propagation delay time of one gate stage with respect to the input signal and shorter than the propagation delay time of the maximum number of gate stages (14 stages in the embodiment). In the case of the example, the correlator 4 delays a time corresponding to one clock cycle by 41.6 ns, that is, one chip of the PN code (see FIG. 2G).
2 has been entered.

The correlator 42 receives the gate-delayed PN code output from the selector 20 and the flip-flop 4.
A PN code delayed by a time corresponding to one chip output from 1 is taken in, an autocorrelation value of the two PN codes is calculated, and the correlation value is output to the control circuit 43. Note that the PN code has autocorrelation, and when the phases are matched, the autocorrelation value is maximum, a correlation peak appears in a range of ± 1 chip before and after, and becomes a minimum correlation value in all other cases. Further, a correlation can be obtained at a shift of n periods (n is an integer). Therefore, the correlator 42 selects the selector 2
An operation of multiplying the PN code from 0 by the PN code delayed by one chip from the flip-flop 41 is performed.

The control circuit 43 outputs a select signal to the selector 20 on the basis of the input correlation value.
It controls the number of PN codes output from 0 through the gate. That is, when performing temperature compensation, the control circuit 4
3 is the selector 2 so that the input correlation value is maximized.
0 is controlled. In the case where the control circuit 43 operates as an actual delay circuit, the control circuit 43 sets m (m is an integer) to 1 through m when the number of gate passage stages at which the autocorrelation is maximized is 1 to 1
Within the range of m, the number of successive passage stages is controlled.

By this control, the selector 20 outputs only the PN code that has passed through the predetermined gate. Then, the control circuit 43 sets the average delay time per gate to 41.6 ns {7} from the number and time of gates at the time of the maximum autocorrelation value, that is, 7 stages and 41.6 ns in the embodiment.
The delay is obtained at 5.94 ns, and the delay amount in the delay circuit 30 is subjected to temperature compensation.

Therefore, in the present embodiment, even if a temperature fluctuation occurs, the PN code is shifted by one chip by the reference clock, and the autocorrelation with the output signal is calculated to calculate the 1-bit signal due to the temperature fluctuation.
Since the average delay time per gate can be obtained, it is possible to accurately recognize the signal propagation delay time and perform temperature compensation for the delay amount in the delay circuit. In this embodiment, a gate element which is a logic circuit is used as the delay element. For this reason, the output corresponding to the input does not directly pass the input signal, but uses the output from the power supply as the output signal, so that the input / output relationship is digitally processed.
Therefore, the input signal is not attenuated no matter how many stages the delay element passes through, so that the signal level can be prevented from lowering, and the received signal can be efficiently despread by the receiving PN code in the radar device. Further, the delay circuit constituted by the gate element not only eliminates the need for a gain control circuit for compensating for the attenuation, but also allows the delay circuit to be incorporated into an integrated circuit, so that there is no need to separately provide an external circuit, thereby saving space. And cost reduction can be achieved.

In the present embodiment, if the delay time per gate is 6 ns, it is sufficient if the number of gate passes is seven, but even if the gate delay fluctuates to 4 ns due to temperature fluctuation, the selector Since the signal output from the control circuit is observed, correction is possible, and the number of gate passages is controlled by the select signal from the control circuit so that the number of gate passages becomes 10 stages as the delay amount per gate is reduced. This makes it possible to perform temperature compensation.

FIG. 3 is a circuit diagram showing another example of the circuit configuration of the delay circuit and the temperature compensation circuit according to the present invention. In the figure, a temperature compensating circuit 45 outputs a selector 46 for switching input signals, a pulse generator 47 for generating a pulse signal, and a select signal for controlling the number of gates passed to the selector 20. And a control circuit 48 for controlling the amount of delay of the delay circuit 30 based on the output state of the output signal selected at 20. Since the selector 20 and the delay circuit 30 have the same configuration as that shown in FIG. 1, they are represented by the same reference numerals.

The selector 46 receives the PN code for reception and the output from the pulse generator 47. When the selector 46 operates as a normal delay circuit, the selector 46 operates according to a control signal input from the control circuit 48. The operation is controlled to output the receiving PN code. Output PN for reception
The code is supplied to the selector 20 and the gate 31 as in FIG. 1, and then output from the selector 20 as an output signal. When performing the operation of temperature compensation, the selector 46 operates according to a control signal input from the control circuit 48.
The operation is controlled so as to output a pulse signal from the pulse generator 47.

The clock input to the pulse generator 47 is a reference clock used to generate a PN code, as in FIG. 1 (see FIG. 4B), and has a frequency of 24 MHz.
This is the signal of z. The pulse generator 47 is in a reset state while the reset signal from the control circuit 48 is valid (in this embodiment, low level as shown in FIG. 4A), and the output to the selector 46 is low level. (Fig. 4
(C)). Also, in the selector 46, when the reset signal becomes invalid (in this embodiment, high level as shown in FIG. 4A) and the clock is input once,
The output to the selector 46 is set to a high level. Next, when a clock is input in this state, a low level is output to the selector 46 again. This pulse signal is supplied to the selector 46
And to the control circuit 48.

In the state where temperature compensation is performed, the selector 46
Operates to output a pulse signal from the pulse generator 47 in accordance with a control signal input from the control circuit 48, and the subsequent operation of providing a delay is the same as that when a receiving PN code is input. That is, the selector 20 outputs an output signal in which the output of the pulse generator 47 is given the delay amount set by the control circuit 48.

FIGS. 4D to 4G are waveform diagrams of typical examples of the output signal. 4, (d) is an output signal passing through the gate 31, (e) is an output signal passing through the gate 32, (f) is an output signal passing through the gate 33, (g) is passing through the gate 37. Output signal. After detecting the edge (falling edge in this embodiment) of the pulse signal output from the pulse generator 47, the control circuit 48 immediately monitors the output signal output from the selector 20. That is, the control circuit 48 checks whether the state of the output signal is high level or low level at the time of detecting the edge of the pulse signal, and outputs the control signal to the selector 20 if the state of the output signal is high level. After controlling to increase the number of stages by one, the pulse generator 47 is again activated.
Is reset and the same operation as above is repeated. The control circuit 48 divides the time 41.6 ns corresponding to the clock cycle by the number of gate passage stages 7 at that time when the state of the output signal is recognized as the low level at the time of detecting the edge of the pulse signal. An average delay time per gate is obtained, and the delay amount in the delay circuit 30 is subjected to temperature compensation.

Therefore, in the present embodiment, even if a temperature variation occurs, the edge of the pulse generated by the reference clock is detected, and the output level state of the output signal from the selector at that time is monitored, and the output level of the output signal corresponds to the reference clock cycle. Since the average delay time per gate due to temperature fluctuation can be obtained by calculating the number of gates for the time required, the signal propagation delay time is accurately recognized, and the delay amount in the delay circuit is temperature-compensated. be able to.

In this embodiment, the case where the PN code is used for the input signal has been described. However, the present invention is not limited to this, and is used for temperature compensation of a delay circuit using a signal other than the PN code for the input signal. It is also possible to provide a temperature compensation circuit having a wide versatility. Further, the temperature compensation circuit according to the present invention can also be used for a delay circuit using a delay element other than a gate, for example, a delay circuit using a delay line as shown in the conventional example.

[0026]

As described above, according to the present invention, a plurality of delay elements which are connected in series and have a predetermined propagation delay time between input and output, and an arbitrary one of the delay elements for the input signal. A delay unit having a selection unit that selects an output from the delay element, wherein a delay unit that delays the input signal by a time corresponding to a predetermined clock cycle;
An operation unit that performs a correlation operation between the output selected by the selection unit and the signal delayed by the delay unit; and a delay amount control unit that controls a delay amount of the delay circuit based on the result of the correlation operation. Since the temperature compensating means is provided, it is possible to accurately recognize the signal propagation delay time by observing the change in the signal transit time of the delay element due to the temperature fluctuation, and perform the temperature compensation of the delay amount in the delay circuit.

According to a fifth aspect of the present invention, the temperature compensating means includes a rectangular wave generating section for generating a rectangular wave for a predetermined time, a selecting section for selecting the generated rectangular wave as an input signal of the delay element, An edge detection unit that detects an edge of a rectangular wave from the unit, a monitoring unit that monitors the state of the output selected by the selection unit, and the monitored output when the edge detection unit detects a square wave edge. A delay amount control unit for controlling the delay amount of the delay circuit based on the state, so that the signal propagation delay time can be accurately recognized, and the temperature of the delay amount in the delay circuit can be compensated;
It can be used for temperature compensation of a delay circuit using a signal other than the PN code.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a circuit configuration of a delay circuit and a temperature compensation circuit according to the present invention.

FIG. 2 is a waveform diagram of a PN code of each of the representative portions of the circuit shown in FIG.

FIG. 3 is a circuit diagram showing another example of the circuit configuration of the delay circuit and the temperature compensation circuit according to the present invention.

4 is a waveform diagram of a PN code of each of the representative portions of the circuit shown in FIG.

FIG. 5 is a circuit diagram showing a conventional circuit configuration of a delay circuit.

[Explanation of symbols]

 20, 46 selector 30 delay circuit 31 to 3n gate 40, 45 temperature compensation circuit 41 flip-flop 42 correlator 43, 48 control circuit 47 pulse generator

Claims (6)

[Claims] 1. A plurality of delay elements connected in series and having a predetermined propagation delay time between input and output, and selection means for selecting an output from an arbitrary one of the delay elements with respect to an input signal. And a temperature compensating means for controlling a delay amount of the delay circuit to perform temperature compensation based on a relationship between the input signal and an output selected by the selecting means. Temperature compensation circuit for the delay circuit. 2. The temperature compensating unit includes a delay unit that delays the input signal by a predetermined time, and an arithmetic unit that performs a correlation operation between the output selected by the selecting unit and the signal delayed by the delay unit. 2. The temperature compensation circuit according to claim 1, further comprising: a delay amount control unit configured to control a delay amount of the delay circuit based on a result of the correlation operation. 3. The delay unit according to claim 2, wherein the delay unit converts the input signal into a delay longer than a propagation delay of one stage of the connected delay element and shorter than a propagation delay of a maximum number of stages of the connected delay element. The delay amount control unit recognizes the number of stages of the delay element through which the signal propagates within the predetermined time, and based on the correlation operation result and the recognized number of stages, 3. The temperature compensation circuit for a delay circuit according to claim 2, wherein an average propagation delay time is obtained and a delay amount of the delay circuit is controlled. 4. The temperature compensation circuit for a delay circuit according to claim 1, wherein said input signal comprises a pseudo noise signal. 5. The apparatus according to claim 1, wherein the temperature compensating unit includes: a rectangular wave generating unit configured to generate a rectangular wave for a predetermined time; a selecting unit configured to select the generated rectangular wave as an input signal of the delay element; An edge detection unit that detects an edge of the rectangular wave; a monitoring unit that monitors the state of the output selected by the selection unit; and a monitor based on the monitored output state when the edge detection unit detects a square wave edge. 2. The temperature compensation circuit for a delay circuit according to claim 1, further comprising: a delay amount control unit configured to control a delay amount of the delay circuit. 6. The rectangular wave generator, wherein the rectangular wave is longer than a propagation delay time of one stage of the connected delay element and is longer than a propagation delay time of a maximum stage of the connected delay element. The delay amount control unit recognizes the number of stages of the delay element through which the signal propagates within the predetermined time, and, based on the number of stages recognized as the output state, per delay element stage. 6. The temperature compensation circuit for a delay circuit according to claim 5, wherein an average propagation delay time of the delay circuit is obtained and a delay amount of the delay circuit is controlled.