JPH10135182A - Method and device for removing resist - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of popping without deteriorating the cost efficiency, throughput, and substrate selectivity at the time of removing the hardened surface layer part of a resist having a hardened surface layer, which is hardened by ion implantation by removing the hardened surface layer through a low-temperature ion-impact treating process. SOLUTION: At the time of removing a hardened surface layer part 4 of a resist 2 having a hardened surface layer which is hardened by ion implantation, the part 4 is removed through a low-temperature ion-impact treating process. The process is one mode of the down-flow plasma treating process and, in the process, the surface of a semiconductor substrate 1 composed, for example, of silicon is treated by generating ions while a substrate 1 is maintained at a relatively low temperature of 120 deg.C or lower, preferably, <=100 deg.C and giving acceleration to the ions, so that the ions can come into collision with the surface of the substrate 1 at high speeds by appropriately impressing a bias upon the ions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of removing a resist film whose surface has been hardened by high dose ion implantation and a resist removing apparatus.

[0002]

2. Description of the Related Art In a semiconductor manufacturing process, a photoresist used as a mask for dry etching or ion implantation is frequently removed and removed. In recent years, the semiconductor manufacturing process has shifted from a wet process to a dry process, and an ashing process using oxygen plasma has become the mainstream in stripping resist.

[0003] This ashing processing method proceeds relatively easily with respect to a resist mask used for ordinary dry etching, but is used for high-dose ion implantation. As a result, a layer was formed, and the cured layer of the resist mask could not be easily removed by a normal processing method.

Further, in the case of a resist mask in which the above-described cured layer is formed on the surface of the resist mask, popping occurs when any kind of heat is applied, and the popping adheres to the semiconductor device or causes the inner wall of the chamber to become popped. As a result, the quality and performance of the semiconductor device are adversely affected, so that there is a problem that it takes more time to process the residue.

That is, since popping residues significantly reduce the yield of semiconductor devices, it is necessary to avoid popping during ashing or to remove popping residues. Popping is considered to occur when the surface hardened layer of the resist mask pops out and its residue is scattered over a wide area on the wafer, and is caused by bumping of the residual solvent contained in the non-hardened layer.

In other words, even if the ashing speed of the hardened layer is low, if the temperature is raised to increase the ashing speed as in the case of normal ashing, popping occurs due to that, so that processing at a high temperature is difficult. is there. As another method for avoiding popping, see, for example,
As shown in FIG. 5326 and as illustrated in FIG. 3, as a result of ion implantation of appropriate ions 5 at a high dose, FIG.
As shown in FIG. 3A, a resist mask 2 composed of a cured layer 4 and an uncured layer 3 is formed on a semiconductor substrate 1, and the resist mask 2 is first made of an oxygen and fluorine based material as shown in FIG. A method is known in which the resist cured portion 4 is removed by using a mixed gas of the following method, and then the remaining resist layer 3 is removed by using oxygen plasma as shown in FIG.

As shown in Japanese Patent Application Laid-Open No. 64-48418 and illustrated in FIG. 4, plasma etching using a reactive gas consisting of hydrogen gas without oxygen, that is, RIE using H2 plasma. As shown in FIG. 3A, a resist mask 2 composed of a hardened layer 4 and an uncured layer 3 is formed by a reactive ion etching) as shown in FIG.
First, the resist mask 2 is formed on the substrate shown in FIG.
As shown in FIG. 4, a method of removing the resist hardened portion 4 by plasma etching using nitrogen ions and hydrogen ions, and then, as shown in FIG. 4C, removing the remaining resist 3 by using downstream ashing. Are known.

In the former, the activation energy of the surface hardened layer is lowered by fluorine radicals to increase the ashing speed, and only oxygen gas is used from the middle so as not to etch the underlayer. The latter is based on the active species in the H2 plasma. The chemical bond of the surface hardened layer is broken, the volatile hydride is generated by combining with the dopant, the surface hardened layer is removed, and downflow ashing is switched halfway to prevent damage.

On the other hand, as a method for removing popping residues,
Is disclosed in, for example, JP-A-6-104223.
As shown in FIG. 5, a suitable ion 5, for example,
As a result of ion implantation of arsenic at a high dose, as shown in FIG.
Resist mask composed of cured layer 4 and uncured layer 3
2 is formed on the semiconductor substrate 1 and the resist mask 2
With plasma 13 comprising oxygen and nitrogen ions
After performing the ashing process, as shown in FIG.
Residue 15 adhered to substrate 1 due to occurrence of tapping
It became a state. The residue 15 is shown in FIG.
O_Two/ S_TwoF _Two By plasma treatment using mixed gas
The oxide of the dopant contained in the popping residue is
Has been proposed to decompose and remove
I have.

This method makes it easy to control the amount of F * (fluorine radical) generated in the plasma by using S ₂ F ₂ instead of a fluorocarbon compound, and to prevent the base from being etched due to excess F * (fluorine radical). I have.

[0011]

However, each of the above methods has its own problems. That is, the first problem is that in the above two conventional methods using a fluorine-based gas, oxygen gas alone is used in the middle, or excess F * (fluorine radical) is prevented by using S ₂ F ₂ . However, it is impossible to completely prevent the fluorine-based gas from damaging the base.

That is, although fluorine radicals are effective in removing a hardened layer, they have a disadvantage of shaving off an insulating oxide film formed on a substrate of a semiconductor device. The second problem is that the conventional method combining RIE and downstream ashing has the disadvantage that the RIE apparatus and the ashing apparatus are separately required, which increases the cost and lowers the throughput.

An object of the present invention is to improve the above-mentioned drawbacks of the prior art, and to remove a resist having a hardened layer formed on the surface thereof due to ion implantation performed at a high dose. It is another object of the present invention to provide a resist removing method and a resist apparatus capable of avoiding popping without lowering the underlayer selectivity.

[0014]

In order to achieve the above-mentioned object, the present invention employs the following basic technical structure. That is, as a first aspect according to the present invention, in a manufacturing process of a semiconductor device, when a hardened layer portion of a resist whose surface layer is hardened by ion implantation is removed by an ashing method, a low-temperature ion bombardment process is performed. A second method according to the present invention is a method of removing a surface hardened layer of the resist through a method, wherein a part of the surface layer is ion-implanted in a semiconductor device manufacturing process. A resist removal device used for removing a resist provided on a semiconductor substrate surface having a cured resist layer by an ashing method,
The resist removal apparatus includes a sealed processing space portion containing a gas body capable of generating ions, ion generating means for ionizing the gas body in the sealed processing space portion, and a bias applied to ions generated in the ion generating means. And a temperature control means for controlling the temperature of the semiconductor substrate.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to solve the above-mentioned problems in the prior art, the resist removing method of the present invention first performs a down-flow plasma treatment using highly active ions such as fluorine. That is, breaking down the interlayer insulating film and the like of the semiconductor substrate, and performing downflow plasma processing at a high temperature will cause popping,
In order to avoid these problems and efficiently decompose the chemical bond of the hardened layer formed on the resist mask layer to generate volatile hydrides and remove the hardened layer, low temperature without using fluorine in particular While employing the ion bombardment method,
After the hardened layer is removed, there is no fear that popping will occur. Therefore, the non-hardened layer is peeled off by using a normal down-flow plasma treatment or especially a high-temperature down-flow plasma treatment.

In particular, the high-speed down-flow plasma treatment makes it possible to increase the removal rate (rate) of the resist layer. In the present invention, the above two steps are performed in one step or in one apparatus from the viewpoint that it is necessary to improve productivity and reduce production cost. Basically, the steps are to perform down-flow plasma processing, and use the same down-flow plasma processing apparatus.

[0017]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a resist removing method and a resist removing apparatus according to an embodiment of the present invention. FIG. 1 is a diagram showing an example of the configuration of a specific example of a resist removing method according to the present invention, and FIG. 6 is a flowchart showing the steps of a process of the resist removing method according to the present invention. As is apparent, as a first specific example of the resist removing method according to the present invention, in a manufacturing process of a semiconductor device, an ashing method is applied to the cured layer portion 4 of the resist 2 whose surface layer is cured by ion implantation. 1 shows a method of removing the resist by removing the surface hardened layer 4 of the resist 2 through a low-temperature ion bombardment process.

That is, in the first step of the present invention, the hardened surface layer 4 formed on the surface layer of the resist layer portion 2 of the semiconductor device is efficiently removed while avoiding the above problem. This method is characterized by employing low-temperature ion bombardment. The low-temperature ion bombardment process according to the present invention is one form of a down-flow plasma process, as described later.
In a state where the temperature is maintained at a temperature equal to or lower than 0 ° C., ions are generated, and an appropriate bias is applied to the ions to accelerate the ions so as to collide with the surface of the semiconductor substrate 1 at high speed. The process is performed while giving the

That is, the low-temperature ion bombardment treatment step in the present invention is performed in the step of maintaining the temperature of the substrate 1 constituting the semiconductor device at a low temperature, the ion generation step, and the ion generation step. And a step of applying a bias to the ions. In the present invention, the step of maintaining the temperature of the substrate 1 at a low temperature may be configured to control the temperature of the substrate 1 to, for example, 120 ° C. or lower, as described above. desirable.

The ion generating gas used in the ion generating step in the present invention does not contain the fluorine gas as described above, and a relatively large ionizable gas can be used. For example, oxygen gas,
It is preferable that the gas is one selected from a mixed gas of oxygen and nitrogen, argon, and helium. Furthermore, in the low-temperature ion bombardment treatment according to the present invention, it is necessary to apply a bias to the ions.
It is desirable that a predetermined electric field is formed from the ion generating means toward the semiconductor substrate 1. Specifically, an electrode means 25 to which an appropriate voltage is applied is disposed below the semiconductor substrate. It is desirable to do.

The degree of bias application by the bias generation means is not particularly limited, and an appropriate bias is applied depending on the type of gas used, the thickness of the surface hardened layer of the resist layer, the ion generation conditions of the ion generation means, and the like. The conditions are set. The above-described low-temperature ion bombardment process according to the present invention is desirably performed using the principle of a downflow plasma process in a predetermined closed space area, for example, a well-known inductively coupled plasma ashing apparatus. It is possible to use

Next, in the resist removing method according to the present invention, the semiconductor substrate 1 is removed by the above-described method.
After the surface hardened layer 4 formed on one main surface is removed, a second step described below is executed as a step of removing the remaining unhardened layer 3 which is the resist layer 3. That is, in the process of manufacturing a semiconductor device, when the hardened layer portion of the resist whose surface layer is hardened by ion implantation is removed by an ashing method, the surface hardened layer of the resist is removed through a low-temperature ion bombardment process. Subsequent to the first step, a second step of removing the non-cured layer 3 of the resist after the surface cured layer 4 is removed through a down-flow plasma processing step is executed.

In the present invention, the second step is preferably a high-temperature down-flow plasma treatment.
In such high-temperature downflow plasma processing, it is desirable to control the temperature of the semiconductor substrate 1 to be set to, for example, 120 ° C. or higher. The means for maintaining the temperature of the semiconductor substrate 1 at a high temperature is not particularly limited. For example, an appropriate heating means such as a heating lamp or a heating panel may be provided near the semiconductor substrate 1 or the semiconductor substrate 1 may be provided. A means for heating the supporting member supporting the first member 1 may be provided.

Control of the temperature of the semiconductor substrate 1 is easily performed by controlling the amount of heat generated by the heat generating means. However, the supporting means for supporting the semiconductor substrate 1 is heated to a predetermined temperature. In addition, the temperature of the semiconductor substrate 1 can be controlled by adjusting the distance of the semiconductor substrate 1 from the supporting means by appropriate means.

In the present invention, as described above, it is desirable that the above two steps are continuously performed in the same processing area or in the processing apparatus. The basic principle is to use the same ions. Therefore, it is preferable that the same ions are used in the first and second steps. In the present invention, the surface hardened layer 4 of the resist 2 generated by the high dose ion implantation is used.
Is removed, popping does not occur even at high temperatures,
It also depends on the fact that a high rate can be obtained and that the surface hardened layer 4 can be gradually formed at a high rate even at a low temperature if a bias is applied.

However, if a bias is applied in the second step, there is a problem that the substrate 1 is damaged. Therefore, the bias is applied to the semiconductor substrate 1 only in the first step, so that the substrate 1 is not affected. The resist hardened layer 4 is removed by low-temperature ion bombardment, and in the second stage, the non-hardened layer 3 is peeled off by high-temperature down-flow plasma without performing a bias treatment, thereby popping without damaging the semiconductor substrate 1. A method of removing the resist layer at a high rate can be obtained while avoiding it. If a high-density plasma is used for this plasma source, a higher rate can be obtained.

Further, in order to rapidly raise the wafer temperature in the ashing of the non-cured layer 3, the switching from the low temperature to the high temperature is not performed by changing the set temperature of the heater, but by raising and lowering pins 11 on which the wafer is mounted, which will be described later, or Lamp 2
7 is desirably performed. The procedure of the resist removing method according to the present invention will be described with reference to the flowchart of FIG. 6. First, after the start, in the step (1), the first
Is performed in step (2) to determine whether or not the surface hardened layer 4 remains. If YES, the process returns to step (1) and returns to step (1). If the impact processing operation is continued and NO,
Proceeding to step (3), the second step, a downflow plasma processing step, is performed.

In step (4), the non-cured layer 3
It is determined whether or not is left. If YES, the process returns to step (3) to continue the down-flow plasma process, and if NO, END. In the resist removing method according to the present invention, it is determined whether or not the surface hardened layer 4 has been completely removed, or whether or not the non-hardened layer 3 in the resist layer has been completely removed. Although the method is not particularly limited, for example, the thickness of each of the surface hardened layers 4 and the thickness of the non-hardened layer 3 formed on the semiconductor substrate 1 to be processed in advance is measured by constantly measuring the respective thicknesses. A scheduled time for removing the surface cured layer 4 and the non-cured layer 3 from a predetermined removal rate (rate) of each layer, and monitor the processing time;
Alternatively, a predetermined processing operation can be stopped and the next processing operation can be started by, for example, catching a change in the color of the plasma during the plasma processing with the naked eye or using spectroscopic analysis means.

Next, a description will be given of a resist removing apparatus according to the present invention. FIG. 7 is a view showing a configuration of a specific example of a resist removing apparatus 20 according to the present invention. In a manufacturing process, a semiconductor substrate 1 having a resist layer 4 having a part of its surface layer hardened by ion implantation.
A resist removing device 20 used for removing the resist 2 provided on the surface of the substrate by an ashing method, the resist removing device 20 includes a sealed processing space portion 21 containing a gas body capable of generating ions, Ion generating means 2 for ionizing a gas in the closed processing space 21
2. a bias unit 26 for applying a bias to the ions 24 generated by the ion generating unit 22; a unit 28 for holding the semiconductor substrate 1; and a temperature control unit 30 for controlling the temperature of the semiconductor substrate 1. The configured resist removing device 20 is shown.

In the resist removing apparatus 20 according to the present invention, an appropriate vacuum state is formed in the sealed processing space 21, and a gas capable of generating ions 24 is formed in the sealed processing space 21. The body is filled with one gas selected from oxygen gas, a mixed gas of oxygen and nitrogen, argon, and helium. The configuration of the ion generating means 22 for ionizing in the present invention is not particularly limited as long as it has a function of ionizing a gas in the closed processing space 21. For example,
As shown in FIG. 7, a configuration in which an appropriate coil 22 is arranged may be adopted, and the coil 22 is configured to supply a high-frequency current from an appropriate high-frequency generation unit 23.

Further, the bias means 26 used in the present invention is used to add the ions 24 in the resist removing apparatus in such a direction as to accelerate the ions 24 toward one main surface of the semiconductor substrate 1. It is desirable that the device be configured so as to form a specific electric field. For example, the device may be configured by an appropriate electrode 25 and an appropriate power supply 31 (for example, a DC power supply).

Further, the temperature control means 30 used in the present invention is desirably constituted by a heat source for directly or indirectly heating the semiconductor substrate 1. Alternatively, it is preferable that the heating element 27 or the heat source 25 also serving as an electrode be constituted. Further, as another specific example of the temperature control means 30, as shown in FIG.
It may be configured to control a mechanism for driving a means 32 for arbitrarily adjusting the distance between the semiconductor substrate 1 and an appropriate heat source 25 also serving as an electrode, and more specifically, Is configured such that a supporting member 28 for supporting the semiconductor substrate 1 can be moved up and down by a pin mechanism 32 which moves up and down by an appropriate up-and-down mechanism, and if it is desired to maintain the temperature of the semiconductor substrate 1 at a relatively low temperature, In order to maintain the semiconductor substrate 1 at a certain distance from the heating heat source 25 heated at the temperature of the above, and to maintain the temperature of the semiconductor substrate 1 at a relatively high temperature, As shown in FIG. 8, by lowering the support member 28 and arranging it so as to be close to the heat source 25, the semiconductor substrate 1
Temperature can be adjusted.

In the resist removing apparatus 20 according to the present invention, when the hardened layer portion 4 of the resist 2 having the hardened surface layer is removed by the ashing method, the ion generating means 22 and the biasing means 26 are used. While being driven, the temperature control means 30 is driven and controlled to maintain the temperature of the semiconductor substrate 1 at a relatively low temperature, and a low-temperature ion bombardment process is performed.

On the other hand, in removing the resist 2 after the cured layer portion 4 has been removed, the ion generating means 22 is driven and the temperature control means 30 is removed.
Is driven and controlled to maintain the temperature of the semiconductor substrate 1 at any one of a relatively low temperature and a relatively high temperature,
Either a down-flow plasma process or a high-temperature down-flow plasma process is performed.

In this step, the above-mentioned bias means 26 is used.
Is controlled so as not to operate, and since the temperature of the semiconductor substrate 1 may be set to a high temperature, the temperature control means 30 is operated to lower the pin mechanism 32 to the lowest point. Thus, the supporting member 28 for supporting the semiconductor substrate 1 is brought into direct contact with the heating means 25 also serving as an electrode portion.

FIG. 8 shows an outline of the resist removing apparatus 20 in such a state. That is, according to the present invention, if the surface hardened layer generated by ion implantation is removed, popping does not occur even at a high temperature and a high rate can be obtained, and if a bias is applied, a high rate can be obtained at a low temperature. Utilize the facts that say. However, biasing creates another problem of damaging the substrate, so biasing the wafer only in the first stage
The resist cured layer 4 is removed by low-temperature ion bombardment at a level that does not affect the substrate, and the non-cured layer 3 is peeled off by high-temperature downflow plasma in the second stage, thereby avoiding popping without damaging the substrate. You can get a rate. If a high-density plasma is used for this plasma source, a higher rate can be obtained.

Further, since the temperature of the wafer is rapidly increased in the ashing of the non-cured layer 3, switching from the low temperature to the high temperature is not performed by changing the set temperature of the heater, but by raising or lowering the pins on which the wafer is mounted or irradiating the lamp. It is desirable to do this. Hereinafter, if the specific conditions for performing the resist removing method according to the present invention are described, the basic conditions of the resist removing method according to the present invention are as follows.
In the ashing of a photoresist film whose surface is altered and hardened, first, the wafer 1 is heated at a temperature ranging from room temperature to 100 ° C.
Is applied with a bias of 100 to 300 W, and the surface hardened layer 4 is removed by oxygen ion bombardment. Thereafter, the uncured layer 3 is removed by a downflow plasma method at a wafer temperature range of 150 to 300 ° C. while the wafer 1 is held in the same ashing chamber.

The method of removing a resist according to the present invention will be described including more detailed conditions. That is, first, arsenic is ion-implanted into a photoresist 2 having a thickness of about 1 μm at a dose of 5 × 10 ¹⁵ cm ⁻² at 60 eV to form a non-cured surface hardened layer 4 as shown in FIG. A resist layer 2 including the layer 3 is formed. Next, when the surface hardened layer 4 of the semiconductor substrate 1 having the resist layer 2 is subjected to ashing treatment and the surface hardened layer 4 is removed, an inductively coupled plasma ashing apparatus is used. First, RF power: 900 W, bias : 200W, pressure: 1.1 Torr, oxygen gas O ₂ : 3750 sccm,
Stage temperature: 100 ° C (wafer temperature 100 ° C,
The removal rate of the non-hardened layer, that is, the rate is about 4 μm / min.) By removing the hardened layer 4, as shown in FIG.
The surface hardened layer 4 is removed, and the semiconductor substrate 1 having a resist layer composed of only the non-hardened layer 3 is formed.

Since the high-density plasma is biased, a high rate can be obtained only with oxygen gas. After that, while holding the wafer in the same ashing chamber, downflow plasma with a bias of 0 W is applied, and the lamp 27 is irradiated (wafer temperature 150 ° C., uncured layer rate about 3 μm /
min) As shown in FIG. 1C, the uncured layer 3 is removed.

Next, another embodiment of the present invention will be described. First, arsenic is added to a photoresist 2 having a thickness of about 1 μm.
By performing ion implantation at 60 eV with a dose of 5 × 10 ¹⁵ cm ⁻² , a resist layer 2 composed of a hardened surface layer 4 and a non-hardened layer 3 is formed as shown in FIG. Next, when the surface hardened layer 4 of the semiconductor substrate 1 having the resist layer 2 is subjected to ashing treatment and the surface hardened layer 4 is removed, an inductively coupled plasma ashing apparatus is used. First, RF power: 900 W, bias : 200W, pressure: 1.1Torr,
The wafer is lifted by the pins 32 under the conditions of oxygen gas O ₂ : 3750 sccm, stage temperature: 200 ° C. (wafer temperature 80 ° C., the cutting speed of the non-cured layer 3, ie, the rate
μm / min) By removing the surface hardened layer 4,
As shown in (B), the surface hardened layer 4 is removed, and the semiconductor substrate 1 having a resist layer composed of only the non-hardened layer 3 is formed.

After that, while holding the wafer in the same ashing chamber, a down flow plasma with a bias of 0 W is applied, the pins 32 are lowered, and the wafer 1 is brought into contact with the stage 25 having a built-in heater (wafer temperature 200 ° C., uncured layer). Rate: about 4 μm / min) Remove the uncured layer 3 (Fig. 2
(c)). In the step of removing the non-cured layer 3, in Example 2, heat is directly obtained from the high-temperature stage, so that a higher rate can be obtained than in Example 1 using lamp heat.

[0042]

The first effect is that the surface hardened layer 4 is kept at a low temperature.
High-speed removal using only oxygen gas. Thereby, the surface hardened layer 4 can be removed at a high speed without damaging the underlayer such as the insulating oxide film provided on the semiconductor substrate 1 and without causing popping. The reason is that the ion bombardment is used at a low temperature so that the rate becomes high even with only oxygen gas.

The second effect is that the cured layer 4 and the non-cured layer 3 can be processed in the same ashing chamber.
This increases economy and throughput, and increases throughput by about 50% compared to conventional methods. The reason is,
This is because the speed is controlled by the bias and the temperature using one plasma source.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view sequentially showing a resist removing step according to the present invention, and FIG. 1 (A) shows a state in which a resist is applied and ion-implanted to form a surface hardened layer 4; FIG. 1B shows a state in which the surface hardened layer 4 has been removed,
FIG. 1C is a diagram showing a state in which the non-cured layer 3 has been removed.

FIG. 2 is a schematic cross-sectional view sequentially showing a resist removing step in a case where vertically movable pins are used as temperature control means of a semiconductor substrate 1 in a resist removing method according to the present invention; 2 (A) to 2 (C) show FIGS.
The figure corresponding to FIG.1 (C) is shown.

FIG. 3 is a schematic cross-sectional view showing a conventional resist removing step of removing a surface hardened layer with a mixed gas of oxygen and fluorine based on the order of steps, and FIGS. 3 (A) to 3 ( C)
1 shows diagrams corresponding to FIGS. 1A to 1C, respectively.

FIG. 4 is a schematic cross-sectional view showing a conventional resist removing step of removing a surface hardened layer by RIE using H ₂ plasma in the order of steps, and FIGS. 4 (A) to 4 (C). )
FIGS. 1A to 1C show diagrams respectively corresponding to FIGS.

FIG. 5 is a diagram showing a fluorine radical (F) after normal ashing.
FIG. 5 is a schematic cross-sectional view showing a conventional resist removing step of removing a popping residue by *) in the order of steps, and FIG.
(A) to FIG. 5 (C) show diagrams corresponding to FIG. 1 (A) to FIG. 1 (C), respectively.

FIG. 6 is a flowchart showing a resist removing step according to the present invention.

FIG. 7 is a side view showing a configuration of a specific example of a resist removing apparatus used in the present invention.

FIG. 8 is a side view showing the configuration of a specific example of a resist removing apparatus used in the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, silicon wafer 2 ... Photoresist 3 ... Uncured layer 4 ... Surface hardened layer 5 ... As + 6 ... Oxygen ion 10 ... Oxygen radical 12 ... Oxygen radical, fluorine radical 13 ... Oxygen radical, nitrogen radical 14 ... Nitrogen ion Hydrogen ion 15 resist residue 20 resist removing device 21 sealed processing space 22 coil 23 high-frequency current source 24 ion 25 heater-supported semiconductor substrate support and electrode 26 bias means 27 lamp and heating element 28 ... Semiconductor substrate support 30 ... Temperature controller 31 ... DC power supply 32 ... Vertical movable pin

Claims (16)

[Claims] In a manufacturing process of a semiconductor device, when a hardened layer portion of a resist whose surface layer is hardened by ion implantation is removed by an ashing method, the surface hardening of the resist is performed through a low-temperature ion bombardment process. A method for removing a resist, comprising removing a layer. 2. The low-temperature ion bombardment treatment step includes: maintaining a temperature of a substrate forming the semiconductor device at a low temperature;
2. The resist removing method according to claim 1, further comprising an ion generating step and a step of applying a bias to the ions generated in the ion generating step. 3. The method according to claim 2, wherein the step of maintaining the temperature of the substrate at a low temperature controls the temperature of the substrate to be set at 120 ° C. or lower. 4. The ion generating gas used in the ion generating step is a gas selected from oxygen gas, a mixed gas of oxygen and nitrogen, argon, and helium. The method for removing a resist according to claim 2. 5. In a manufacturing process of a semiconductor device, when a hardened layer portion of a resist whose surface layer is hardened by ion implantation is removed by an ashing method, a surface hardening of the resist is performed through a low-temperature ion bombardment process. A first step of removing a layer and a second step of removing an uncured layer of the resist after the surface cured layer has been removed through a downflow plasma treatment step. Resist removal method. 6. The method according to claim 5, wherein the second step is a high-temperature down-flow plasma process. 7. The method according to claim 5, wherein the same ion is used in the first and second steps. 8. The ion generating gas used for generating said ions is one gas selected from oxygen gas, a mixed gas of oxygen and nitrogen, argon, and helium. 8. The method for removing a resist according to any one of 5 to 7. 9. The method according to claim 5, wherein the first and second steps are performed in a single processing area. 10. A resist used for removing, by an ashing method, a resist provided on a surface of a semiconductor substrate having a resist layer in which a part of a surface layer is hardened by ion implantation in a manufacturing process of a semiconductor device. A resist removing apparatus, wherein the resist removing apparatus includes: a sealed processing space portion containing a gas body capable of generating ions; ion generating means for ionizing the gas body in the sealed processing space portion; A resist removing apparatus, comprising: a bias unit for applying a bias to the applied ions; a unit for holding the semiconductor substrate; and a temperature control unit for controlling the temperature of the semiconductor substrate. 11. When removing the hardened layer portion of the resist in which the surface layer is hardened by the ashing method, the ion generating means and the biasing means are driven, and the temperature control means is used for controlling the temperature of the semiconductor substrate. 11. The resist removing apparatus according to claim 10, wherein driving is controlled so as to maintain the temperature at a relatively low temperature, and a low-temperature ion bombardment process is performed. 12. When removing the resist after the cured layer portion is removed, the ion generating means is driven, and the temperature control means reduces the temperature of the semiconductor substrate to a relatively low temperature. 11. The apparatus according to claim 10, wherein the driving is controlled so as to maintain the temperature at a relatively high level from the start, and either the down-flow plasma processing or the high-temperature down-flow plasma processing is executed. Resist removal equipment. 13. The biasing means is configured to form an additional electric field in the resist removing device in a direction such that the ions are accelerated toward one main surface of the semiconductor substrate. The resist removing apparatus according to claim 10, wherein the resist removing apparatus is used. 14. The resist removing apparatus according to claim 10, wherein said temperature control means is constituted by a heat source for directly or indirectly heating said semiconductor substrate. 15. The resist removing apparatus according to claim 14, wherein said temperature control means includes means for arbitrarily adjusting a distance between said semiconductor substrate and said heat source. 16. A gas body capable of generating the ions includes oxygen gas, a mixed gas of oxygen and nitrogen, argon,
16. The resist removing apparatus according to claim 10, wherein the gas is one gas selected from the group consisting of helium and helium.