JPH10135157A - Multilayer wiring substrate and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent separation between a base substrate and interlayer insulating film in a dicing or breaking step by directly applying a photosensitive resin to the interlayer insulating film, patterning it and forming scribe lines at dicing or breaking positions with the base substrate exposed. SOLUTION: A first interlayer insulating film, first layer base conductive film 2a and first layer wiring pattern are formed to complete a first layer wiring into a base substrate 10 first trenches 8a are formed. Interlayer connection holes 7 and second trenches 8b are formed, second layer base conductive film 2b and second layer wiring pattern are formed, electroplated film is deposited on this conductive film 2b, conductors 5b are formed, the base conductive film 2b not having the conductors 5b is removed and the divide into mufti- chip modules, and the substrate 10 is cut, using a dicing blade along scribe lines defined by the first and second trenches 8a, 8b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board for producing a high-density high-speed multi-chip module and a method for producing the same.

[0002]

2. Description of the Related Art In circuit boards on which electronic components such as LSIs are mounted, in order to satisfy the demand for higher density and higher speed,
An interlayer insulating film made of an organic polymer material having a low dielectric constant is formed on a base substrate, and circuit wirings are respectively formed on the laminated interlayer insulating film. A multi-chip module connected by forming via holes is used. Generally, the multi-chip module is formed as a multi-layer wiring board in which a plurality of multi-chip modules are formed on a large base substrate for cost reduction and the like, and then the multi-layer wiring board is formed for each multi-chip module. It is divided and manufactured.

[0003]

The multi-chip module is usually divided by dicing the multi-layer wiring board into small multi-chip modules (small boards) using a dicing cutter. As shown in FIG. 6, it is necessary to directly cut the interlayer insulating film laminated on the base substrate, and peeling occurs between the base substrate and the interlayer insulating film or between the interlayer insulating films during the dicing process (see FIG. 6). 6 (b)), deterioration of insulation properties and the like are caused, and this is a cause of deterioration of reliability of the multi-chip module. Also,
In the multilayer wiring board of the conventional structure, when using a method in which a multilayer wiring is formed on a base substrate provided with a laser scribe in advance on the front surface or the back surface, and instead of the scribe cut, the laser scribe is used to break each multi-chip module, A break of the interlayer insulating film on the base substrate is required, and peeling of the interlayer insulating film at the time of the break has been a problem. SUMMARY OF THE INVENTION It is an object of the present invention to provide a multilayer wiring board structure in which a peeling does not occur between a base substrate and an interlayer insulating film or between interlayer insulating films in a dicing step or a breaking step.

[0004]

Accordingly, as a result of intensive studies, the inventor has used a photosensitive resin for an interlayer insulating film of a multilayer wiring board and directly exposed and patterned the same, thereby forming a dicing position of the multilayer wiring board. The present inventors have found that the above-mentioned separation can be prevented by forming a scribe line in which the surface of the base substrate is exposed at the break position, and completed the present invention.

That is, according to the present invention, an interlayer insulating film laminated on a base substrate to form a plurality of multi-chip modules, wirings respectively formed on the interlayer insulating film, and wiring between the wirings are provided. In the multilayer wiring board having via holes formed in the interlayer insulating film for connection, the laminated interlayer insulating film is made of a photosensitive resin, and the photosensitive resin is exposed and patterned, A multi-layer wiring board characterized by forming scribe lines with a base substrate surface exposed together with via holes around a multi-chip module. In the process of dividing the multi-layer wiring board into each multi-chip module, the base substrate is diced and cut along the scribe line, so that it is not necessary to directly cut the interlayer insulating film, and the peeling of the interlayer insulating film can be prevented. Becomes In addition, since the scribe line is formed by directly exposing and patterning an interlayer insulating film made of a photosensitive resin, it can be formed together with the via hole, and
Compared with the method of patterning the interlayer insulating film using a photoresist or the like, the controllability of the scribe line forming position, the scribe line width, and the like can be improved.

Further, the present invention provides an interlayer insulating film formed on a base substrate to form a plurality of multi-chip modules, wirings formed on the interlayer insulating film, and wiring between the wirings. Multilayer wiring having via holes formed in the interlayer insulating film for connection and openings provided in the interlayer insulating film for exposing the base substrate surface around the multi-chip module to form scribe lines In the substrate, the interlayer insulating film forming the side surface of the opening is formed sequentially so that the upper interlayer insulating film covers the side surface of the lower interlayer insulating film. The lower interlayer insulating film side surface of the opening side wall portion is covered with an upper interlayer insulating film,
In the dicing step, moisture or the like does not permeate between the interlayer insulating films, and thus the separation of the interlayer insulating films can be prevented.

Further, the present invention is characterized in that a notch line is provided on a front surface or a back surface of the base substrate on which the scribe line is formed so that a center line of the notch line is arranged in the scribe line. It is also a multi-layer wiring board. By adopting such a multilayer wiring board structure, it is not necessary to break the interlayer insulating film on the base substrate when breaking the multi-chip module on the multilayer wiring board, and the peeling of the interlayer insulating film in the breaking step is prevented. be able to.

Further, the present invention provides a process for forming a first interlayer insulating film made of a photosensitive resin on a base substrate, and exposing and patterning the first interlayer insulating film. Forming a first opening with a base substrate surface exposed around the multi-chip module forming portion of the interlayer insulating film; forming a first wiring on the first interlayer insulating film; Forming a second interlayer insulating film made of a photosensitive resin on the first wiring, and forming a via hole in the second interlayer insulating film by exposing and patterning the second interlayer insulating film; Removing the second interlayer insulating film over the first opening to form a second opening, and forming a scribe line with the base substrate surface exposed at the same time. Of multi-layer wiring boards There is also a way. As described above, in the present invention, the photosensitive resin is used for the interlayer insulating film, and the photosensitive resin is directly exposed and patterned to form scribe lines. Therefore, the scribe line is formed by etching the interlayer insulating film using a photoresist as a mask. The controllability of the patterning is improved as compared with the method of forming the first opening, and the alignment between the first opening and the second opening can be performed easily and with high accuracy. As the patterning conditions for the photosensitive resin, it is preferable to use conditions as shown in Table 1 below.

[Table 1]

Further, the present invention provides a step of forming a first interlayer insulating film on a base substrate and patterning the first interlayer insulating film to form a multi-chip module of the first interlayer insulating film. Forming a first opening having a base substrate surface exposed around the portion, forming a first wiring on the first interlayer insulating film, and forming the first wiring on the first interlayer insulating film;
Forming a second interlayer insulating film on the wiring and patterning the second interlayer insulating film to form a via hole in the second interlayer insulating film and simultaneously form the first opening The scribe line exposing the base substrate surface by removing the upper second interlayer insulating film and forming a second opening having a smaller opening width than the first opening in the first opening. And a step of forming a multilayer wiring board.

Further, the present invention is characterized in that a notch line is provided on the back surface of the scribe line forming portion of the base substrate in advance so that the center line of the notch line is arranged in the scribe line. Item 6. The method for manufacturing a multilayer wiring board according to item 4 or 5.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 to 3 are cross-sectional views showing a manufacturing process of a multichip module according to one embodiment of the present invention. First, as shown in step (a) of FIG. 1, on a base substrate 10 made of high-purity alumina (purity 99.5%),
A photosensitive organic polymer material 1a (a photosensitive polyimide “Photo Nice” manufactured by Toray Industries, Inc.) is applied and prebaked. Next, as shown in step (b), patterning is performed using a negative photomask, and the photosensitive organic polymer material 1a on the boundary (cut line) of the adjacent multichip module is removed by development. Then, a first groove 8a having a width of 400 μm is formed. Subsequently, the photosensitive organic polymer material 1a
To form a first interlayer insulating film having a thickness of 20 μm. Next, as shown in step (c), the organic polymer material 1
a surface was treated with hydrazine and the catalyst was activated with palladium.
An electroless copper plating film of 05 μm is formed, and a first-layer underlying conductor film 2a is formed. Next, as shown in step (d), a positive photoresist 3 (Positive photoresist AZP4620, manufactured by Hoechst) is applied and prebaked.
Next, as shown in step (e), the positive photoresist 3 is exposed using a photomask 4a to expose a first-layer wiring pattern, and then developed and washed with water. A first-layer wiring pattern as shown in f) is formed. Next, as shown in step (g), an electroplating film is deposited on the first-layer underlying conductor film 2a by using a semi-additive method to form a conductor 5a. Such electrolytic plating uses electrolytic copper plating with a copper sulfate plating solution, and deposits electrolytic copper plating on the exposed electroless copper plating film to a thickness of about 5 μm.
(The thickness of the photoresist 3 used for the mask is 7 μm). Next, as shown in step (h), after the photoresist 3 is removed, the underlying conductor film 2a in the portion without the conductor 5a is removed, and the first layer wiring is completed as shown in step (i). .

Subsequently, as shown in step (j) of FIG.
A negative photosensitive organic polymer material (photosensitive polyimide "Photo Nice", manufactured by Toray Industries, Inc.) 1b is applied to the entire surface and prebaked. Next, as shown in the step (k), the pattern of the via hole and the second groove 8b is exposed using the photomask 6 for negative type, and is developed and washed to perform the processing as shown in the step (l). Then, a via hole (interlayer connection hole) 7 and a second groove 8b are formed. The second groove 8
b is the first groove 8 having a width of 400 μm formed in the step (b).
a, the groove width is 200 μm, and thereafter, as in the step (b), the photosensitive organic polymer material 1
Cure b. Subsequently, as shown in step (m),
The second-layer underlying conductor film 2b is formed by using the same step as the step (c). Next, as shown in a step (n), a photoresist 3 is applied using the same step as the step (d), and is pre-baked. Next, as shown in step (o), the second layer wiring pattern is exposed using the photomask 4b.

Further, as shown in a step (p) of FIG. 3, only the via hole 7 is exposed using the positive type photomask 4c for multiple exposure, and the photoresist 3 in the via hole 7 is exposed. I do. Next, as shown in step (q), development and washing are performed to form a second layer pattern. Next, as shown in the step (r), an electrolytic plating film is deposited on the second-layer underlying conductor film 2b by the same step as the step (g) to form the conductor 5b, and then the step (s) Then, the photoresist 3 is removed as shown in FIG. Subsequently, as shown in step (t), the underlying conductive film 2b in the portion without the conductor 5b is removed, and a multi-chip module is completed.
Finally, to divide each multi-chip module,
The base substrate 10 is cut using a dicing blade having a width of 150 μm along the scribe line formed by the first and second grooves 8a and 8b, thereby completing a multi-chip module.

FIG. 4A is a cross-sectional view of the multilayer wiring board according to the first embodiment of the present invention, and FIG. 4B is a cross-sectional view of the multi-chip module when it is scribe-cut. In the step (l), the second groove 8b is formed so that the center line of the groove coincides with the first groove 8a.
The width of the groove 8a is 400 μm, and the width of the second groove 8b is 200 μm.
4A, the side surface of the first-layer organic insulating film (organic polymer material) is formed on the side wall of the groove forming the scribe line, as shown in FIG. Material).

As described above, according to the present embodiment, by cutting and dividing the base substrate along the scribe line, it is necessary to directly cut the organic insulating film (organic polymer material) formed by lamination during dicing. As a result, the organic insulating film does not peel off during dicing as shown in the conventional example (FIG. 6), and it is possible to prevent the deterioration of the insulating property and the like due to this. In particular, the present embodiment has a structure in which the side surface of the first-layer organic insulating film (organic polymer material) is covered with the second-layer organic insulating film (organic polymer material) on the groove side wall forming the scribe line. Therefore, intrusion of cooling water and the like used in the dicing step between the first and second organic insulating films can be prevented, and the reliability of the chip can be improved as compared with the conventional structure (FIG. 6). In the present embodiment, a photosensitive resin is used for the interlayer insulating film, and the photosensitive resin is directly exposed and patterned to form scribe lines. Therefore, the scribe line is formed by etching the interlayer insulating film using a photoresist as a mask. The controllability of patterning is improved as compared with the method of forming the first groove 8a.
The second groove 8b can be easily formed therein with high precision. Furthermore, since the via hole forming step (step (l)) can be used for forming the groove 8b, the groove 8b can be formed without increasing the number of manufacturing steps.

In the above embodiment, a two-layer wiring board has been described. However, it is also possible to further increase the number of layers by repeating the same steps. Further, in the above embodiment, the photosensitive organic polymer material is used as the interlayer insulating film. However, an organic polymer material having no photosensitive group, a polyimide for printing, or the like can be used instead. FIG.
In the step (g) and the step (l) in FIG. 3, the semi-additive method was used to form the wiring, but instead of forming the underlying conductor film, the surface of the organic polymer material was subjected to a catalyst activation treatment for electroless plating. It is also possible to perform (seeding) and use a full additive method of forming a conductor by growing an electroless plating film to a desired thickness instead of the electrolytic plating film.

Embodiment 2 FIG. FIG. 5A is a sectional view of a multilayer wiring board according to another embodiment of the present invention.
FIG. 2B is a cross-sectional view when a break occurs between the multi-chip modules. In the manufacture of the multilayer wiring board according to the present embodiment, a break line is previously formed on the back surface of the cut portion of the base substrate by some method. For example, it is a laser scribe formed by laser processing, and the laser scribe will be described below as an example. After forming the laser scribe (see FIG. 5A) by laser processing, the same steps as those in the first embodiment (FIGS. 1A to 3T)
Is performed to form a multilayer wiring board so that a scribe line is formed on the laser scribe. In this case, the interval between the organic insulating films (organic polymer materials) adjacent to each other on the scribe line is 6 between the first organic insulating films.
It is appropriate that the distance between the first-layer organic insulating films is set to 400 μm. After forming the multilayer wiring board, instead of dicing and cutting the scribe line, by breaking the multilayer wiring board along the scribe line,
It becomes possible to divide the multi-chip module without peeling off the interlayer insulating film. In particular, in the present embodiment, the dicing cut step can be omitted, so that the manufacturing process can be simplified. Note that the laser scribe can be formed on the surface of the cut portion of the base substrate.

[0018]

As is apparent from the above description, according to the present invention, a scribe line exposing the surface of the base substrate is formed in advance in the portion where the dicing cut is to be made on the multilayer wiring board, so that the lamination is performed. Since it is not necessary to scribe the organic insulating film directly, it is possible to prevent the deterioration of the insulating property due to the peeling of the organic insulating film in the scribe cutting step, and to improve the reliability of the multi-chip module. In particular, by adopting a structure in which the side surface of the lower organic insulating film is covered with the upper organic insulating film on the scribe line side wall, penetration of moisture and the like between the layers of the organic insulating film during dicing cut is prevented, and peeling of the insulating film is prevented. It is also possible to prevent it.

Further, according to the present invention, a scribe line is formed by directly exposing and patterning a photosensitive resin for an interlayer insulating film to form a scribe line. As compared with a method of forming a scribe line by etching an interlayer insulating film using a mask as a mask, the controllability of patterning is improved, alignment of the first opening and the second opening can be easily performed, and It can be performed with high accuracy.

Further, according to the present invention, by using a base substrate having a laser scribe formed on a front surface or a back surface, a multi-layer wiring substrate is manufactured such that scribe lines are arranged on the upper surface of a laser scribe portion. The break between the multi-chip modules can be performed without removing the insulating film, the dicing step can be omitted, and the manufacturing process can be simplified.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a multilayer wiring board according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the multilayer wiring board according to the first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the multilayer wiring board according to the first embodiment of the present invention.

FIG. 4A is a cross-sectional view of the multilayer wiring board according to the first embodiment of the present invention, and FIG. 4B is a cross-sectional view of the multi-chip module when it is scribe-cut.

FIG. 5A is a cross-sectional view of a multilayer wiring board according to a second embodiment of the present invention, and FIG. 5B is a cross-sectional view when a break between multi-chip modules is performed.

6A is a cross-sectional view of a multilayer wiring board manufactured by a conventional method, and FIG. 6B is a cross-sectional view of a multi-chip module when scribe-cut is performed.

[Explanation of symbols]

Reference Signs List 1a, 1b organic polymer material, 2a, 2b base conductor film, 3 photoresist, 4a, 4b, 4c photomask, 5a, 5b conductor, 6 photomask, 7 via hole, 8a, 8b groove, 9 dicing location, 10
Base substrate.

Claims (6)

[Claims] An interlayer insulating film laminated on a base substrate to form a plurality of multi-chip modules, wirings respectively formed on the interlayer insulating film, and connection between the wirings. In a multilayer wiring board having via holes formed in an interlayer insulating film, the laminated interlayer insulating film is made of a photosensitive resin,
By exposing and patterning the photosensitive resin,
A multi-layer wiring board, wherein a scribe line whose base substrate surface is exposed and a via hole are collectively formed around the multi-chip module. 2. An interlayer insulating film laminated on a base substrate to form a plurality of multi-chip modules, wirings respectively formed on the interlayer insulating film, and connection between the wirings. In a multilayer wiring board having a via hole formed in an interlayer insulating film and an opening provided in the interlayer insulating film to form a scribe line by exposing a surface of a base substrate around the multi-chip module, A multilayer wiring board, wherein an interlayer insulating film forming a side surface of an opening is sequentially formed such that an upper interlayer insulating film covers a side surface of a lower interlayer insulating film. 3. A notch line is provided on a front surface or a back surface of the base substrate on which the scribe line is formed, such that a center line of the notch line is disposed in the scribe line. Or the multilayer wiring board according to 2. 4. A first substrate made of a photosensitive resin on a base substrate.
Forming the first interlayer insulating film; and exposing and patterning the first interlayer insulating film to expose the base substrate surface around the multi-chip module forming portion of the first interlayer insulating film. Forming an opening, forming a first wiring on the first interlayer insulating film, and forming a second interlayer insulating film made of a photosensitive resin on the first wiring. Forming a via hole in the second interlayer insulating film by exposing and patterning the second interlayer insulating film, and simultaneously removing the second interlayer insulating film on the first opening. Forming a second opening by forming a scribe line with the surface of the base substrate exposed. 5. A step of forming a first interlayer insulating film on a base substrate, and patterning the first interlayer insulating film,
Forming a first opening with a base substrate surface exposed around the multi-chip module forming portion of the first interlayer insulating film; and forming a first wiring on the first interlayer insulating film. Forming a second interlayer insulating film on the first wiring; and patterning the second interlayer insulating film,
Forming a via hole in the second interlayer insulating film and simultaneously removing the second interlayer insulating film on the first opening;
Forming a scribe line in which the base substrate surface is exposed by forming a second opening having a smaller opening width than the first opening in the first opening. A method for manufacturing a multilayer wiring board. 6. A notch line is provided on a front surface or a back surface of a scribe line forming portion of the base substrate so that a center line of the notch line is arranged in the scribe line in advance. Or the method for manufacturing a multilayer wiring board according to 5.