JPH10134575A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of suppressing the increase of a chip area owing to the increase of the number of memory blocks. SOLUTION: An internal control signal generating circuit 10 generates a 1st control signal A and a 2nd control signal B in accordance with input signals received from a /RAS pin, a /CAS1 pin and a /CAS2 pin. At the time of a reading operation, the read-out datum of a memory block #1 or #2 is outputted from an outer terminal DQ1 and the read-out datum of a memory block #3 or #4 is outputted from an outer terminal DQ2 in accordance with the 1st control signal A and the 2nd control signal B. On the other hand, at the time of a writing operation, the input datum from the outer terminal DQ1 is the written datum of the memory block #1 or #2 and the input datum from the outer terminal DQ2 is the written datum of the memory block #3 or #4 in accordance with the 1st control signal A and the 2nd control signal B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a plurality of memory blocks in which a specific memory cell is simultaneously selected by a common address signal and which can perform a write operation or a read operation. It concerns the device.

[0002]

2. Description of the Related Art In a semiconductor memory device, in particular, a dynamic random access memory (hereinafter referred to as DRAM), the power consumption increases and the access to a specific memory cell becomes slow with the increase in capacity. Has occurred.

As a means for solving this problem, a DRAM having a memory cell array composed of a plurality of independent memory blocks has been developed and already manufactured.

FIG. 17 is a schematic block diagram showing a configuration of a conventional DRAM 500 comprising a plurality of memory blocks.

Referring to FIG. 17, a DRAM 500 has a memory cell array 50 and a memory cell array 50.
Includes four memory blocks # 1 to # 4.

FIG. 18 is a circuit diagram schematically showing a configuration of a memory block in a conventional DRAM 500.

Memory block # 1 includes a plurality of memory cells MC arranged in a matrix consisting of a plurality of rows and a plurality of columns. Memory cells MC are connected by word lines in the row direction and bit line pairs BL, / BL in the column direction.
Connected by Each bit line pair BL, / BL is
Each is connected to a corresponding sense amplifier 56. The bit line pair BL, / BL is connected to a data bus DB1 via an I / O gate 57. I / O gate 5
7 is controlled by the column selection line CSL.

Memory blocks # 2 to # 4 have the same structure as memory block # 1 in FIG. 21, memory block # 2 is connected via data bus DB2, and memory block # 3 is connected via data bus DB3. Memory block♯
4 exchanges data with the outside via a data bus DB4.

Referring to FIG. 17, DRAM 500 further includes an internal control signal generating circuit 51. The internal control signal generation circuit 51 converts the * RAS signal (row address strobe signal) input from the / RAS pin into a / RAS signal (internal row address strobe signal), and converts the * CAS signal (column address) input from the / CAS pin. The strobe signal is converted to a / CAS signal (internal column address strobe signal), the * WE signal (write enable signal) input from the / WE pin is converted to a / WE signal (internal write enable signal), and * O entered
The E signal (output enable signal) is converted into a / OE signal (internal output enable signal). Further, from these internal control signals, a DRAM described later is used.
Internal control signal / X for controlling an internal circuit included in H.500
E is generated.

The DRAM 500 further includes an address buffer 52, a row decoder 53, and a column decoder 54.

The address buffer 52 receives the / RAS signal.
Address terminal a₀, ..., a _NAds entered from
Signal (A₀, ..., A_N) And internal line ad
Signal (X₀, ..., X_N).

A row decoder 53 decodes an internal row address signal (X ₀ ,..., X _N ) to generate a memory block #
The corresponding word line WL in each of the memory blocks 1 to # 4 is selected. When the potential of the selected word line WL rises, the sense amplifier 56 corresponding to the memory cell MC connected to each word line WL operates to amplify the minute potential difference generated on the bit lines BL and / BL. Is done.

Further, the address buffer 52 has a / CAS
Based on the signal, address terminals a _0, ..., the address signal input from _{a N (A 0, ...,} A N) is captures and internal column address signals _{(Y 0, ..., Y N} ) for generating a.

The column decoder 54 decodes the internal column address signals (Y ₀ ,..., Y _N ) and outputs
The corresponding column selection line CSL in each of the memory blocks 1 to # 4 is selected. When the potential of the selected column select line CSL rises, the bit line pair BL, / BL
Are connected to the data buses DB1 to DB via the I / O gate 57.
4 is connected.

As a result, during a write operation, data input from an external terminal is transmitted to data buses DB1 to DB4 via an input / output circuit described later, and then the corresponding bit line B
L and / BL and written to a specific memory cell MC.

In a read operation, bit lines BL, /
The potential of BL is transmitted to data buses DB1 to DB4, and then to an input / output circuit described later, and as a result, is output to an external terminal.

The DRAM 500 further includes a main amplifier 6
0 to 63, data output buffer circuits 70 to 73, and data input buffer circuits 80 to 83.

The main amplifier 60 has a memory block # 1
The signal on the data bus DB1 is amplified and output. Main amplifier 61 is connected to data bus DB of memory block # 2.
2 is amplified and output. The main amplifier 62
The signal on data bus DB3 of memory block # 3 is amplified and output. The main amplifier 63 is a memory block
4 on the data bus DB4.

The data output buffer circuit 70 generates external read data from the input output signal of the main amplifier 60 based on the / OE signal (output enable signal) and outputs it to the external terminal DQ1. Data output buffer circuit 71 generates external read data from the input output signal of main amplifier 61 based on the / OE signal, and outputs it to external terminal DQ2. Data output buffer circuit 72
Generates external read data from the input output signal of the main amplifier 62 based on the / OE signal, and outputs the external terminal DQ
Output to 3. The data output buffer circuit 73 has a / OE
Based on the signal, external read data is generated from the input output signal of the main amplifier 63 and output to the external terminal DQ4.

The data input buffer circuit 80 has an external terminal DQ1 based on a / WE signal (write enable signal).
, Generates internal write data to be written to a specific memory cell MC of memory block # 1, and transmits the data to data bus DB1. The data input buffer circuit 81 is connected to an external terminal DQ2 based on the / WE signal.
, Generates internal write data to be written into a specific memory cell MC of memory block # 2, and transmits the generated data to data bus DB2. The data input buffer circuit 82 controls the external terminal DQ3 based on the / WE signal.
, Generates internal write data to be written into a specific memory cell MC of memory block # 3, and transmits the data to data bus DB3. The data input buffer circuit 83 is connected to an external terminal DQ4 based on the / WE signal.
, Generates internal write data to be written into a specific memory cell MC of memory block # 4, and transmits the data to data bus DB4.

The timing of the read operation and write operation in DRAM 500 will be described below. FIG.
Is a conventional DRAM 50 having four memory blocks.
FIG. 11 is a timing chart of a read operation and a write operation at 0. In FIG. 19, RA indicates an internal row address signal, and CA indicates an internal column address signal.

At time t0, when the / RAS signal falls to the L level, address buffer 52 takes in address signals (A ₀ ,..., A _N ) from the outside, and outputs internal row address signals (X ₀ ,. X _N ). The corresponding word line WL in each of memory blocks # 1 to # 4 is received by row decoder 53 receiving the signal.
Is activated.

At time t1, when the / CAS signal falls to the L level, address buffer 52 takes in address signals (A ₀ ,..., A _N ) from the outside, and outputs internal column address signals (Y ₀ ,. Y _N ). Column decoder 54 receiving this activates the corresponding column select line CSL in each of memory blocks # 1 to # 4, and connects data buses DB1 to DB4 to bit line pair BL and / BL. You.

Similarly, at time t0, the / OE signal becomes L
When the level falls, the read operation starts.

As a result, after the signals on the data buses DB1 to DB4 are amplified by the main amplifiers 60 to 63, they are converted into external read data O1, O2, O3 and O4 by the data output buffer circuits 70 to 73. , External terminal D
Output from Q1 to DQ4.

At time t2, when the / OE signal rises to the H level, the read operation ends. At time t2, when the / RAS signal and / CAS signal rise to H level, memory blocks # 1 to # 4 enter a non-operating state.

During the period from time t3 to t4, time t
As in the period from 0 to t1, the / RAS signal and / CAS
When the signal falls to L level, a specific word line WL in each of memory blocks # 1 to # 4 is activated and data bus DB1 is activated.
To DB4 and a specific bit line pair BL, / BL in each of memory blocks # 1 to # 4.

At time t4, when the / WE signal falls to L level, the writing operation is started.

As a result, the external write data W1, W2, inputted from the respective terminals of the external terminals DQ1 to DQ4,
After W3 and W4 are converted into internal write data by data input buffer circuits 80 to 83, data buses DB1 to DB
B4 to be written to specific memory cells MC of memory blocks # 1 to # 4.

[0030]

SUMMARY OF THE INVENTION As indicated above,
A conventional semiconductor memory device has a configuration in which a memory cell array is divided into a plurality of blocks and operated as a solution to the above-mentioned problem accompanying an increase in storage capacity.

However, in the above configuration, input / output pins are prepared by the number of divided memory blocks, and internal circuits (for example, a main amplifier and a data input buffer) related to input / output corresponding to each input / output pin are provided. Circuit, data input buffer circuit) must be installed inside the chip. As a result, a circuit design corresponding to the number of memory blocks is required, and there is a problem that the chip area increases as the number of memory blocks increases.

Further, as a future technology trend, the capacity of the memory cell array is further increased, and the number of memory blocks included in one chip tends to increase. Therefore, an increase in chip area is an unavoidable problem.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problem, and it is an object of the present invention to operate a plurality of memory blocks without increasing a chip area due to an increase in the number of memory blocks. It is to provide a semiconductor memory device that can be used.

[0034]

According to a first aspect of the present invention, there is provided a semiconductor memory device including a plurality of memory blocks in which specific memory cells are simultaneously selected by a common address signal. Signal generation means for receiving a first input signal from an external terminal, a second input signal from a second external terminal, and a third input signal from a third external terminal to generate a control signal A plurality of memory blocks divided into a group for each two memory blocks, and selectively outputting read data from one of the memory blocks belonging to each group to the outside in accordance with a control signal; Output control means for each group, and write data of one of the memory blocks belonging to each group selectively according to a control signal. A plurality of group-based input control means, and one data input / output terminal common to the group of output of data to the outside of the output control means and input of data from the outside of the input control means. Do.

A semiconductor memory device according to a second aspect is the semiconductor memory device according to the first aspect, wherein the control signals are a first control signal and a second control signal, and each of the output control means is , The first group belonging to the group according to the first control signal.
Means for outputting read data from a memory block of the group from a data input / output external terminal, and means for outputting data read from a second memory block belonging to a group from a data input / output external terminal in response to a second control signal Wherein each of the input control means transmits data input from the data input / output external terminal to the first memory block in accordance with a first control signal; and data input from the data input / output external terminal. To the second memory block in response to a second control signal.

According to a third aspect of the present invention, there is provided the semiconductor memory device according to the first aspect, wherein the first input signal is /
RAS signal, the second input signal is the first / CAS signal, and the third input signal is the second / CAS signal.

A semiconductor memory device according to a fourth aspect is a semiconductor memory device comprising a plurality of memory blocks in which a specific memory cell is selected at the same time by a common address signal, wherein a first external terminal receives a first external terminal. Signal generating means for generating a control signal in response to an input signal from the second external terminal and a second input signal from a second external terminal, and dividing the plurality of memory blocks into groups for each of the two memory blocks Then, based on the control signal, one of the memory blocks belonging to each of the groups selectively according to the third input signal from the third external terminal and the fourth input signal from the fourth external terminal. A plurality of group-based output control means for outputting readout data from the external device to the outside, and selectively inputting externally input data to each group according to a control signal and a fourth input signal A plurality of group-based input control means for writing data of any of the memory blocks to which the data control unit belongs, wherein data output to the outside of the output control means and data input to the outside of the input control means are grouped; This is performed by one data input / output terminal common to the units.

According to a fifth aspect of the present invention, there is provided the semiconductor memory device according to the fourth aspect, wherein each of the output control means responds to the control signal and the third input signal so that each of the first and second input signals belongs to the first group. Means for outputting read data from a memory block from a data input / output external terminal; output of read data from a second memory block belonging to a group from a data input / output external terminal in response to a control signal and a fourth input signal Each of the input control means, when the fourth input signal is at the first logic level, in response to the control signal, stores the data input from the data input / output external terminal into the first memory block. Transmitting the data input from the data input / output external terminal to the second memory block if the fourth input signal is a second logical level different from the first logical level in accordance with the transmitting means and the control signal; And means for transmitting the click.

According to a sixth aspect of the present invention, there is provided the semiconductor memory device according to the fourth aspect, wherein the first input signal is /
The RAS signal, the second input signal is a / CAS signal, the third input signal is a first / OE signal, and the fourth input signal is a second / OE signal.

[0040]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a schematic block diagram showing an entire configuration of a semiconductor memory device 100 according to a first embodiment of the present invention. Components in common with the conventional example shown in FIG. Numbers and reference numerals are assigned, and description thereof is omitted.

The difference between the semiconductor memory device 100 according to the first embodiment of the present invention and the conventional example shown in FIG. 17 is as follows.

That is, while there is one terminal for inputting the * CAS signal, the * CAS1 signal and the * CA
It has two terminals for inputting the S2 signal. Instead of the internal control signal generation circuit 51, the * RAS signal and the * C
An internal control signal generating circuit 10 receiving the AS1 signal, the * CAS2 signal, the * WE signal, and the * OE signal at its input is provided in common to the memory blocks # 1 and # 2 instead of the data output buffer circuits 70 to 73. Data output buffer circuit 20 and data output buffer circuit 21 common to memory blocks # 3 and # 4, and data input buffer circuit common to memory blocks # 1 and # 2 instead of data input buffer circuits 80-83 Circuit 3
0 and a data input buffer circuit 31 common to the memory blocks # 3 and # 4.
63, a main amplifier 64 for amplifying the signal on the data bus DB1 and the signal on the data bus DB2, and a main amplifier 65 for amplifying the signal on the data bus DB3 and the signal on the data bus DB4. It is in.

The * CAS1 signal input from the / CAS1 pin and the * CAS2 signal input from the / CAS2 pin become the / CAS1 signal and the / CAS2 signal in the internal control signal generation circuit 10. Both the / CAS1 signal and the / CAS2 signal have the same function as the conventional / CAS signal. Therefore, when the / CAS1 signal or the / CAS2 signal falls to the L level while the / RAS signal is at the L level, the address buffer 52 stores the / C signal.
An internal column address signal is generated for an address signal received from the outside when the AS1 signal or the / CAS2 signal falls to the L level.

That is, at the time when the / CAS1 signal falls to the L level, one memory cell MC belonging to each of memory blocks # 1 to # 4 is selected and the / CAS2 signal goes to the L level. Even at the time of falling, one memory block MC belonging to each of memory blocks # 1 to # 4 is selected.

FIG. 2 is a timing chart showing a relationship between a read operation and a write operation of semiconductor memory device 100 according to the first embodiment of the present invention. In FIG. 2, RA
Indicates an internal row address signal, CA1, CA2, CA
3, CA4 indicates an internal column address signal.

Semiconductor memory device 100 divides memory blocks # 1 to # 4 into a group including memory blocks # 1 and # 2 and a group including memory blocks # 3 and # 4. An output circuit is provided, and the input and output circuits of each group use a common external terminal to input and output data. The control of the write operation and the read operation for each group is performed by control signals (first control signal A and second control signal B) based on the / RAS signal, / CAS1 signal, and / CAS2 signal described later. . That is, semiconductor memory device 100 performs a write operation or a read operation by selecting one of two memory blocks in each group according to a control signal.

More specifically, the semiconductor memory device 100
Performs the following operation during a read operation (/ OE is at L level). When receiving the / CAS1 signal at the L level, it generates the first control signal A at the H level. As a result, electric signal O1 corresponding to the write signal of memory cell MC located at address Z1 of memory block # 1 is output from external terminal DQ1, and external signal DQ2 is located at address Z1 of memory block # 3. Memory cell M
An electric signal O3 corresponding to the write signal of C is output.

On the other hand, when receiving the / CAS2 signal at the L level, it generates the second control signal B at the H level. As a result, electric signal O2 corresponding to the write signal of memory cell MC located at address Z2 of memory block # 2 is output from external terminal DQ2, and external signal DQ2 is located at address Z2 of memory block # 4. Memory cell MC
And outputs an electric signal O4 corresponding to the write signal of.

Semiconductor memory device 100 performs the following operation during a write operation (/ WE signal at L level). When receiving the / CAS1 signal at the L level, it generates the first control signal A at the H level. As a result, input signal W1 received from external terminal DQ1 is written to memory cell MC located at address Z3 of memory block # 1, and input signal W3 received from external terminal DQ2 is input to memory block # 1.
No. 3 is written to the memory cell MC located at the address Z3.

On the other hand, when receiving the / CAS2 signal at the L level, it generates the second control signal B at the H level. As a result, input signal W2 received from external terminal DQ1 is written to memory cell MC located at address Z4 of memory block # 2, and input signal W4 received from external terminal DQ2 is written to memory cell M located at address Z4 of memory block # 4.
Write to C.

The configuration and operation of semiconductor memory device 100 will be described below. FIG. 3 is a circuit diagram schematically showing a configuration of a main part of internal control signal generation circuit 10 in the first embodiment of the present invention.

Internal control signal generating circuit 10 includes NOR circuits NOR1 and NOR2. The NOR circuit NOR1 is
/ RAS signal generated by internal control signal generation circuit 10 and /
A CAS1 signal and an output signal of the NOR circuit NOR2 are received at an input, and a first control signal A is output from an output node 1. The NOR circuit NOR2 includes an internal control signal generation circuit 10
Receives the / RAS signal, the / CAS2 signal, and the output signal of the NOR circuit NOR1, and outputs the second control signal B from the output node 2.

Next, the operation of the internal control signal generation circuit 10 will be described. FIG. 4 is a timing chart showing the relationship between input and output signals of internal control signal generation circuit 10 according to the first embodiment of the present invention.

During the period from time t0 to t1, / CA of H level
NOR circuit NOR1 receiving the S1 signal at its input outputs an L-level signal to output node 1 regardless of the logic level of the signal at output node 2. On the other hand, H level /
NOR circuit NOR2 receiving CAS2 signal at its input
Outputs an L-level signal to output node 2 regardless of the logic level of the signal at output node 1.

During the period from time t1 to t2, / CA of H level
NOR circuit NOR2 receiving the S2 signal at its input outputs an L level signal to output node 2. On the other hand, NOR circuit NOR1 receiving L-level / RAS signal, L-level / CAS1 signal, and L-level signal at output node 2 at its inputs outputs an H-level signal to output node 1.

During the period from time t2 to time t3, / CA of H level
NOR circuit NOR1 receiving the S1 signal at its input outputs an L-level signal to output node 1. On the other hand, NOR circuit NOR2 which receives L-level / RAS signal, L-level / CAS2 signal, and L-level signal of output node 1 at its inputs outputs an H-level signal to output node 2.

During the period in which all of the / RAS, / CAS1 and / CAS2 signals are at the H level (before time t0 and after time t3 in FIG. 3), the signal at output node 1 and the signal at output node 2 are output. Are both L
Level.

Therefore, the signal of output node 1, that is, first control signal A is applied to the / RAS signal and / CAS1
When both signals are at the L level, the signal goes to the H level. When the / CAS1 signal is at the H level, the signal goes to the L level. On the other hand, the signal at output node 2, that is, second control signal B, goes high when both the / RAS signal and the / CAS2 signal are at the L level, and / CAS2
When the signal is at H level, it becomes L level.

That is, during the memory operation of semiconductor memory device 100, internal control signal generating circuit 1 is controlled by the combination of the logic levels of / CAS1 signal and / CAS2 signal.
0 generates two signals (a first control signal A and a second control signal B).

FIG. 5 is a circuit diagram schematically showing a configuration of data output buffer circuit 20 according to the first embodiment of the present invention.

The data output buffer circuit 20 includes inverter circuits IV1 to IV5 and NAND circuits NA1 and NA2.
And transfer gates T1 and T2.

The inverter circuit IV1 receives the / OE signal at its input and outputs a signal S1 obtained by inverting the / OE signal.

NAND circuit NA 1 receives signal S 1 and first control signal A output from internal control signal generation circuit 10 at its inputs, and outputs the operation result to node 3.

NAND circuit NA2 receives signal S1 and second control signal B output from internal control signal generation circuit 10 at its inputs, and outputs the operation result to node 4.

Inverter circuit IV2 inverts the signal on node 3. Inverter circuit IV3 inverts the signal on node 4.

The transfer gate T1 includes a P-channel MOS transistor (hereinafter, referred to as PMOS) PT1 and an N-channel MOS transistor (hereinafter, referred to as NMOS) NT1.

PMOS PT1 and NMOS NT1
Are connected at a node 5;
Each other conduction terminal is connected to data bus DB1 of memory block # 1. And PMOS PT
1 receives the signal on node 3 at its gate,
NT1 receives at its gate the output signal of inverter circuit IV2 (inverted signal on node 3).

The transfer gate T2 is a PMOS P
T2 and NMOS NT2. One conduction terminal of each of the PMOS PT2 and the NMOS NT2 is
Node 5 is connected to the other conductive terminal, and is connected to data bus DB2 of memory block # 2. The gate of the PMOS PT2 receives the signal on the node 4 and the gate of the NMOS NT2 receives the output signal of the inverter circuit IV3 (the inverted signal on the node 4) at its gate.

Inverter circuit IV4 is connected to node 5, receives the outputs of transfer gates T1 and T2, and inverts and amplifies them. On the other hand, the inverter circuit IV5
Inverts and amplifies the output of the inverter circuit IV4 and outputs the result to the external terminal DQ1.

Data output buffer circuit 21 has the same structure as data output buffer circuit 20 and has a data bus D
A data bus DB3 is used as an input line instead of B1, and a data bus DB4 is used as an input line instead of the data bus DB2,
The external terminal DQ2 is used as an output terminal instead of the external terminal DQ1.

FIG. 6 is a timing chart showing the relationship between input and output signals in data output buffer circuit 20 according to the first embodiment of the present invention.

As already described with reference to FIG. 3, internal control signal generating circuit 10 includes * RAS signal, * CAS1 signal, and * C signal.
In response to the AS2 signal, a first control signal A and a second control signal B shown in FIG. 6 are generated.

At time t0, the / RAS signal falls to the L level, and at the next time t1, when the / CAS1 signal falls to the L level, a specific memory cell in each of memory blocks # 1 to # 4 M
C is selected. At time t1, the / OE signal falls to L level, so that this particular memory cell M
A data read operation is performed from C through data buses DB1 to DB4.

At time t2, when the / CAS1 signal rises to H level, these specific memory cells MC are in a non-selected state. Then, a new / CAS2 signal becomes L
When the level falls, a specific memory cell MC in each of memory blocks # 1 to # 4 is selected, and a data read operation is performed via data buses DB1 to DB4.

During the period when the / OE signal is at L level (time t1 to t3 in FIG. 6), signal S1 output from inverter circuit IV1 in FIG. 5 is at H level.

In the period between times t1 and t2, NAND circuit NA1 receiving H-level signal S1 and H-level first control signal A at its inputs outputs an L-level signal on node 3. Transfer gate T1 is PMO
The gate of SPT1 receives the L-level signal on node 3, and the gate of NMOS NT1 receives the H-level signal obtained by inverting the signal on node 3 by inverter circuit IV2. As a result, the transfer gate T1 becomes conductive.

On the other hand, NAND circuit NA receiving H-level signal S1 and L-level second control signal B at its inputs
2 outputs an H level signal to the node 4. The transfer gate T2 receives the H-level signal on the node 4 at the gate of the PMOS PT2, and receives the L-level signal obtained by inverting the signal on the node 4 by the inverter circuit IV3 at the gate of the NMOS NT2. As a result, the transfer gate T2 is turned off.

Therefore, if first control signal A is at the H level, an electric signal corresponding to the signal on data bus DB1 of memory block # 1 is output from external terminal DQ1 via transfer gate T1.

In the period from time t2 to time t3, NAND circuit NA2 receiving H-level signal S1 and H-level second control signal B at its inputs outputs an L-level signal to node 4. The transfer gate T2 is a PMO
The gate of SPT2 receives the L-level signal on node 4 and the gate of NMOS NT2 receives the H-level signal obtained by inverting the signal on node 4 by inverter circuit IV3. As a result, the transfer gate T2 becomes conductive.

On the other hand, NAND circuit N receiving at its inputs H-level signal S1 and L-level first control signal A
A1 outputs an H-level signal to the node 3. The transfer gate T1 receives the signal of the H level on the node 3 at the gate of the PMOS PT1, and the NMOS NT1.
Receives an L-level signal obtained by inverting the signal on node 3 by inverter circuit IV2. As a result, the transfer gate T1 is turned off.

Therefore, if the second control signal is at the H level, an electric signal corresponding to the signal on data bus DB2 of memory block # 2 is output from external terminal DQ1 via transfer gate T2.

Since the signal S1 output from inverter circuit IV1 is at the L level during the period when the / OE signal is at the H level, that is, during the non-read operation (before time t1 and after time t3 in FIG. 6), Receiving NAND circuit NA1 outputs an H-level signal to node 3, and NAND circuit NA2 outputs an H-level signal to node 4. As a result, transfer gates T1 and T2
Become non-conductive. Therefore, data bus DB1 and data bus DB2 are electrically disconnected from external terminal DQ1.

The data output buffer circuit 21 having the data bus DB3 of the memory block # 3 and the data bus DB4 of the memory block # 4 as input lines and having the external terminal DQ2 as an output terminal is composed of the data output buffer circuit 20 and the basic circuit. The same operation is performed.

That is, the semiconductor memory device 100 has the / O
When the E signal becomes L level and a read operation is performed, / RAS
The first signal based on the / CAS1 signal and the / CAS2 signal
Under the control of the control signal A and the second control signal B,
Data of a specific memory cell MC of memory block # 1 or memory block # 2 is selectively output from external terminal DQ1, and memory block # 3 or memory block # 4 is selectively selected from external terminal DQ2. Of the memory cell MC is output.

FIG. 7 is a circuit diagram schematically showing a configuration of data input buffer circuit 30 according to the first embodiment of the present invention.

The data input buffer circuit 30 includes inverter circuits IV6 to IV10 and NAND circuits NA3 and NA3.
4 and transfer gates T3 and T4.

The inverter circuit IV6 receives the / WE signal output from the clock buffer 11 at its input, and outputs a signal S2 obtained by inverting the / WE signal.

NAND circuit NA 3 receives signal S 2 and first control signal A output from internal control signal generation circuit 10 at its inputs, and outputs the operation result to node 6.

NAND circuit NA 4 receives signal S 2 and second control signal B output from internal control signal generation circuit 10 at its inputs, and outputs the operation result to node 7.

The inverter circuit IV7 has an external terminal DQ1
And inverts and amplifies the signal received from. On the other hand, inverter circuit IV8 further inverts and amplifies this signal and outputs it to node 8.

The transfer gate T3 is a PMOS P
T3 and NMOS NT3. One conduction terminal of each of the PMOS PT3 and the NMOS NT3 is
Connected to data bus DB1 of memory block # 1, and the other conduction terminal of each is connected to node 8. PMOS PT3 receives the signal on node 6 at its gate, and NMOS NT3 receives the output signal of inverter circuit IV9 (inverted signal on node 6) at its gate.

The transfer gate T4 is a PMOS P
T4 and NMOS NT4. One conduction terminal of each of the PMOS PT4 and the NMOS NT4 is
Memory block # 2 is connected to data bus DB2, and the other conductive terminal is connected to node 8. PMOS PT4 receives at its gate the signal on node 7, and NMOS NT4 receives at its gate the output signal of inverter circuit IV10 (inverted signal on node 7).

Data input buffer circuit 31 has the same structure as data input buffer circuit 30 and has an external terminal DQ.
1, the external terminal DQ2 is used as an input terminal, the data bus DB1 is used as an output line instead of the data bus DB1, and the data bus DB4 is used as an output line instead of the data bus DB2.

FIG. 8 is a timing chart showing a relationship between input and output of signals in data input buffer circuit 30 in the first embodiment.

As already shown in FIG. 3, internal control signal generating circuit 10 generates first control signal A and second control signal B shown in FIG.

At time t0, / RAS signal falls to L level, and at subsequent time t1, / CAS1 signal falls to L level, specific memory cells MC of memory blocks # 1 to # 4 are selected. . And at time t1
In this case, when the / WE signal falls to the L level, a data write operation is performed on this specific memory cell MC via data buses DB1 to DB4.

At time t2, when the / CAS1 signal rises to the H level, these specific memory cells MC are deselected. Then, when the / CAS2 signal newly falls to L level, a specific memory cell MC of each of memory blocks # 1 to # 4 is selected, and a data write operation is performed via data buses DB1 to DB4. Is performed.

Note that during the period when the / WE signal is at the L level (time t1 to t3 in FIG. 8), the signal S2 output from the inverter circuit IV6 in FIG. 7 is at the H level.

In the period from time t1 to time t2, NAND circuit NA3 which receives H-level signal S2 and H-level first control signal A at its input outputs an L-level signal to node 6. The transfer gate T3 is a PMOS
The gate of PT3 receives the L-level signal on node 6, and the gate of NMOS NT3 receives the H-level signal obtained by inverting the signal on node 6 by inverter circuit IV9. As a result, the transfer gate T3 becomes conductive. On the other hand, NAND circuit NA4 receiving at its inputs H-level signal S2 and L-level second control signal B
Outputs an H level signal to the node 7. Transfer gate T4 is connected to the gate of PMOS PT4 at node 7
The upper H level signal is received, and the L level signal obtained by inverting the signal on the node 7 by the inverter circuit IV10 is received at the gate of the NMOS NT4. As a result, the transfer gate T4 is turned off.

Therefore, based on the first control signal A,
An electric signal corresponding to a signal input from external terminal DQ1 via transfer gate T3 is applied to memory block # 1.
On the data bus DB1.

In the period between times t2 and t3, NAND circuit NA4 receiving H-level signal S2 and H-level second control signal B at its inputs outputs an L-level signal to node 7. Transfer gate T4 is a PMO
The gate of SPT4 receives the L-level signal on node 7, and the gate of NMOS NT4 receives the H-level signal obtained by inverting the signal on node 7 by inverter circuit IV10. As a result, the transfer gate T4 becomes conductive.

On the other hand, NAND circuit NA receiving signal S2 at H level and first control signal A at L level at its inputs is provided.
3 outputs an H level signal to the node 6. The transfer gate T3 receives the H-level signal on the node 6 at the gate of the PMOS PT3, and receives the L-level signal obtained by inverting the signal on the node 6 by the inverter circuit IV9 at the gate of the NMOS NT3. As a result, the transfer gate T3 is turned off.

Therefore, based on the second control signal B,
The electric signal corresponding to the signal input from the external terminal DQ1 via the transfer gate T4 is stored in the memory block # 2.
On the data bus DB2.

Since the signal S2 output from the inverter circuit IV6 is at the L level during the period when the / WE signal is at the H level, that is, during the non-write operation (before time t1 and after time t3 in FIG. 8), NAND circuit NA3 receiving this outputs an H level signal to node 6,
AND circuit NA4 outputs an H-level signal to node 7. As a result, transfer gates T3 and T4
Become non-conductive. Therefore, both data bus DB1 and data bus DB2 are electrically disconnected from external terminal TQ1.

Incidentally, the data input buffer circuit 31 having the data bus DB3 of the memory block # 3 and the data bus DB4 of the memory block # 4 as output lines and the external terminal DQ2 as an input terminal is the same as the data input buffer circuit 30 and the data input buffer circuit 30. The same operation is performed.

That is, the semiconductor memory device 100 has the / W
When the E signal becomes L level and a write operation is performed, the first control signal A and the second control signal B are controlled based on the / RAS signal, the / CAS1 signal, and the / CAS2 signal, and are received from the external terminal DQ1. The selected data is selectively written to a specific memory cell MC of memory block # 1 or memory block # 2, and the data received from external terminal DQ2 is selectively specified for memory block # 3 or memory block # 4. Is written to the memory cell MC.

As described above, semiconductor memory device 100
Divides the memory blocks # 1 to # 4 into two groups, shares an input circuit and an output circuit in a group unit, and the input circuit and the output circuit of each group share one external terminal. use. The / RAS signal and / CAS1 signal and / C
With a control signal based on the AS2 signal, any one of the two memory blocks in each group can be selected to perform a write operation or a read operation.

In the first embodiment of the present invention, four memory blocks have been described. However, by providing K input circuits, K output circuits, and K external terminals, 2K blocks are provided. It can also be realized in a semiconductor memory device having the above memory block.

On the other hand, the number of external terminals for inputting the / CAS signal is increased, and four control signals are generated by using four / CAS signals, thereby forming four memory blocks as one group and one external terminal. To selectively output any one of the read data of the four memory blocks, and selectively write the input data from one external terminal to any one of the four memory blocks. It is also possible to insert.

[Second Embodiment] FIG. 9 is a schematic block diagram showing an overall configuration of a semiconductor memory device 200 according to a second embodiment of the present invention. Components in common with the conventional example shown in FIG. With the same reference numbers and reference signs,
The description is omitted.

The difference between the semiconductor memory device 200 according to the second embodiment of the present invention and the conventional example shown in FIG. 17 is as follows. That is, the terminal for inputting the * OE signal is 1
However, two terminals for inputting the * OE1 signal and the * OE2 signal are provided, the internal control signal generation circuit 11 is provided instead of the internal control signal generation circuit 51, and the data output buffer circuit is provided. Including data output buffer circuits 22 and 23 instead of 70 to 73;
Data input buffer circuits 32 and 33 are provided in place of data input buffer circuits 80 to 83, and main amplifiers 64 and 65 are provided in place of main amplifiers 60 to 63.

The * OE1 signal input from the / OE1 pin and the * OE2 signal input from the / OE2 pin are supplied to the internal control signal generation circuit 11 by the / OE1 signal and the / OE signal.
It becomes the E2 signal. Both the / OE1 signal and the / OE2 signal have the same function as the conventional / OE signal.

FIG. 10 is a timing chart showing a relationship between a write operation and a read operation of semiconductor memory device 200 according to the second embodiment of the present invention. In FIG.
RA indicates an internal row address signal, and CA indicates an internal column address signal.

Semiconductor memory device 200 divides memory blocks # 1 to # 4 into a group of memory blocks # 1 and # 2 and a group of memory blocks # 3 and # 4. An output circuit is provided, and the input and output circuits of each group use a common external terminal to input and output data. The input and output operations of each group are controlled by a third control signal C based on a / RAS signal and a / CAS signal described later. That is, during the read operation, the third control signal C
And according to the / OE1 and / OE2 signals,
Any one of the two memory blocks in each group is selected to perform a read operation, and at the time of a write operation, any one of the two memory blocks in each group is selected according to the / OE2 signal. Or 1
Write operation is performed by selecting one memory block.

More specifically, semiconductor memory device 200
Performs the following operation during a read operation (/ OE1 or / OE2 is at L level). When L level / OE1 signal is received using third control signal C generated from / RAS and / CAS signals, memory cell MC located at address Z1 of memory block # 1 is received from external terminal DQ1. An electric signal O1 corresponding to a write signal is output, and an electric signal O3 corresponding to a write signal of a memory cell MC located at address Z1 of memory block # 3 is output from external terminal DQ2.

On receiving L level / OE2 signal, external terminal DQ1 outputs electric signal O2 corresponding to the write signal of memory cell MC located at address Z1 of memory block # 2, and outputs external terminal DQ2 Outputs an electrical signal O4 corresponding to the write signal of the memory cell MC located at the address Z1 of the memory block # 4.

Semiconductor memory device 200 performs the following operation during a write operation (/ WE signal is at L level). Using a third control signal C generated from the / RAS signal and the / CAS signal, / OE2
When a signal is received, input signal W received from external terminal DQ1 is input.
1 is written to the memory cell MC located at the address Z2 of the memory block # 1, and the input signal W3 received from the external terminal DQ2 is written to the memory cell MC located at the address Z2 of the memory block # 3.

On the other hand, when receiving the / OE2 signal at L level, input signal W2 received from external terminal DQ1 is written to memory cell MC located at address Z2 of memory block # 2, and input signal W4 received from external terminal DQ2 is stored in the memory. Memory cell M located at address Z2 of block # 4
Write to C.

The configuration and operation of semiconductor memory device 200 will be described below. FIG. 11 is a circuit diagram showing a configuration of a main part of internal control signal generation circuit 11 according to the second embodiment of the present invention. The internal control signal generation circuit 11 includes a NOR circuit N
OR3. NOR circuit NOR3 receives a / RAS signal and a / CAS signal generated by internal control signal generation circuit 11 at its input, and outputs a third control signal C. continue,
The operation of the internal control signal generation circuit 11 will be described.

FIG. 12 is a timing chart showing the relationship between input and output signals in internal control signal generation circuit 11 according to the first embodiment of the present invention. It is a timing chart figure. Before time t1, / CA at H level
NOR circuit NOR3 receiving the S signal at its input outputs an L level signal.

In a period from time t1 to time t2, NOR circuit NOR3 receiving L level / RAS signal and L level / CAS signal at its input outputs an H level signal.

After time t2, H level / C
NOR circuit NOR3 receiving the AS signal at its input outputs an L-level signal.

Therefore, the output of the NOR circuit NOR3,
That is, the third control signal C includes the / RAS signal and / C
When both AS signals are at L level, the signal goes high, and when the / RAS signal or / CAS signal goes high, the signal goes low.

That is, during the memory operation of semiconductor memory device 200, internal control signal generation circuit 11 generates third control signal C at H level.

FIG. 13 is a circuit diagram schematically showing a configuration of data output buffer circuit 22 according to the second embodiment of the present invention.

The data output buffer circuit 22 includes an AND circuit AN1, inverter circuits IV11 to IV16, N
AND circuits NA5 and NA6 and transfer gate T
5, T6.

The AND circuit AN1 receives the / WE signal and the third control signal C generated by the internal control signal generating circuit 11, and outputs a signal S3.

NAND circuit NA5 outputs signals S3 and / OE.
1 signal and the signal / O
The E2 signal is received at the input, and the operation result is output to the node 12.

NAND circuit NA6 outputs signal S3 and / O
An input receives an E1 signal and a signal obtained by inverting a / OE2 signal by an inverter circuit IV12, and outputs an operation result to a node 13.

The transfer gate T5 is a PMOS P
T5 and NMOS NT5. One conduction terminal of each of the PMOS PT5 and the NMOS NT5 is
Connected at node 14, each other conducting terminal
Connected to data bus DB1 of memory block # 1.
The PMOS PT5 has a node 12 at its gate.
Upon receiving the above signal, the NMOS NT5 receives at its gate the output signal of the inverter circuit IV13 (the inverted signal of the signal on the node 12).

The transfer gate T6 is a PMOS P
T6 and NMOS NT6. One conduction terminal of each of the PMOS PT6 and the NMOS NT6 is
Connected at node 14, each other conducting terminal
Connected to data bus DB2 of memory block # 2.
Then, the PMOS PT6 has a node 13 at its gate.
In response to the above signal, NMOS NT6 receives at its gate the output signal of inverter circuit IV14 (inverted signal on node 13).

Inverter circuit IV15 is connected to node 14, receives the outputs of transfer gates T5 and T6, and inverts and amplifies them. On the other hand, the inverter circuit I
V16 inverts and amplifies the output of the inverter circuit IV15 and outputs it to the external terminal DQ1.

Data output buffer circuit 23 has the same configuration as data output buffer circuit 22, and has a data bus D
A data bus DB3 is used as an input line instead of B1, and a data bus DB4 is used as an input line instead of the data bus DB2,
The external terminal DQ2 is used as an output terminal instead of the external terminal DQ1.

FIG. 14 is a timing chart showing the relationship between input and output signals in data output buffer circuit 22 according to the second embodiment of the present invention.

Thereafter, the / RAS signal falls to the L level and the / CAS signal subsequently falls to the L level, thereby selecting a specific memory cell MC of each of memory blocks # 1 to # 4. , And / WE
The description will be made assuming that the signal is at the H level.

Further, as described with reference to FIG. 12, it is assumed that internal control signal generating circuit 11 has generated third control signal C shown in FIG. 14 based on the / RAS signal and the / CAS signal.

In the period from time t0 to t2,
Since the / WE signal is at the H level and the third control signal C is at the H level, the AND circuit AN1 in FIG.
Is at the H level.

During the period from time t0 to time t1, the H level signal S3, the H level signal obtained by inverting the L level / OE1 signal by the inverter circuit IV11, and the H level signal / OE1 are output.
NAND circuit NA5 receiving OE2 signal at its input
Outputs an L-level signal to the node 12. The transfer gate T5 receives the L-level signal on the node 12 at the gate of the PMOS PT5, and outputs the NMOS NT5
The signal on node 12 to the inverter circuit IV1
3 receives the inverted H-level signal. As a result, the transfer gate T5 becomes conductive.

On the other hand, NAND circuit NA6 receiving at its inputs H-level signal S3, L-level / OE1 signal, and L-level signal obtained by inverting H-level / OE2 signal at inverter circuit IV12 receives H-level signal S3. Is output to the node 13. The transfer gate T6 is a PMOS
The gate of PT6 receives the H-level signal on node 13, and the gate of NMOS NT6 receives the L-level signal obtained by inverting the signal on node 13 by inverter circuit IV14. As a result, the transfer gate T6 is turned off.

Therefore, if the / OE1 signal is at the L level, an electric signal corresponding to the signal on data bus DB1 of memory block # 1 is output from external terminal DQ1 via transfer gate T5.

In the period from time t1 to t2, H level signal 3S, H level / OE1 signal, and L level / OE2 signal are inverted by inverter circuit IV12 to H level.
Level signal and NAND circuit NA6 receiving at its input
Outputs an L-level signal to the node 13. The transfer gate T6 receives the L-level signal on the node 13 at the gate of the PMOS PT6, and
The signal on node 13 to the inverter circuit IV1
4 receives the inverted H-level signal. As a result, the transfer gate T6 becomes conductive.

On the other hand, NAND circuit NA5 receiving at its inputs H-level signal S3, L-level signal obtained by inverting H-level / OE1 signal at inverter circuit IV11, and L-level / OE2 signal is at H-level. Is output to the node 12. The transfer gate T5 is a PMOS
The gate of PT5 receives the H-level signal on node 12, and the gate of NMOS NT5 receives the L-level signal obtained by inverting the signal on node 12 by inverter circuit IV13. As a result, the transfer gate T5 is turned off.

Therefore, if the / OE2 signal is at L level, an electric signal corresponding to the signal on data bus DB2 of memory block # 2 is output from external terminal DQ1 via transfer gate T6.

Note that the / OE1 signal and / OE2 signal are both at the H level, that is, at the time of non-read operation (FIG. 14).
Before time t0 and after time t2), the signal output from inverter circuit IV11 and inverter circuit I
Since both signals output from V12 are at L level, NAND circuit NA5 outputs an H level signal to node 12, and NAND circuit NA6 outputs an H level signal to node 13. As a result, transfer gates T5 and T6 are both turned off. Therefore, the data bus DB1 and the data bus DB2 are
Both are electrically disconnected from the external terminal DQ1.

The data output buffer circuit 23 having the data bus DB3 of the memory block # 3 and the data bus DB4 of the memory block # 4 as input lines, and having the external terminal DQ2 as an output terminal, is basically the same as the data output buffer circuit 22. The same operation is performed.

That is, the semiconductor memory device 200 has the / O
When the E1 signal or the / OE2 signal becomes L level and the read operation starts, the external terminal receives the control of the third control signal C based on the / RAS signal and the / CAS signal and responds to the / OE1 signal and / OE2 signal. DQ1 selectively outputs data of a specific memory cell MC in memory block # 1 or memory block # 2, and outputs an external terminal DQ1.
2 selectively outputs data of a specific memory cell MC in memory block # 3 or memory block # 4.

FIG. 15 is a circuit diagram schematically showing a configuration of data input buffer circuit 32 according to the second embodiment of the present invention.

The data input buffer circuit 32 includes inverter circuits IV17 to IV22 and NAND circuits NA7, N
A8, and transfer gates T7 and T8.

Inverter circuit IV17 receives the / WE signal at its input, and outputs a signal S4 obtained by inverting this signal.

The NAND circuit NA7 outputs the signal S4 and / O
E2 signal and the third signal output from the internal control signal generation circuit 11.
And outputs the operation result to the node 14.

The NAND circuit NA8 outputs the signal S4 and / O
A signal obtained by inverting the signal E2 by the inverter circuit IV8 and the third control signal C are received at its inputs, and the operation result is output to the node 15.

The inverter circuit IV21 has an external terminal DQ
The signal received from 1 is inverted and amplified. On the other hand, inverter circuit IV22 further inverts and amplifies this signal and outputs it to node 16.

The transfer gate T7 is a PMOS P
T7 and NMOS NT7. One conduction terminal of each of the PMOS PT7 and the NMOS NT7 is
Connected to data bus DB1 of memory block # 1, and the other conductive terminal of each is connected to node 16.
Then, the PMOS PT7 has a node 14 connected to its gate.
Receiving the above signal, NMOS NT7 receives at its gate the output signal of inverter circuit IV19 (inverted signal on node 14).

The transfer gate T8 is a PMOS P
T8 and NMOS NT8. One conduction terminal of each of the PMOS PT8 and the NMOS NT8 is
Memory block # 2 is connected to data bus DB2, and the other conductive terminal is connected to node 16.
Then, the PMOS PT8 has a node 15 at its gate.
Receiving the above signal, NMOS NT8 receives at its gate the output signal of inverter circuit IV20 (inverted signal on node 15).

The data input buffer circuit 33 has the same configuration as the data input buffer circuit 32. The external terminal DQ2 is used as an input terminal instead of the external terminal DQ1, and the data bus DB3 is used as an output line instead of the data bus DB1. And the data bus DB4 is used as an output line instead of the data bus DB2.

FIG. 16 is a timing chart showing an input / output relationship of signals of data input buffer circuit 32 according to the second embodiment of the present invention.

Thereafter, the / RAS signal falls to the L level and the / CAS signal subsequently falls to the L level, whereby a specific memory cell MC of each of memory blocks # 1 to # 4 is selected. The description is made as follows. Further, as already described with reference to FIG. 12, it is assumed that the internal control signal generation circuit 11 has generated the third control signal C shown in FIG.

Since signal / WE is at L level during time t0 to t2, signal S4 output from inverter circuit IV17 in FIG. 14 is at H level.

In the period from time t0 to time t1, H
Level signal S4, H level second control signal C,
NAND circuit NA7 receiving / OE signal at H level
Outputs an L-level signal to the node 14. The transfer gate T7 has a node 1 connected to the gate of the PMOS PT7.
4 and the gate of NMOS NT7 applies the signal on node 14 to inverter circuit IV19.
Receives the inverted H level signal. As a result, the transfer gate T7 becomes conductive.

On the other hand, NAND circuit NA8 receiving H-level signal S4, H-level third control signal C, and L-level signal obtained by inverting H-level / OE2 signal by inverter circuit IV18 is connected to node 15 at node 15. To output an H-level signal. The transfer gate T8 is a PMOS PT
The gate of No. 8 receives the H-level signal on node 15 and the gate of NMOS NT8 receives the L-level signal obtained by inverting the signal on node 15 by inverter circuit IV20. As a result, the transfer gate T8 is turned off.

Therefore, if the / OE2 signal is at the H level, an electric signal corresponding to the signal input from external terminal DQ1 is transmitted onto data bus DB1 of memory block # 1 via transfer gate T8.

In the period from time t1 to time t2, the H level signal S4, the H level third control signal C, and the H level signal obtained by inverting the L level / OE2 signal by the inverter circuit IV18 are output. NAND circuit N received at input
A8 outputs an L-level signal to node 15. The transfer gate T8 receives the L-level signal on the node 15 at the gate of the PMOS PT8, and
The signal on node 15 to inverter circuit IV2
It receives an H-level signal inverted at 0. As a result, the transfer gate T8 becomes conductive.

On the other hand, NAND circuit NA7 receiving H-level signal S4, H-level third control signal C, and L-level / OE2 signal at its inputs outputs an H-level signal to node 14. . Transfer gate T7 is P
The gate of the MOS PT7 receives the H-level signal on the node 14, and the gate of the NMOS NT7 receives the L-level signal obtained by inverting the signal on the node 14 by the inverter circuit IV19. As a result, the transfer gate T7 is turned off.

Therefore, if the / OE2 signal is at the L level, an electric signal corresponding to the signal input from external terminal DQ1 is transmitted to data bus DB2 of memory block # 2 via transfer gate T8.

Note that while the / WE signal is at the L level,
That is, during the non-write operation (in FIG. 16, before time t0 and after time t2), signal S4 output from inverter circuit IV17 is at L level, and therefore N is received.
AND circuit NA7 outputs an H-level signal to node 14, and NAND circuit NA8 outputs an H-level signal to node 15. As a result, the transfer gate T7
And T8 are both turned off. Therefore,
Data bus DB1 and data bus DB2 are both electrically disconnected from external terminal DQ1.

Incidentally, the data input buffer circuit 33 having the data bus DB3 of the memory block # 3 and the data bus DB4 of the memory block # 4 as output lines and the external terminal DQ2 as an input terminal is the same as the data input buffer circuit 32 and the data input buffer circuit 32. The same operation is performed.

That is, the semiconductor memory device 200 has the / W
When the E signal becomes L level and the writing operation is performed, the data received from the external terminal DQ1 is selectively controlled based on the / OE2 signal under the control of the third control signal C based on the / RAS signal and the / CAS signal. Is written to a specific memory cell MC of memory block # 1 or memory block # 2, and data received from external terminal DQ2 is selectively written to specific memory cell M of memory block # 3 or memory block # 4.
Write to C.

As described above, the semiconductor memory device 20
0 indicates that the memory blocks # 1 to # 4 are divided into two groups, the input circuit and the output circuit are shared in group units, and the input circuit and the output circuit of each group share one external terminal. To use. The operation of the input circuit and the output circuit is controlled by a control signal based on the / RAS signal and the / CAS signal input from the outside, and the / OE1 signal and /
In response to the OE2 signal, one of the two memory blocks in the group is selected to output read data to the outside, and in response to the / OE2 signal, one of the two memory blocks in the group is output. Data can be written by selecting any one of the memory blocks.

In the first embodiment of the present invention, four memory blocks have been described. However, by providing K input circuits, K output circuits, and K external terminals, 2K blocks are provided. It can also be realized in a semiconductor memory device having the above memory block.

On the other hand, the number of pins for inputting the / OE signal is further increased, and two or more memory blocks are grouped into one group to selectively output one of the read data of the M memory blocks from one external terminal. Alternatively, input data from one external terminal can be selectively written to any one of the M memory blocks.

[0171]

As described above, according to the semiconductor memory device of the present invention, the capacity of the memory cell array is increased and the chip area is reduced even if the number of memory blocks included in one chip increases. It is possible to operate a plurality of memory blocks without increasing.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a timing chart illustrating a relationship between a read operation and a write operation of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 3 is a circuit diagram schematically showing a configuration of a main part of an internal control signal generation circuit according to the first embodiment of the present invention.

FIG. 4 is a timing chart showing a relationship between input and output signals of an internal control signal generation circuit according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram schematically showing a configuration of a data output buffer circuit according to the first embodiment of the present invention.

FIG. 6 is a timing chart illustrating a relationship between input and output signals of the data output buffer circuit according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram schematically showing a configuration of a data input buffer circuit according to the first embodiment of the present invention.

FIG. 8 is a timing chart illustrating a relationship between input and output signals of the data input buffer circuit according to the first embodiment of the present invention.

FIG. 9 is a schematic block diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 10 is a timing chart showing a relationship between input and output signals of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 11 is a circuit diagram schematically showing a configuration of a main part of an internal control signal generation circuit according to a second embodiment of the present invention.

FIG. 12 is a timing chart illustrating a relationship between input and output signals of an internal control signal generation circuit according to a second embodiment of the present invention.

FIG. 13 is a circuit diagram schematically showing a configuration of a data output buffer circuit according to a second embodiment of the present invention.

FIG. 14 is a timing chart showing a relationship between input and output signals of a data output buffer circuit according to a second embodiment of the present invention.

FIG. 15 is a circuit diagram schematically showing a configuration of a data input buffer circuit according to a second embodiment of the present invention.

FIG. 16 is a timing chart showing a relationship between input and output signals of the data input buffer circuit according to the second embodiment of the present invention.

FIG. 17 is a schematic block diagram showing a configuration of a conventional semiconductor memory device including a plurality of memory blocks.

FIG. 18 is a circuit diagram schematically showing a configuration of a memory block in a conventional semiconductor memory device.

FIG. 19 is a timing chart of a read operation and a write operation in a conventional semiconductor memory device having four memory blocks.

[Explanation of symbols]

50 memory cell array, # 1 to # 4 memory blocks, 51, 10, 11 internal control signal generation circuits, 70 to 7
3, 20 to 23 data output buffer circuits, 80 to 8
3, 30 to 33 data input buffer circuits, 52 address buffers, 53 row decoders, 54 column decoders,
60 to 65 main amplifier, DB1 to DB4 data bus, 56 sense amplifier, 57 I / O gate, IV1
To IV22 inverter circuit, NA1 to NA8 NAND
Circuit, AN1 AND circuit, NOR1 and NOR2 NO
R circuit, T1-T8 transfer gate, NT1-N
T8 NMOS, PT1 to PT8 PMOS.

Claims (6)

[Claims] 1. A semiconductor memory device comprising a plurality of memory blocks in which specific memory cells are simultaneously selected by a common address signal, wherein a first input signal from a first external terminal and a second A second input signal from an external terminal and a third input signal from a third external terminal.
Signal generating means for generating a control signal in response to the input signal of the plurality of memory blocks; and dividing the plurality of memory blocks so as to form a group for each of the two memory blocks; A plurality of group-based output control means for outputting read data from any of the memory blocks belonging to the group to the outside, and selectively inputting external input data to each of the groups according to the control signal. A plurality of group-based input control means for writing data to any one of the memory blocks belonging thereto; outputting data to the outside of the output control means, and outputting data from outside the input control means. A semiconductor memory device in which input is performed by one common data input / output terminal in the group unit. 2. The method according to claim 1, wherein the control signal includes a first control signal and a second control signal.
A control signal, wherein each of the output control means outputs read data from a first memory block belonging to the group from the data input / output external terminal according to a first control signal; Means for outputting read data from a second memory block belonging to the group from the data input / output external terminal in response to a second control signal, wherein each of the input control means comprises: The data input from the terminal
Means for transmitting the data to the first memory block in response to the control signal of
Means for transmitting to the second memory block in response to the control signal of (i). 3. The signal according to claim 1, wherein the first input signal is a / RAS signal, the second input signal is a first / CAS signal, and the third input signal is a second / CAS signal. 2. The semiconductor memory device according to claim 1, wherein 4. A semiconductor memory device comprising a plurality of memory blocks in which specific memory cells are simultaneously selected by a common address signal, wherein a first input signal from a first external terminal and a second Signal generation means for generating a control signal in response to a second input signal from an external terminal; dividing the plurality of memory blocks so as to form a group for each of the two memory blocks; , The third input signal from the third external terminal and the fourth
A plurality of group-based output control means for selectively outputting read data from any of the memory blocks belonging to the respective groups to the outside in response to a fourth input signal from an external terminal of A plurality of the group units, wherein input data from the outside is selectively used as write data of one of the memory blocks belonging to the respective groups in accordance with the control signal and the fourth input signal. A semiconductor memory, comprising: input control means; and outputting data to the outside of the output control means and inputting data from the outside of the input control means to one common data input / output terminal in the group unit. apparatus. 5. The output control means outputs read data from a first memory block belonging to the group from the data input / output external terminal according to the control signal and the third input signal. Means for outputting read data from a second memory block belonging to the group from the data input / output external terminal in response to the control signal and the fourth input signal; A means for transmitting, to the first memory block, data input from the data input / output external terminal if the fourth input signal is at a first logical level, in response to the control signal; If the fourth input signal is a second logic level different from the first logic level in accordance with the signal, the data input from the data input / output external terminal is transferred to the second memory. And means for transmitting to the lock, the semiconductor memory device according to claim 4, wherein. 6. The signal according to claim 1, wherein the first input signal is a / RAS signal, the second input signal is a / CAS signal, the third input signal is a first / OE signal, 5. The semiconductor memory device according to claim 4, wherein said fourth input signal is a second / OE signal.