JPH10124388A - Storage controller - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce the number of times of referencing / updating cache management information and increase the throughput of a storage control device. A storage control device (3) has N cache memories (35-1 to 35-N) and N control memories (34-1 to 3-N) for storing cache management information (343), and refers to the cache management information (343). In addition, it controls the data transfer between the processing device 1 and the storage device 2 via the cache memory 35 while updating. Management information on the entire cache memory 35 is stored in each of the N control memories 34-1 to N.
The control memories 34-1 to 34-N are set to be N-fold. The control units of the channel adapter 31 and the drive adapter 32 refer to the management information in one of the control memories 34-i when referencing the management information, and refer to the N-multiplexed management information when updating the management information. Update N times simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage control device connected to an upper processing device and a lower storage device and controlling data transfer between the processing device and the storage device via a cache memory possessed by the storage control device. In particular, the present invention relates to a storage control device that controls data transfer via a cache memory while referring to and updating management information in a control memory.

[0002]

2. Description of the Related Art There is known a technique in which a cache memory is held in a storage control device, and data transfer between a processing device and a storage device is controlled via the cache memory.
The data stored in the cache memory has two states. One is a state in which data has already been written to the storage device. This state is called clean. The other is a state where data has not yet been written to the storage device. This state is called dirty. Dirty data must not be erased from the cache memory until writing to the storage device is completed.

Japanese Patent Laid-Open Publication No. Hei 5-189314 discloses a cache memory control method for a storage control device having a plurality of cache memories backed up by a battery. This storage control device has a cache memory whose power supply is duplicated by a battery backup. This cache memory is divided into N, and the storage control device stores the clean data read from the storage device in accordance with a command from the host device in any one of the N divided cache memories.
Dirty data written to the cache memory in accordance with a command from the higher-level device is redundantly stored in any two of the N divided cache memories. This technique guarantees the preservation of information in the cache memory in the event of a failure in the storage controller, and can prevent performance degradation.

To manage a cache memory, cache management information is required. Usually, it has one piece of cache management information to manage one piece of cache memory.
Therefore, to manage N cache memories, it is common to have N cache management information.

[0005]

According to the prior art, N
N cache management information for independently managing each cache memory is provided corresponding to the cache memories. The cache memory management information includes information for managing whether or not specific data is stored in the cache memory, information for managing clean data and dirty data when data is stored in the cache memory, and information in the cache memory. And information for managing the use / non-use of the storage area. For example, when a data read request or a write request is issued from the processing device, if the requested data is in the cache memory, the data in the cache memory may be transferred to the processing device or updated. For this reason, the storage control device searches for information for managing the storage status of data in the cache memory. However, since it is unknown which cache memory contains the desired data,
All of the cache management information had to be retrieved. When the data write request is issued from the processing device and there is no desired data in the cache memory, the storage control device stores the dirty data in the two cache memories in a duplicated manner in the cache memory. It is necessary to secure an area, create a table for managing dirty data, and update information for managing a storage area in the cache memory. Therefore, the storage controller is 2
These processes have to be repeated twice for one piece of cache management information. As described above, the number of dynamic steps when executing the control program in the storage control device for referring / updating the cache management information increases, and the traffic on the bus inside the storage control device increases. As a result, the storage control device The throughput of
There is a problem that the response time of the storage control device to the processing device increases.

SUMMARY OF THE INVENTION An object of the present invention is to reduce the number of times the cache management information is referred / updated, and to improve the throughput of the storage control device and the response time of the storage control device to the processing device.

[0007]

According to the present invention, management information relating to the entirety of N cache memories is collectively set in each of N control memories, and management information having the same contents is duplicated for the N control memories. When the cache management information is referred to, the management information in one of the control memories is referred to, and when the cache management information is updated, the N pieces of management information in the N control memories are simultaneously updated. A storage control device is characterized.

Further, according to the present invention, each of the N control memories manages management information indicating whether data is stored in the cache memory (information for managing whether or not data is stored in the cache memory and clean data / dirty data). Table), the management information on the entire N cache memories is collectively collected and stored in N control memories in a N-fold manner, and the management information for managing the use / non-use of the storage area in the cache memory is controlled by each control. The management information about the storage area in the cache memory corresponding to each memory is retained, and when the former management information is referred to and updated, the reference of one management information and the N-multiplexing of the N management information are performed as described above. When the management information is updated and the latter management information is referred to and updated, the management information in the control memory corresponding to the specific cache memory is updated. Wherein the reference and update the storage control device.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

(1) First Embodiment FIG. 1 is a configuration diagram of a system centering on a storage controller according to a first embodiment of the present invention. The system includes a storage control device 3, a processing device 1 as a higher-order device thereof, and a storage device 2 as a lower-order device. The storage controller 3 includes a channel adapter 31, a drive adapter 32, N cache memories 35-1 to N, and N control memories 34-1 to 34-1.
N, a control memory control unit 37, and an internal bus 33 interconnecting these mechanisms as shown.

The cache memories 35-1 to 35-N are buffer memories for holding data read from the storage device 2 and data to be written to the storage device 2 in block units. Clean data or dirty data is stored in unused blocks. Is stored. Here, the block is a fixed size storage area in the cache memory 35. Clean data is stored in only one cache memory 35-i, and dirty data is stored in any two cache memories 35-i and 35-j. Hereinafter, when any one of the cache memories 35 is referred to, it is expressed as a cache memory 35-i.
Is expressed as

The control memories 34-1 to 34-N have information for managing the presence / absence of data, information for managing clean data / dirty data, and information for managing use / non-use of blocks in all the cache memories 35. . Each of the control memories 34-i holds the same management information. Hereinafter, when any one of the control memories 34 is indicated, it is expressed as a control memory 34-i, and when all the control memories 34-1 to N are collectively referred to as a control memory 34.

The channel adapter 31 has an interface for controlling data transfer with the processing device 1 and an interface for controlling data transfer via the internal bus 33. The channel read controller 311 and the channel write controller 311 serve as control units. The control unit 312 includes a cache control unit 36 which is common to the drive adapter 32. The hardware of the channel adapter 31 includes an interface (not shown), a processor, and a memory. These control units are realized by executing a control program stored in the memory.

The drive adapter 32 has an interface for controlling data transfer to and from the storage device 2 and an interface for controlling data transfer via the internal bus 33. The drive read controller 321 and the drive write controller 321 serve as control units. It has a control unit 322. The hardware of the drive adapter 32 includes an interface (not shown),
It is composed of a processor and a memory. These control units are realized by executing a control program stored in the memory. The fact that there are a plurality of channel adapters 31 and a plurality of drive adapters 32 respectively indicates that the same control program can be executed multiple times.

The control memory control unit 37 includes a control memory 34
This is a memory control unit that controls -1 to N and is realized by a hardware circuit. When the specific control memory 34-i receives a specified read / write command from the channel adapter 31 or the drive adapter 32 via the internal bus 33, the control memory control unit 37 stores the specified control memory 34-i in the specified control memory 34-i. Refer to or update the storage area.
When receiving a single write command, a single address, and a single data item for which the N-fold update is designated, the control memory control unit 37 simultaneously updates the contents of the N control memories 34-1 to 34-N.

The drive-side read control unit 321 executes data transfer from the storage device 2 to the cache memory 35, and the channel-side read control unit 311 executes data transfer from the cache memory 35 to the processing device 1. Further, the channel side write control unit 312 executes data transfer from the processing device 1 to the cache memory 35, and the drive side write control unit 322 executes data transfer from the cache memory 35 to the storage device 2.

The cache control unit 36 allocates / releases blocks in the cache memory 35. When allocating cache, N for clean data
Blocks are allocated from any one of the cache memories 35-1 to 35-N, and blocks are allocated from any two of the N cache memories 35-1 to 35-N for dirty data.

FIG. 2 is a diagram for explaining the relationship between the data structure of management information stored in each control memory 34-i and the cache memory 35. Each control memory 34-i stores storage controller management information 341, cache management information 343, and cache management information lock information 342. The storage control device management information 341 is composed of information transferred between adapters, information for managing a processing wait state, and the like. The cache management information lock information 342 stores lock information for excluding access to the area of the cache management information 343 between adapters.

The cache management information 343 includes a hit / miss determination table 3431 and a data management table 343.
2. It comprises a data management table unused queue 3434, an allocated block management table 3433, and an allocated block management table unused queue 3435.

The hit / miss determination table 3431 stores the identifier of the data stored in the cache memory 35. That is, each entry of the hit / miss determination table 3431 stores a pointer to the data management table 3432 corresponding to a specific area in the storage device 2. Initial values are set for unused entries.

The data management table 3432 is a table for managing the state of data stored in the cache memory 35, which is allocated to one or a plurality of blocks allocated to data. Each data management table 3432 includes lock information 34321, read storage information 34322, write storage information 34323, a read pointer 34324, a write pointer 34325, and a backward pointer 34326. Lock information 34
321 stores lock information for exclusive access to the data management table 3432. The read pointer 34324 is stored in the allocation block management table 34.
This is a pointer that points to a block 33 that is allocated as a read surface of the cache memory 35. The write pointer 34325 is a pointer that points to the allocation block management table 3433, and is a pointer that points to a block allocated as a write surface of the cache memory 35. In the case of clean data, the write pointer 34325 is not used, and an initial value is set. The read storage information 34322 is information representing whether or not data is stored in each area when a block on the read surface is subdivided into a plurality of areas, using a bitmap. The write storage information 34323 is information expressing whether or not data is stored in each area when a block on the write surface is subdivided into a plurality of areas, using a bitmap. The backward pointer 34326 is stored in the data management table 3
When the pointer 432 is unused, the backward pointer 34
A pointer that points to another unused data management table 3432 linked to 326 is stored. When the data management table 3432 is in use, the backward pointer 3432
6 is set to an initial value.

Data management table unused queue 3434
Is information for managing the unused data management table 3432 as a queue. The unused queue header 34341 is the data management table 34 at the head of the queue.
32341 and the end pointer 34341 to the data management table 3432 at the end of the queue.
And 2. The unused data management table 3432 starts from the data management table 3432 pointed to by the leading pointer 343411 and is sequentially linked by the backward pointer 34326 to the ending pointer 343412.
A chain that terminates in the data management table 3432 pointed by is formed. It is desirable that the data management tables 3432 be provided in the same number as the total number of the allocation block management tables 3433 so that the data management table 3432 does not run short as the number of uses of the allocation block management table 3433 increases.

Allocation block management table 3433
Is a table for managing a block 351 which is an allocation unit of the cache memory 35, and one table is provided for each block 351. The cache management information 343 of each control memory 34-i manages a block 351 of the entire cache memory 35. The allocation block management table 3433 includes a block address 34331, a serial number 34332, and a backward pointer 34333. The block address 34331 stores the address of the assigned block 351. The block address is transmitted from the cache memory 35-1 to the cache memory 3
Addresses are assigned to the cache memories 35-i through, for example, an identifier for identifying each cache memory 35-i and the address of a block in each cache memory 35-i. The serial number 34332 is a serial number starting from 0, and stores a serial number when a plurality of allocated block management tables 3433 are secured for the read pointer 34324 or the write pointer 34325 of one data management table 3432. Backward pointer 34333
Is a pointer to the allocation block management table 3433 linked to the allocation block management table 3433.

The allocated block management table unused queue 3435 is an unused allocated block management table 3 corresponding to an unallocated block 351.
This is information for managing 433 as a queue, and the unused block management table 3433 is managed for each cache memory 35-i. Unassigned block management table unused queue header 34351 of each assigned block management table unused queue 3435
Are the start pointer 343511 and the end pointer 3435
12 and the number of entries 343513. Allocation block management table unused queue header 3435
1 is the allocation block management table 34 at the head of the queue.
33, and the end pointer 343512 is an allocation block management table 3433 at the end of the queue.
Is a pointer to The number of entries 343513 stores the number of the allocation block management table 3433 connected to the unused queue. The control memories 34-1 and 3-3
The storage areas inside 4-2,... And 34-N are accessible by the same address, and store the same information as described above. Control memory 34-1 to N
The management information can be referred / updated by designating one of them, or the entire control memory 34 can be updated simultaneously.

FIG. 3 is a flowchart showing the flow of the process of the channel side read control unit 311. The channel-side read control unit 311 starts a channel-side read process in response to a read request from the processing device 1. First, the channel-side read control unit 311 transfers control to the cache control unit 36 to execute data lock acquisition processing for the target data (step 3111). The cache control unit 36
It is determined whether the target data exists in the cache memory 35 by referring to the hit / miss determination table 3431,
If the data does not exist in the cache memory 35, the cache memory allocation processing is performed, and the data management table 3432 relating to the target data is locked. The channel-side read control unit 311 checks the return code issued by the cache control unit 36, and if the return code is “cannot acquire the target data lock” (step 3112 Yes), suspends the processing until the lock on the target data is released. Then (step 3113), the process returns to step 3111. If the return code is not “target data lock cannot be acquired” (step 3112 No), it is determined whether the return code is “target data exists” (step 3114). When the return code is "target data exists" (step 31)
14Yes), since there is no need to transfer the target data from the storage device 2 to the cache memory 35, step 311
Go to 7. If the return code is not “there is target data” (No in step 3114), the drive-side read control unit 32 via the storage control device management information 341 transfers the target data from the storage device 2 to the cache memory 35.
1 (step 3115). Thereafter, the process is set to a standby state until the transfer of the target data from the storage device 2 to the cache memory 35 is completed (step 3116).
After the waiting state is released, the cache memory 35 is searched by tracing the allocation block management table 3433 of the data.
The target data being transferred is transferred to the processing device 1 (step 31).
17). Finally, the control is transferred to the cache control unit 36 to execute the data lock release processing (step 3118).
The cache control unit 36 releases the lock of the data management table 3432 relating to the target data. When referring to the cache management information 343, only a single control memory 34-i is referred.

FIG. 4 is a flowchart showing the flow of the processing of the drive-side read control unit 321. When instructed by the channel-side read control unit 311, the drive-side read control unit 321 refers to the read storage information 34322 of the instructed read target data (step 321).
1). Next, based on the read storage information 34322, the part of the target data not yet stored in the cache memory 35 is transferred from the storage device 2 to the block of the block address specified by the read pointer 34324 (step 3212). Next, the read storage information 34322 is updated for the transferred part (step 3213). Finally, the transfer end wait state of the channel side read processing is released via the storage controller management information 341 (step 32).
14). When referring to the cache management information 343, only a single control memory 34-i is referred. When updating the cache management information 343, the control memory 34 is updated N times through the control memory control unit 37.

FIG. 5 is a flowchart showing the flow of the processing of the channel side write control unit 312. The channel side write control unit 312 starts the channel side write processing in response to a write request from the processing device 1. First, the channel-side write control unit 312 transfers control to the cache control unit 36 to execute data lock acquisition processing on the target data (step 3120). The cache control unit 36 is notified that the request source is the channel side write control unit 312. The cache control unit 36 determines whether the target data exists in the cache memory 35 with reference to the hit / miss determination table 3431, and
If it does not exist, the cache memory allocation process is performed and the data management table 3432 relating to the target data is locked. The channel-side write control unit 312 checks the return code issued by the cache control unit 36, and if the return code is “cannot acquire the target data lock” (step 3121 Yes), suspends the processing until the lock on the target data is released. Then (step 3122), the process returns to step 3120. When the return code is not “target data lock cannot be acquired” (step 3121N)
o), by tracing the allocation block management table 3433 and writing the write data from the processing device 1 to the read pointer 343
The data is stored in both areas on the 24th and 34325 sides (step 3123). The bit map of the read storage information 34322 and the write storage information 34323 is updated according to the range of the data occupying the block of the cache memory 35 by storing the write data (step 3124). Finally, the control is transferred to the cache control unit 36 to execute the data lock release processing (step 312).
5). The cache control unit 36 releases the lock of the data management table 3432 relating to the target data. The single control memory 34-i when referring to the cache management information 343 and the N-fold update of the control memory 34 when updating are as described above.

FIG. 6 is a flowchart showing the flow of processing of the drive-side write control unit 322. The drive-side write control unit 322 executes drive-side write processing asynchronously with a read / write request from the processing device 1. First, the drive-side write control unit 322 sends each data management table 34 via the hit / miss determination table 3431.
32, and refers to the lock information 34321 and the write pointer 34325 to select any dirty data in which the unlocked write pointer 34325 is stored (step 3220). Next, the control is transferred to the cache control unit 36 to execute data lock acquisition processing for the target data (step 3221). The cache control unit 36 is notified that the request source is the drive-side write control unit 322. Cache control unit 36
Locks the data management table 3432 relating to the target data. The drive-side write control unit 322 checks the return code issued by the cache control unit 36, and if the return code is “unable to acquire the target data lock” (Step 3222 Yes), returns to Step 3220 and retries the selection of dirty data. I do. If the return code is not “target data lock unavailable” (step 3222 No), dirty data pointed to via the allocation block management table 3433 is written to the storage device 2 (step 3223). Finally, the control is transferred to the cache control unit 36 to execute the data lock release processing (step 3224). The cache control unit 36
The block in the cache memory 35 pointed to by the write pointer 34325 for the target data management table 3432 is released, and the lock of the data management table 3432 is released. The reference to the single control memory 34-i when referring to the cache management information 343 is as described above.

FIG. 7 is a flowchart showing the flow of the data lock acquisition process of the cache control unit 36. The cache control unit 36 first acquires a lock of the cache management information lock 342 in order to exclude access to the cache management information 343 between adapters (step 360).
1). Next, the hit / miss determination table 3431 is referred to to determine whether the target data is stored in the cache memory 35 (step 3602). If the data management table 3432 relating to the target data does not exist (No in step 3603), the unused data management table 3 is stored in the data management table unused queue 3434.
432 (step 3604), and this data management table 34 is stored in the hit / miss determination table 3431.
Add an entry for 32 and go to step 3608. If the data management table 3432 exists (step 3603 Yes), the lock information 34321 in the data management table 3432 of the target data is referred to (step 3605). If already locked (Step 3
606 Yes), “unable to acquire target data lock” is set as the return code of the data lock acquisition process (step 3620), and the process goes to step 3622. If the data has not been locked (No in step 3606), the request source of the data lock acquisition processing is the drive-side write control unit 322.
It is determined whether or not this is the drive-side write process (step 3607). In the case of drive-side write processing (step 3607 Yes), the process simply proceeds to write dirty data to the storage device 2 and does not need to newly secure a cache memory area. If not drive-side write processing (step 360)
7), the read securing flag and the write securing flag, which are local flags referred to in the data lock acquisition processing and the cache memory allocation processing described later, are set to off (step 3608). Next, reference is made to the read storage information 34322 of the target data (step 3609).
If all of the target data exists in the cache memory 35 (step 3610 Yes), the read securing flag is kept off, and the process proceeds to step 3612. If not all of the target data exists in the cache memory 35 (step 3610 No), the read securing flag is set to on (step 3611), and the process proceeds to step 3612. Next, it is determined whether or not the request source of the data lock acquisition processing is the channel side write processing of the channel side write control unit 312 (step 3612). If it is not the channel-side write process (No at Step 3612), the process goes to Step 3616 because it is not necessary to secure an area necessary for storing the dirty data in the cache memory in duplicate. If it is a channel side write process (step 361)
2Yes), reference is made to the write storage information 34323 of the target data (step 3613). If all of the target data exists in the cache memory 35 (step 3614)
Yes), the light securing flag is kept off, and the flow proceeds to step 3616. If all of the target data does not exist in the cache memory 35 (step 3614N
o), and set the write securing flag to ON (step 36)
15) Go to step 3616. Next, it is determined whether any one of the read securing flag and the write securing flag is set to ON (step 3616). If neither flag is set to ON (step 3616 No), the return code indicates “there is data to be present”.
Is set (step 3619), and the procedure goes to step 3621. If any of the flags is set to ON (step 3616 Yes), the cache memory allocation process is executed (step 3617). After executing the cache memory allocation process, the process returns to the data lock acquisition process, and sets "no target data" as the return code of the data lock acquisition process (step 3618). Next, the lock information 3 in the data management table 3432 of the target data
Acquire the lock for 4321 (step 362)
1). Finally, the lock of the cache management information lock 342 is released (step 3622). A pointer to the data management table 3432 relating to the target data is reported to the requester of the data lock acquisition processing together with the return code. The single control memory 34-i when referring to the cache management information 343 and the N-fold update of the control memory 34 when updating are as described above.

FIG. 8 is a flowchart showing the flow of the cache memory allocation process of the cache control unit 36. The cache control unit 36 first determines whether the read securing flag is set to ON (step 36).
30). If it is not set to ON (step 363)
0No), the process proceeds to step 3633 because it is not necessary to secure the cache memory 35 on the read pointer 34324 side. If it is set to ON (step 3630Y
es) In order to secure an area necessary for storing the target data, the allocation block management table 3433 is allocated to the read pointer 34324 side in an arbitrary one of the N unit cache memories 35-1 to 35-N. It is secured from the management table unused queue 3435 (step 3631). However, when the allocation block management table 3433 is already connected to the read pointer 34324 side, the allocation block management table 3433
33 is allocated from the same allocated block management table unused queue 3435 as that which has been allocated. Next, the number of entries 343513 of the allocated block management table unused queue 3435 that has allocated the allocated block management table 3433 is subtracted by the number of allocated block management tables that have allocated (step 3632). Next, it is determined whether or not the write securing flag is set to ON (step 3633). If it is not set to ON (No in step 3633), the process ends because it is not necessary to secure the cache memory 35 on the side of the write pointer 34325. If it is set to ON (step 3633Ye
s) The cache memory 35-i secured on the read pointer 34324 side as the block management table 3433 allocated to the write pointer 34325 side to secure an area necessary for storing the target dirty data.
Any one of the allocated block management table unused queues 3 in the N-1 cache memories 35-j except for
435 (step 3634). However, when the allocation block management table 3433 is already connected to the write pointer 34325 side, the same allocation block management table unused queue 34 as that in which the allocation block management table 3433 is secured.
Secure from 35. Next, the number of entries 343513 of the allocated block management table unused queue 3435 that has allocated the allocated block management table 3433 is decremented by the number of allocated block management tables that have allocated (step 3635). The single control memory 34-i when referring to the cache management information 343 and the N-fold update of the control memory 34 when updating are as described above.

FIG. 9 is a flowchart showing the flow of the data lock release processing of the cache control unit 36. The cache control unit 36 first acquires a lock of the cache management information lock 342 to exclude access to the cache management information 343 between adapters (step 366).
0). Next, it is determined whether or not the request source of the data lock release processing is the drive side write processing of the drive side write control unit 322 (step 3661). If it is not a drive-side write process (No in step 3661), the process goes to step 3665 since the release of the cache memory is unnecessary. If it is drive-side write processing (step 36)
61Yes), the block on the side of the write pointer 34325 storing one of the duplicated dirty data is released. First, the write storage information 34323 is initialized (step 3662). Next, the number of entries 343513 of the allocation block management table unused queue 3435 which is the release destination of the allocation block management table 3433 secured on the side of the write pointer 34325 is added by the number of allocation block management tables to be released (step 36).
63). Next, the allocation block management table 3433 secured on the side of the write pointer 34325 is released from the allocation block management table unused queue 3435 which is the release destination.
To initialize the write pointer 34325 (step 3664). As a result, the data on the read pointer 34324 side of the same data management table 3432 becomes clean data. Next, the lock information 34321 in the data management table 3432 of the target data is initialized,
The lock on the target data is released (step 3665).
Next, the lock release wait state of the data in another process is released (step 3666). Finally, the lock of the cache management information lock 342 is released (step 3667). Single control memory 34-i when referring to cache management information 343, N of control memory 34 when updating
The multiple updates are as described above.

In this embodiment, an allocation block management table unused queue 3435 is provided for each cache memory 35-i, and the number of entries 343513 in the allocation block management table unused queue header 34351.
Is constantly updated, the number of unused blocks in each cache memory 35-i can be monitored, and only the clean data is stored in the cache memory 35-i in which the number of unused blocks is determined to be insufficient. It is possible to control by a control program to release a block and add it to the allocated block management table unused queue 3435 corresponding to the cache memory 35-i.

According to the present embodiment, the read pointer 34324 and the write pointer 34325, the read storage information 34322 and the write storage information 34323 are provided in one data management table 3432, and one cache management information 343 is a block of the entire cache memory 35. Is stored in the data management table unused queue 3434 that manages the cache management information 343. Therefore, when the cache management information 343 is referred to, the process of referring to the single control memory 34-i only needs to be performed sequentially, and the process that overlaps the two cache management information is performed. Need not be repeated. N sets of control memories 34-
When updating 1 to N, N of the control memory control unit 37
Since the simultaneous N-fold update can be used by the multiple update function, when the cache management information 343 is updated, the entire control memory 34 can be updated on the program in the procedure for updating the single control memory 34-i. There is no need to repeat the update process for two pieces of cache management information. With the above advantages, the number of dynamic steps when executing the control program can be reduced, the traffic on the internal bus 33 when referring to / updating the control memory 34 can be reduced, and the throughput of the storage control device 3 and the response to the processing device 1 can be reduced. Can be improved. In particular, since the control memory 34 is made N-fold, the reliability of the control memory 34 is improved.

(2) Second Embodiment In the first embodiment, since the cache management information 343 holds the allocation block management table 3433 for the entire cache memory 35, each control memory 34-
i requires a storage capacity commensurate with this. In the second embodiment, an allocation block management table 3433 is held for each control memory 34-i, and the storage capacity required by each control memory 34-i is reduced.

FIG. 10 is a configuration diagram of a system centering on the storage controller of the second embodiment. The difference from the configuration of the first embodiment is that the cache management information 343 of the first embodiment is divided into common cache management information 344 and individual cache management information 345, and the individual cache management information 345 is stored in the corresponding control memory 34-. The point is that only the allocation block management table 3433 for i is retained. The contents of the management information represented by the same reference numerals as those in the first embodiment are the same as those in the first embodiment.

FIG. 11 is a diagram showing the structure of management information stored in the control memory 34-i. The common cache management information 344 includes the hit / miss determination table 3431, the data management table 3432, and the data management table unused queue 34 included in the cache management information 343.
34. The individual cache management information 345 includes an allocation block management table 3433 and an allocation block management table unused queue 3435. However, unlike the cache management information 343, the allocation block management table 34 in the individual cache management information 345
33 holds only those relating to the corresponding control memory 34-i. The read pointer 34324 and the write pointer 34325 in the data management table 3432 specify the identifier of the control memory 34-i and the address in the control memory 34-i.

In the second embodiment, in the read processing and the write processing, the allocation block management table 3433 is used.
Is accessed, the identifier of the control memory 34-i holding the allocated block management table 3433 is specified. In the cache memory allocation process of the cache control unit 36, an unused allocation block management table 3433 is allocated from the allocation block management table unused queue 3435 of the control memory 34-i corresponding to the cache memory 35-i in which the block has been allocated. . Other processing procedures are the same as in the first embodiment.

According to the second embodiment, the management information indicating the data storage status in the cache memory 35 in the common cache management information 344 is controlled by the control memory controller 3.
7, the control memory 34 is updated N times. For management information for managing blocks in the individual cache management information 345, only the control memory 34-i corresponding to the target cache memory 35-i is referenced or updated. According to the second embodiment, when dirty data is stored in the cache memory 35 as in the first embodiment, redundant processing is not required. Further, the storage capacity of each control memory 34-i for holding the allocation block management table 3433 is reduced as compared with the first embodiment.

[0039]

According to the present invention, it is sufficient to always refer to and update the cache management information of a single control memory from the viewpoint of the control program of the storage controller, and to refer to the cache management information for two or more control memories. It is possible to reduce the number of dynamic steps when executing the control program, reduce the traffic on the internal bus, increase the throughput of the storage control device, and shorten the response time to the processing device without repeating the update. it can.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of a first embodiment.

FIG. 2 is a diagram illustrating the relationship between the data configuration of cache management information and a cache memory according to the first embodiment.

FIG. 3 is a flowchart illustrating a processing flow of a channel side read control unit 311 according to the embodiment.

FIG. 4 is a flowchart illustrating a processing flow of a drive-side read control unit 321 according to the embodiment.

FIG. 5 is a flowchart illustrating a processing flow of a channel side write control unit 312 according to the embodiment.

FIG. 6 is a flowchart illustrating a processing flow of a drive-side write control unit 322 according to the embodiment.

FIG. 7 is a flowchart illustrating a flow of a data lock acquisition process of a cache control unit 36 according to the embodiment.

FIG. 8 is a flowchart illustrating a flow of a cache memory allocation process of a cache control unit 36 according to the embodiment.

FIG. 9 is a flowchart illustrating a flow of a data lock release process of the cache control unit according to the embodiment.

FIG. 10 is a system configuration diagram of a second embodiment.

FIG. 11 is a diagram illustrating a data configuration of cache management information according to the second embodiment.

[Explanation of symbols]

3: storage controller, 34: control memory, 343: cache management information, 344: common cache management information, 34
5: individual cache management information, 35: cache memory, 36: cache control unit, 37: control memory control unit

Claims (2)

[Claims] An information processing system, comprising: N (N is an integer of 2 or more) cache memories connected to an upper processing unit and a lower storage device; and information for managing the cache memories corresponding to each of the cache memories. N control memories for storing
A storage control device having means for controlling data transfer between the processing device and the storage device via the cache memory while referring to and updating management information in the control memory; , N sets of management information relating to the entire N cache memories are set for the N control memories, and the control unit refers to the management information in any one of the control memories when referring to the management information. See,
A storage control device, comprising means for simultaneously updating N pieces of management information in N control memories when updating the management information. 2. An N (N is an integer of 2 or more) cache memories connected to an upper processing unit and a lower storage device, and information for managing the cache memories corresponding to each of the cache memories. N control memories for storing
A storage control device having means for controlling data transfer between the processing device and the storage device via the cache memory while referring to and updating management information in the control memory; Of the first management information indicating the storage status of data in the cache memory, the management information relating to the entire N cache memories is held N times for the N control memories, and stored in the cache memory. As for the second management information for managing the area, management information about the storage area in the cache memory corresponding to each control memory is held, and when the control means refers to the first management information, any one of the control information is stored. When the first management information is updated with reference to the first management information in the control memory of N, N pieces of the first management information in the N control memories are simultaneously updated. And a means for referencing and updating the second management information in the control memory corresponding to the specific cache memory when referring to and updating the second management information. .