JPH10116232A - Memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory system which can be packaged with a high density and has a low defect occurrence rate. SOLUTION: This memory system is constituted by including light memory bare chips 11 to 18 utilized to store and read data and a standby bear chip 19. Those memory bare chips are packaged on a printed wiring board by cutting memory chips formed in successive areas on a semiconductor wafer. Fuses 20 are connected to data input/output terminals of the memory bare chips 11 to 18. Further, light fuses 20 each are connected to data input/output terminals of the memory bare chip 10, and the other-end sides of those fuses 2 are connected to the other-end sides of the fuses 20 of the memory bare chips 11 to 18. Those fuses 20 are switched to replace a memory bare chip which becomes defective with the standby memory bare chip 19.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory system in which a plurality of memory chips are mounted on a printed wiring board.

[0002]

2. Description of the Related Art In portable devices such as cellular phones and electronic organizers, miniaturization of products and reduction of power consumption are important factors influencing product sales. For this reason, conventionally, the number of components to be mounted has been reduced by using a multifunctional LSI, and the size has been reduced by mounting both sides on a multilayer printed wiring board. It has also been generalized to improve the mounting density by so-called flip-chip mounting in which a bare chip from which an LSI package is removed is directly mounted on a printed wiring board.

By the way, most electronic devices such as portable devices include a CPU therein, and the performance of a product is often determined by a failure of a program for operating the CPU. In addition, the amount of programs has become enormous along with the diversification of functions, and a desired processing speed cannot be obtained unless a large amount of memory is mounted.

[0004]

However, when a large amount of memory is mounted on a printed wiring board, there is a problem that the printed wiring board becomes large. For this reason, in an electronic device such as a computer requiring a large amount of memory, a SIMM (Single In-line Memory Module) in which a plurality of memory chips are mounted on a small printed wiring board 2 is vertically or obliquely mounted on a main board. Is common. However, since the SIMM uses a commercially available memory chip as a component, there is a limit in reducing the outer dimensions of the SIMM, and the main substrate must be increased according to the outer dimensions of the SIMM and the number of SIMMs to be mounted.

[0005] If some of the memory chips mounted on a memory board such as a SIMM have a defect, the entire memory board has conventionally been treated as a defect. Therefore, before mounting the memory chips, each memory chip must be carefully inspected for defects.
There is a problem in that a considerable amount of time is required for the inspection, and even if the inspection takes a long time, the defect rate in manufacturing the memory board does not decrease.

An object of the present invention has been made in view of the above points, and an object of the present invention is to provide a memory system capable of mounting a memory chip on a printed wiring board at a high density and reducing the incidence of defects. To provide.

[0007]

According to a first aspect of the present invention, there is provided a memory system in which a plurality of memory chips formed in a continuous area on a semiconductor wafer are mounted on a printed wiring board. When some of the memory chips are defective, a wiring switching circuit is formed on the printed wiring board to substitute for another memory chip. It is not necessary to treat the memory system as defective, and the defective rate at the time of manufacturing the memory system can be reduced.

According to a second aspect of the present invention, a data input / output terminal of a memory chip to be subjected to data storage and data reading and a data input / output terminal of a spare memory chip are selectively selected and externally connected. Since the terminals are electrically connected, the use of a defective memory chip can be prohibited only by switching the data input / output terminals, and a spare memory chip can be used instead.

In the memory system according to the third aspect, by controlling the signal level of the enable terminal of each memory chip, use of a defective memory chip can be prohibited and a spare memory chip can be used instead.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a memory system to which the present invention is applied will be specifically described with reference to the drawings.

First Embodiment FIG. 1 is a circuit diagram of a first embodiment of a memory system, FIG. 2 is a plan view showing a state in which the circuit of FIG. 1 is mounted on a printed wiring board 2, and FIG. FIG.
FIG. 2 is an enlarged view of a part of the printed wiring board 2 of FIG.
As shown in FIG. 2, the memory system according to the present embodiment is configured such that a plurality of memory bare chips 1 formed in a continuous area on a semiconductor wafer are closely connected to each other without being divided into individual pieces. It is mounted on the board 2.
One end side P of the printed wiring board 2 is processed into a shape attachable to a connector on a main board (not shown), and a plurality of patterns 3 for conducting with the connector on the main board are formed in this portion. I have. As shown in FIG. 3, each of these patterns 3 is electrically connected to the input / output pad 6 of the bare chip for memory 1 via the pad 4 on the printed wiring board 2 and the bonding wire 5. Each of the patterns 3 shown in FIG. 2 corresponds to the external connection terminal I / O shown in FIG.
0-31, A0-9, RAS, CAS, WE, OE.

As shown in FIG. 1, the memory system according to the present embodiment includes nine memory bare chips 11 to 19, of which eight memory bare chips 11 are provided.
To 18 are actually used as memories, and the remaining one memory bare chip 19 is used as a spare. FIG. 1 shows an example in which a 1M × 4 bit DRAM is used as each of the memory bare chips 11 to 19, and the memory capacity of the entire memory system is 32 bits × 4M bytes.

Each of the memory bare chips 11 to 19 is shown in FIG.
As shown in FIG. 1, address terminals A0 to A9, data input / output terminals D0 to D3, RAS terminal, CAS terminal,
It has an E (write enable) terminal and an OE (out enable) terminal. The connection of the terminals other than the data input / output terminals D0 to D3 is the same for all of the nine memory bare chips 11 to 19. Each of the data input / output terminals D0 to D3 of the memory bare chips 11 to 18 is connected to a fuse 20, and these fuses 20 are normally conductive, and are cut off when irradiated with a laser beam. FIG. 1 shows only one fuse 20 connected to the data input / output terminals D0 to D3 of each of the memory bare chips 11 to 18 for simplification. Terminal D
A fuse 20 is separately connected to each of the terminals 0 to D3. Eight fuses 20 are connected to the data input / output terminals D0 to D3 of the spare memory bare chip 19, respectively.
Fuse 20 for bare chips 11 to 18 for memory
Are connected respectively to the other end side.

For each of the fuses 20 shown in FIG. 1, it is possible to arbitrarily select whether or not to cut off conduction for each fuse. For example, when none of the memory bare chips 11 to 18 is defective, as shown in FIG. 4, the data input / output terminals D0 to D0 of the spare memory bare chip 19 are provided.
All fuses 20 connected to D3 are blown.
On the other hand, for example, when the memory bare chip 11 shown in FIG. 1 is defective, as shown in FIG. 5, all the fuses 20 connected to the data input / output terminals D0 to D3 of the defective memory bare chip 11 become defective. The spare memory bare chip 19 connected to these fuses 20 is cut.
Fuse 20 is not blown. As a result, the use of the defective memory bare chip 11 is prohibited, and the spare memory bare chip 19 is used as a part of the memory instead.

Note that pull-up resistors R are attached to the other ends of all the fuses 20 so that the potentials of the external connection terminals I / O0 to I / O31 do not become unstable when the fuses 20 are cut. I have.

As described above, in the memory system of the first embodiment, the spare memory bear chip 19 is mounted on the printed wiring board 2 in advance, and the data input / output terminals D0 to D0 of the spare memory bear chip 19 are mounted. D3 and the data input / output terminals D0 to D3 of the other memory bare chips 11 to 18 can be alternatively selected by the fuse 20, so that even if a part of the memory bare chips 11 to 18 is defective, It is possible to prohibit the use of the memory bare chip which has been replaced by the above and use a spare memory bare chip 19 instead. For this reason, when only a part of the memory bare chip mounted on the printed wiring board 2 is defective, the entire memory system does not have to be treated as defective, and the defective rate at the time of manufacturing the memory system is reduced.

The memory system according to the first embodiment includes a memory bare chip 1 formed on a semiconductor wafer.
Are cut out into a plurality of sets, and they are mounted on the printed wiring board 2 in close contact with each other without being separated, so that high-density mounting is possible as compared with a conventional case of mounting a packaged memory. .

Further, by simply cutting a desired fuse, a defective memory bare chip and a spare memory bare chip 1 can be obtained.
9, the printed wiring board 2
Switching to the spare memory bare chip 19 becomes possible without complicating the upper wiring.

[Second Embodiment] In the first embodiment,
Although the example in which the fuse 20 is used to switch the memory bare chip has been described, the switching may be performed by a dip switch, a gate, or the like instead of the fuse 20.

FIG. 6 is a circuit diagram of a memory system according to the second embodiment. The memory system according to the second embodiment has a total of nine memory bear chips 11 to 19 including one spare memory bear chip 19, as in the first embodiment.
Each of the memory bare chips 11 to 18 is connected to data control circuits 21 to 28 whose detailed configuration is shown in FIG.

Each of the data control circuits 21 to 28 has a 4-bit configuration, and a circuit corresponding to one bit is shown in FIG. 7 is connected to the data input / output terminals D0 of the memory bare chips 11 to 18 shown in FIG. 6, and the terminal B1 is connected to the data input / output terminals D0 of the spare memory bare chip 19 shown in FIG. Is connected. Also,
For example, an external connection terminal I / O0 shown in FIG.
Is connected to the terminal S, for example, the contact SL0 of the DIP switch 29 shown in detail in FIG. The dip switch 29 is composed of eight switches. By switching these switches, the contacts SL0 to SL7 are set to either a high level or a low level.
To SL7 are connected to the data control circuits 21 to 28, respectively.

Data control circuits 21 to 2 shown in detail in FIG.
Numeral 8 selects one of the terminals A1 to B4 and the terminals B1 to B4 according to the logic of the terminal S, and switches the direction of data flow according to the logic of the WE (write enable) terminal. .

FIG. 9 is a logic diagram showing the operation of data control circuits 21 to 28 shown in detail in FIG. As shown in FIG. 9, when the terminal S is at the low level and the WE terminal is at the low level, the tristate buffer 31 is enabled, and the data input from the terminals D1 to D4 are output from the terminals A1 to A4, respectively. The data is stored in the corresponding memory bare chips 11 to 18. When the terminal S is at the low level and the WE terminal is at the high level, the tristate buffer 32 is enabled, the data input from the terminals A1 to A4 are output from the terminals D1 to D4, and the corresponding external connection terminal I It is output to the outside via / O0-31.
When the terminal S is at the high level and the WE terminal is at the low level, the data input from the terminals D1 to D4 is not transmitted to the terminal B1.
Output from ~ 4. When the terminal S is at a high level and WE
When the terminals are at the high level, the data input from the terminals B1 to B4 is output from the terminals D1 to D4.

For example, if there is no defect in any of the memory bare chips 11 to 18, the dips shown in FIG. 9 are set so that all the S terminals of the data control circuits 21 to 28 shown in FIG. The switch 29 is switched.
This allows the data control circuits 21 to 28 to control the tri-state buffers 31, 3 according to the signal level of the WE terminal.
2 is enabled. On the other hand, for example, when the memory bare chip 18 shown in FIG. 6 is defective, the dip switch 29 is switched so that only the contact SL7 of the dip switch 29 becomes high level. Thereby, the memory bare chip 18 is replaced with the spare memory bare chip 19.

As described above, according to the second embodiment, the data control circuits 21 to 28 are respectively connected to the memory bare chips 11 to 18, and the data passing through the data control circuits 21 to 28 are changed depending on the state of the dip switch 29. Since the flow is controlled, the defective memory bare chip can be replaced with the spare memory bare chip 19 only by switching the dip switch 29, and the replacement of the memory bare chip can be easily performed manually.

[Third Embodiment] In a third embodiment, a fuse is connected to an OE (out enable) terminal of a memory bare chip.

FIG. 10 is a circuit diagram of a memory system according to the third embodiment. As shown in FIG.
The fuses 20 are connected to the OE terminals of the eight memory bare chips 11 to 18 mounted thereon, respectively.
The data input / output terminals D0 to D3 of the spare memory bare chip 19 are connected to the data input / output terminals of the memory bare chips 11 to 18 via different fuses 20, respectively.

For example, if none of the memory bare chips 11 to 18 has a defect, all the fuses 20 connected to the respective OE terminals are not cut, and the data input / output terminals of the spare memory bare chip 19 are not cut. All the fuses 20 connected to D0 to D3 are blown. This allows
Data storage and data reading are performed on the memory bare chips 11 to 18.

On the other hand, for example, when the memory bare chip 11 is defective, all the fuses 20 connected to the OE terminal of the chip 11 are cut. Further, the fuses 20 of the spare memory bare chips 19 connected to the data input / output terminals D0 to D3 of the chip 11 are not blown, and the fuses 20 of the other spare memory bare chips 19 are blown.

In FIG. 10, the fuse 2 is connected to the OE terminal.
In the example described above, a fuse is connected to the WE terminal, the RAS terminal, and the CAS terminal to connect the bare chip 1 for memory.
9 may be switched.

In each of the above embodiments, an example is described in which only one spare memory bare chip 19 is provided. However, a plurality of bare memory chips may be provided as spare. Further, the type and number of the memory bare chips constituting the memory system are not limited to the above embodiments.

Further, in the above-described first and third embodiments, the example in which the fuse 20 is connected to the data input / output terminal of each memory bare chip has been described. Instead of the fuse 20, a mechanical device such as a dip switch is used. Other switching means, or an electrical switching means such as a transistor. Alternatively, instead of the fuse 20, a wiring pattern formed on the printed wiring board 2 may be directly burned off by a laser.

[0033]

As described above in detail, according to the present invention, a plurality of memory chips formed on a semiconductor wafer are mounted in close contact with a printed wiring board, and a part of the memory chips is Used for storing and reading data, and using other memory chips as spares, even if a part of the memory chip used for storing and reading data becomes defective, it is replaced with another memory chip without removing the memory chip. be able to. Therefore, the defective rate at the time of manufacturing the memory system is reduced, and the cost of parts can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of a memory system.

FIG. 2 is a plan view showing a state where the circuit of FIG. 1 is mounted on a printed wiring board.

FIG. 3 is an enlarged view of a part of the printed wiring board of FIG. 2;

FIG. 4 is a circuit diagram showing a state where some of the fuses shown in FIG. 1 are cut.

FIG. 5 is a circuit diagram showing a state where some of the fuses shown in FIG. 1 are cut.

FIG. 6 is a circuit diagram of a memory system according to a second embodiment.

FIG. 7 is a circuit diagram showing a detailed configuration of a data control circuit.

FIG. 8 is a circuit diagram showing details of a dip switch.

FIG. 9 is a logic diagram showing the operation of the data control circuit.

FIG. 10 is a circuit diagram of a memory system according to a third embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 11-19 Bare chip for memory 2 Printed wiring board 3 Pattern 4 Pad 5 Bonding wire 20 Fuse 21-28 Data control circuit 29 Dip switch

Claims (3)

[Claims] 1. A printed wiring board on which a plurality of memory chips formed in a continuous area on a semiconductor wafer are mounted in close contact with each other, and data is stored in some of the plurality of memory chips. And a memory access circuit for controlling data reading and a wiring switching circuit for switching wiring so that each of the some memory chips can be replaced with a memory chip other than the some memory chips on the printed wiring board. A memory system formed in a memory. 2. The printed wiring board according to claim 1, wherein each of the plurality of memory chips mounted on the printed wiring board has at least an address terminal and a data input / output terminal, A plurality of external connection terminals for performing transmission and reception, the wiring switching circuit includes, for each of the some memory chips, a data input / output terminal of the some memory chips and a part other than the some memory chips; A memory system, wherein a data input / output terminal of a memory chip is alternatively selected to conduct with the external connection terminal. 3. The circuit according to claim 1, wherein each of the plurality of memory chips mounted on the printed wiring board includes an enable terminal for controlling data storage or data reading, and A memory system for controlling a signal level of the enable terminal for each of the memory chips of the unit.