JPH1011412A - Initial processing load scattering system for multi-cpu constitution system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly start the scattering system without impairing the starting order by dividing the initial processing into blocks of every function that can be processed in parallel to each other and assigning these processing of divided blocks to all CPUs. SOLUTION: The initial processing is divided into blocks of every function that can be processed in parallel to each other. For instance, the check/clear processing of local memories 2-1 to 2-5 used for initial processing in common to all CPUs and the processing which loads the programs in the memories 2-1 to 2-5 from the system data are set in a block A. Then the processing is set in a block B to transfer the information contents of a common memory 3-2 under waiting to a backup memory 6. When the system is reset, the CPU 2-1 to 2-5 are also reset. Then the block A of the processing common to all CPUs is carried out. When the processing of the block A is completed, a CP# setting processing is carried out based on a CP# management table that is set in the memory 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an initial processing load distribution method for shortening a startup time in a multi-CPU system.

[0002]

2. Description of the Related Art Conventionally, in order to reduce processing time, a multi-CPU configuration system in which processing is performed in parallel by divided group CPUs is disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 5-12024.
It is well known as disclosed in Japanese Patent Publication No. FIG. 1 is a diagram showing an example of the configuration of such a conventional multi-CPU system. Note that the multi-C which is the object of the present invention
The PU configuration system is similar to the conventional one shown in FIG.

In the example shown in FIG. 1, a multi-CPU configuration system 1 has a desired mounting number, here, five CPUs.
2-1 to 2-5, and a common memory 3 comprising two systems of an active system and a standby system for storing dynamically changing data.
1, 3-2, a system data memory 4 for storing static data such as programs and system data, a common timer 5 for managing a timer necessary for sequence management,
It comprises a backup memory 6 for backing up data in the common memory 3-1 or 3-2, and an input / output device 7 serving as an interface with the outside. 8-1 to 8-2 are local memories provided in each of the CPUs 2-1 to 2-5.

FIG. 2 is a diagram for explaining a state of initial processing performed when the multi-CPU configuration system 1 shown in FIG. 1 is started. In FIG. 2, when a system reset is first performed, each device constituting the system is reset. Each of the CPUs 2-1 to 2-5 checks and clears the local memories 8-1 to 8-5 of each CPU, and loads a program stored in the system data memory 4. Next, in in the active common memory 3-1
The value of itial-FLAG (initial processing flag, described as I-FLG) is read out, and if the value of this I-FLG is "0", the CPU, here CPU 2-1 is in charge of the initial processing of the system. Master CPU to perform the operation. This I-
If the value of FLG is "1", other CPU
(Here, the CPU 2-5 is exemplified) is a master CPU.
Slave CP waits until the system completes the initial processing of the system
It becomes U.

The CPU 2-1 which has become the master CPU sequentially performs a save process for saving the data in the standby common memory 3-2 to the backup memory 6, and the active common memory 3-1 and the standby common memory 3 -2 check / clear processing, common timer 5 clear processing, data table on common memory 3-1 initialization,
The input / output device 7 is initialized, and complete-FLAG (initial processing completion flag, C-FLG)
) Is set to “1”. After the slave CPU 2-5 and the input / output device 7 recognize that the C-FLG has become "1", the system starts operation.

[0006]

In the conventional multi-CPU configuration system 1 described above, the initial processing is performed by one CPU.
(Master CPU) 2-1. Only the master CPU 2-1 performs a system reset due to a program upgrade, a change in system data, or the like. there were. In addition, there is also a problem that customer satisfaction is reduced because the service cannot be provided to the user until the system restarts operation. In addition, programs and common memories are expected to increase in order to provide high-quality services in the future, and there is a high possibility that the initial processing time will further increase, and in such a case, the above-described problems will become more prominent.

An object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide an initial processing load distribution method in a multi-CPU configuration system that enables a quick system startup without breaking the system startup sequence.

[0008]

The initial processing load distribution method in the multi-CPU configuration system of the present invention is a multi-C system.
This is a method of distributing the initial processing load performed when the system configured with PUs is started. The initial processing is divided into several blocks for each function that can process the parallel processing, and the blocks are allocated to all mounted CPUs. This is characterized in that the load of the initial processing is distributed by allocating the optimized processing.

More specifically, the initial processing load distribution method in the multi-CPU configuration system of the present invention is a method for distributing the initial processing load performed at the time of starting the system configured with the multi-CPU. The function is divided into several blocks for each function that can be processed, and the load of the initial processing is distributed by assigning the blocked processing to all mounted CPUs.

[0010] Further, when the block processing is assigned to the CPU, a complete state is checked so that the order of starting the system is not disturbed.

Further, the block-based initial processing is as follows:
Checking and clearing of local memory in each CPU common initial process, process of loading a program from system data to local memory, process of transferring information content of common memory (standby system) to backup memory, process of common memory (active system) One of check and clear processing, common memory (standby) check and clear processing, common timer timer clear processing, common data table initialization processing, input / output device initialization processing, and initialization processing completion flag ON processing It is characterized by being.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a diagram showing a state of blocking initial processing in the initial processing load distribution method in the multi-CPU configuration system of the present invention. In FIG. 3, the initial processing of the conventional multi-CPU configuration system shown in FIG. 2 is divided into blocks for each function that can be processed.
In the example shown in FIG. 3, in the block A, a check and clear process of the local memories 8-1 to 8-5 of the CPU common initial process and a program are loaded from the system data to the local memories 8-1 to 8-5. A process is set, and in block B, a process of transferring the information content of the standby common memory 3-2 to the backup memory 6 is set.
In block C, the check and clear processing of the working common memory 3-1 is set, in block D, the check and clear processing of the standby common memory 3-2 are set, and in block E, the common memory 3-1 is set. The timer clear processing of the timer 5 is set, the initialization processing of the common data table in the working common memory 3-1 is set in the block F, and the initialization processing of the input / output device 7 is set in the block G. The initial processing completion flag ON is set in the block H.

FIG. 4 is a diagram showing an example of the state of the initial processing performed when the multi-CPU configuration system using the initial processing distribution method of the present invention is started. In the example shown in FIG.
An example is shown in which three U2-1, 2-2, and 2-3 are mounted. First, in the multi-CPU configuration system shown in FIG.
... 2-3 are reset. Thereafter, block A of the CPU common processing shown in FIG. 3 is executed. Block A
After the above processing is completed, the CP # setting process shown in FIG. 8 is executed using the CP # management table shown in FIG.

The CP # setting process will be described with reference to FIG. 8. First, a LOCK is obtained from the CP # management table shown in FIG. 7 (801). If the content of LOCK is “OFF”, the following processing is performed.
K is obtained (802). Next, "O"
N "is set (803). Then, the CP # shown in FIG.
The CP # is acquired from the management table (804), and it is determined whether the CP # is less than 5 (805). If the CP # is less than 5, the acquired CP # is incremented by 1 and set in the table (806). If it is 5 or more, the following processing is performed. LOCK is set to “OFF” again (80
7). Here, the CPU 2-1 sets the CPU # 2 to CP # 0.
-2 is set to CP # 1, and CPU2-3 is set to CP # 2.

Next, based on the acquired CP #, each CPU determines a block to be processed according to a block processing dispatch (allocation) list shown in FIG. That is, by using the complete table shown in FIG. 6 set on the backup memory 6, the process of setting the complete state shown in FIG. 9 is executed.

The complete state setting processing will be described with reference to FIG. 9. The CPU 2-1 of CP # 0 determines the block B of the block B based on the CP # 0 part in the column of the number of mounted CPUs 3 in the list shown in FIG. The LOCK of the complete table shown in FIG. 6 is obtained (901). If the content of the LOCK is "OFF", the following processing is performed, and if the content is "ON", the LOCK is acquired again (902). "ON" is set to LOCK (903). Then, the complete state of the complete table shown in FIG. 6 of the block B is acquired (904), and if the complete state is “unexecuted” (905), “completed” is set as the complete state (906). If the complete state is other than "not implemented", an abnormal process is performed. Next, the current CP is
# Here, "0" is set (909). Finally LOC
K is set to “OFF” (910). After that, CP #
0 performs the processing of block B in the CPU 2-1.
After the processing is completed, the complete state “in progress” (907) is set to the complete state “completed” (908) in accordance with the complete state setting processing of FIG.

Similarly to the above, the CPU 2-2 of the CP # 1 performs the processing of the block C. CP # 2 CPU 2-3
Can be determined to perform the processing of the block D in accordance with the block processing dispatch table shown in FIG. 5, but the processing is started after the complete state of the block B becomes “completed” because there is a complete condition.

Here, since the first processing after the block A is completed, each CPU obtains the CP # from the CP # management table shown in FIG. 7 again, and obtains the CP # in the block processing dispatch list shown in FIG. Judge the part of the number of CPU implementation 3
The CPU 2-1 of CP # 0 executes the process of block E,
The CPU 2-2 of the CP # 1 executes the processing of the block F after the completion state of the block D becomes “completed”, and executes the processing of the block F.
The CPU 2-3 of P # 2 executes the processing of the block G.

Finally, the CPU 2-1 of CP # 0 determines the complete state of the blocks B to G, and all of them are "completed".
If so, the processing of the block H is executed. The CPUs 2-1 to 2-3 after the processing of each CP # and the input device 7 after the block G shown in FIG.
The acquisition is performed until the FLG becomes “1”, and after the recognition that the FLG has become “1”, the system starts operation.

[0020]

As is apparent from the above description, according to the initial processing load distribution method in the multi-CPU configuration system of the present invention, the initial processing is divided into a plurality of CPUs.
By executing the processing in parallel, the system can be started up quickly without losing the order of starting up the system.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an example of a multi-CPU configuration system to which the present invention is applied.

FIG. 2 is a diagram showing a state of a conventional initial process in a multi-CPU configuration system.

FIG. 3 is a diagram illustrating an example of blocking of initial processing in a multi-CPU configuration system.

FIG. 4 is a diagram showing a state of initial processing in a multi-CPU configuration system using the initial processing load distribution method of the present invention.

FIG. 5 is a diagram illustrating an example of a dispatch list of block processing.

FIG. 6 is a diagram illustrating an example of a complete table.

FIG. 7 illustrates an example of a CP # management table.

FIG. 8 is a flowchart illustrating an example of a CP # setting process.

FIG. 9 is a flowchart illustrating an example of a complete state setting process.

[Explanation of symbols]

 1 Multi-CPU Configuration System 2-1 to 2-5 CPU 3-1 and 3-2 Common Memory 4 System Data Memory 5 Common Timer 6 Backup Memory 7 I / O Device

Claims (3)

[Claims] 1. A method for distributing an initial processing load performed at the time of starting a system constituted by multiple CPUs, wherein the initial processing is divided into several blocks for each function capable of processing in parallel, and is implemented. All CPUs that are
An initial processing load distribution method in a multi-CPU system, wherein a load of initial processing is distributed by assigning a block of processing to a multi-CPU. 2. The multi-CPU configuration system according to claim 1, wherein a complete state is confirmed when assigning the block processing to the CPU, so that the start-up order of the system is maintained. Processing load distribution method. 3. The method according to claim 1, wherein the initial processing performed by the block is performed by each CP.
Checking and clearing of local memory of U common initial processing, processing of loading programs from system data to local memory, processing of transferring information content of common memory (standby system) to backup memory, checking of common memory (active system) And clear processing, common memory (standby system)
3. The processing of claim 1 or 2, wherein the processing is any one of a processing of checking and clearing, a processing of clearing a common timer, a processing of initializing a common data table, a processing of initializing an input / output device, and a processing of turning on an initial processing completion flag. An initial processing load distribution method in the multi-CPU configuration system described above.