JPH1011388A - Direct memory access controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make data transfer processing fast by sufficiently displaying direct memory access(DMA) transfer processing capability. SOLUTION: This direct access controller is provided with a transfer source address controller 21 which obtains the transfer source address of transfer data to be transferred next by adding unit addition data for updating successive addresses to a transfer source address and a transfer destination address controller 22 which obtains the transfer destination address of the transfer data to be transferred next by selecting the unit addition data for updating previously set transfer destination addition data and successive addresses according to whether the addresses of transfer data determined according to the transfer count number of a previously set successive address part and adding the selected addition data to the transfer destination address, thereby performing transfer processing only by DMA even when transfer data of successive addresses are transferred to intermittent addresses.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA control device for controlling data transfer processing by direct memory access (hereinafter, referred to as "DMA").

[0002]

2. Description of the Related Art DMA is a method for directly exchanging data between an input / output device and a memory or between memories, and is faster in data transfer than a normal method performed via a CPU (central processing unit). Since it can be delivered, it is often used in personal computers and the like.

A DMA controller (DMA controller) for controlling the DMA includes a character generator (C) provided in, for example, a ROM (Read Only Memory) or the like.
It is started when the image data extracted from G) is expanded in the image buffer. In this case, DMA hardware control could only be performed when the source address and the destination address were both continuous.

Accordingly, for example, a character "A" as shown in FIG. 9 and FIG.
If the character "A" is stored as image data at addresses 0 to 8 which are consecutive to the image buffer, this character "A" is included in a part of the image buffer as shown in FIG. 10 and FIG. D to transfer to the part
Along with the hardware control of the MA, software control as shown in FIG. 12 was required.

That is, first, a transfer source address “0”, a transfer destination address “500”, and a transfer number “2” of data at consecutive addresses are set in the DMA controller (for example, when down-counting from 2 to 0). Then, the DMA is started. Thus, hardware control of DMA transfer of data (x blocks) from address 0 to address 2 in the character generator (CG) shown in FIG. 11 is performed, and when the transfer processing of the x blocks is completed, the DMA stops. I do.

Then, it is determined whether or not the transfer to the continuous addresses of the transfer destination has been completed, that is, whether or not the terminal count has occurred. At this time, when it is determined that the terminal count has occurred, it is determined whether or not the DMA transfer of the last line of the transfer source address has been completed. In the case of this example, the data from address 0 to address 2 (x
Block) is not yet a final line transfer,
Proceed to the next process.

That is, the next transfer source address “3”, the transfer destination address “600” and the number of consecutive transfers “2” are set in the DMA controller, and the DMA is started. Thereby, the character generator (C) shown in FIG.
The hardware control of the DMA transfer of the data (y block) from address 3 to address 5 in G) is performed, and when the transfer processing of this y block is completed, the DMA stops again.

Then, it is determined whether or not a terminal count has occurred. At this time, when it is determined that the terminal count has occurred, it is determined whether or not the DMA transfer of the last line of the transfer source address has been completed. In the case of this example, since the data (y block) from address 3 to address 5 is not the transfer of the last line yet, the process proceeds to the next processing.

That is, the next transfer source address “6”, the transfer destination address “700” and the number of consecutive transfers “2” are set in the DMA controller, and the DMA is started. Thereby, the character generator (C) shown in FIG.
The hardware control of the DMA transfer of the data (z block) from address 6 to address 8 in G) is performed, and when the transfer processing of the z block ends, the DMA stops again.

Then, it is determined whether or not a terminal count has occurred. At this time, when it is determined that the terminal count has occurred, it is determined whether or not the DMA transfer of the last line of the transfer source address has been completed. In the case of this example, since the data (z block) from address 6 to address 8 is the transfer of the last line, this DMA control is ended.

As described above, the character generator (C
In the case of transferring the image data of the continuous address to the intermittent address in G), the hardware control is stopped every time the address becomes intermittent, and the setting of the transfer source address and the like and the DM
Software control for restarting A was necessary.

[0012]

However, such a D
In the MA control device, when the transfer destination address performs DMA transfer of intermittent data, the address is divided into portions that can be transferred continuously, the DMA controller is set a plurality of times, and the DMA is started each time. There is a problem that software control such as interrupt processing is required and complicated processing must be performed.

Further, since the DMA is stopped every time the address becomes a discontinuous portion, the entire transfer processing of image data and the like by the DMA takes time, and the effect of the DMA transfer control that the processing speed is fast is sufficiently achieved. There was also a problem that it was not possible. In particular, the larger the font data, the more times the DMA stops, and the lower the transfer processing speed. For example, in normal CG data, DMA stops about 24 times per character, so that one page 100
In the case of a character, DMA stops 2400 times.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a direct memory access control device capable of speeding up data transfer processing by sufficiently exhibiting transfer processing capability by direct memory access.

[0015]

According to the first aspect of the present invention, there is provided a direct communication system in which a data transfer is directly performed by obtaining a right to use a bus line and switching a transfer source address and a transfer destination address of data to be transferred. In a direct memory access control device that controls a data transfer process by memory access, a preset transfer source addition data and a unit addition data for updating consecutive addresses are determined based on a transfer count number of a preset continuous address portion. A transfer source address generation unit that selects according to the determined address continuity or discontinuity and adds the selected addition data to the transfer source address to update the transfer data as the transfer source address of the transfer data to be transferred next; The set transfer destination addition data and unit addition data for updating successive addresses are Is selected according to the continuity or discontinuity of the address of the transfer data determined based on the transfer count number of the set continuous address portion, and the selected transfer data is added to the transfer destination address to thereby transfer the next transfer. And a transfer destination address generator for updating the data as a transfer destination address.

According to a second aspect of the present invention, there is provided a data transfer process by direct memory access in which a right to use a bus line is obtained and data is exchanged directly by switching a transfer source address and a transfer destination address of data to be transferred. In a direct memory access control device that controls
A source address generator for adding a unit address data for updating successive addresses to a source address to update the source address of the next data to be transferred, The unit addition data for updating the address to be transferred is selected according to the continuity or discontinuity of the address of the transfer data determined based on the transfer count number of the preset continuous address portion, and the selected addition data is transferred to the transfer destination. A transfer destination address generator is provided which updates the transfer data to be transferred next as a transfer destination address by adding to the address.

According to a third aspect of the present invention, there is provided a data transfer process by direct memory access, in which a right to use a bus line is obtained and data is transferred directly by switching a transfer source address and a transfer destination address of data to be transferred. In a direct memory access control device that controls
Select and select a preset transfer source addition data and a unit addition data for updating a continuous address according to a continuation or discontinuity of an address determined based on a transfer count number of a predetermined continuous address portion. By adding the added data to the transfer source address, the transfer source address generator for updating the transfer data as the transfer source address of the transfer data to be transferred next, and the unit addition data for updating successive addresses to the transfer destination address are added. By doing so, a transfer destination address generation unit for updating as a transfer destination address of transfer data to be transferred next is provided.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a main part of a circuit according to the present embodiment. Reference numeral 11 denotes a CPU (central processing unit) constituting a control unit main body, and 12 denotes a program for the CPU 11 to control each part. A ROM (read only memory) storing data and character generator (CG) data, and a RAM (random memory) 13 provided with a memory such as an image buffer used for data processing such as image expansion processing performed by the CPU 11. Access memory) 14 is a DMA control circuit. The CPU 11, the ROM 12, the RAM 13, and the DMA control circuit 14 are electrically connected by a bus line 15 such as an address bus, a data bus, and a control bus. Also, the CPU 11 and the DM
A control circuit 14 is a bus use right request signal (HREG),
They are connected by a control line of a bus use permission signal (HACK).

As shown in FIG. 2, the DMA control circuit includes a transfer source address controller 21, a transfer destination address controller 22, a transfer number counter 23, a DMA control hold timing generation circuit 24, a line byte counter circuit 25, and an address selector 26. Be composed.
The transfer source address controller 21 sets the set transfer source address to 1 when the transfer source addresses are consecutive.
If the address is updated by the address and the source address is intermittent,
That part is updated intermittently.

The line byte counter circuit 25 counts down when the number of consecutive addresses of a transfer source or a transfer destination is set. For example, address 5
In the case where image data is continuously transferred from address 00 to address 502, if "2" is set, the count is down-counted from "2" to "0", and when it becomes "0", a TC signal is generated.

The transfer number counter 23 counts all the transferred addresses. The address selector 26 selects and outputs addresses from the source address controller 21 and the destination address controller 22 in accordance with the SEL_S / D signal from the CPU 11. The DMA control hold timing generation circuit 24 is for securing the right to use the bus of the DMA during the transfer process.

FIGS. 3 and 4 show a more detailed circuit configuration of the DMA control circuit. That is, the transfer source address controller 21 includes a transfer source register 31, a transfer source addition data register 32, an adder 33, and selectors 34 and 3
5. An OR gate 36 is provided.

The selector 34 receives a chip select signal (CS) and a write signal (W), and selects one of an address from the CPU 11 and an address from the adder 33 according to the input of the write signal (W). Then, the data is supplied to the transfer source register 31. This adder 3
3 adds the address from the transfer source register 31 by the transfer source addition data register 32 and the transfer source addition data from the selector 35 and supplies the result to the selector 34.

In the case of the transfer source addition data, if the transfer source is a continuous address, the default value "1" as the unit addition data is selectively output by the selector 35. Be updated. On the other hand, when the transfer source is a discontinuous address and the address is discontinuous (when the TC signal is output from the line byte counter circuit 25), the CPU 11 sends the transfer source addition data register 32 Since the set transfer source addition data is selectively output by the selector 35, the transfer source register 31 is updated with the address increased by the transfer source addition data.

The output of the transfer source register 31 updated each time data of one address is transferred is supplied to the adder 33 and the address selector 26.

The destination address controller 22 also has
The configuration is the same as that of the transfer source address controller 21.
That is, it is composed of a destination register 41, a destination addition data register 42, an adder 43, selectors 44 and 45, and an OR gate 46.

The selector 44 receives a chip select signal (CS) and a write signal (W), and selects one of an address from the CPU 11 and an address from the adder 43 according to the input of the write signal (W). Then, the data is supplied to the transfer destination register 41. This adder 4
3 adds the address from the destination register 41 by the amount of the destination addition data from the destination addition data register 42 and the selector 45 and supplies it to the selector 44.

In the case of the transfer destination addition data, when the transfer destination is a continuous address, the selector 45 selects and outputs the default value "1" as the unit addition data. Be updated. On the other hand, when the transfer destination is a discontinuous address and the address is discontinuous (when the select signal (RC) is output from the line byte counter circuit 25),
Since the destination addition data set in the destination addition data register 42 is selectively output from the CPU 11 by the selector 45, the destination register 41 is updated with the address increased by the amount of the destination addition data.

As described above, the output of the transfer destination register 41 updated every time data of one address is transferred is supplied to the adder 43 and the address selector 36.

The line byte counter circuit 25 has a C
A line count register 51 for setting the number of consecutive addresses from the PU 11, a line count register 5
The counter 52 supplies a select signal (RC) to the selector 35 of the source address controller 21 and the selector 45 of the destination address controller 22 when counting down and counting up based on the number of addresses set in 1. The DMA control hold timing generation circuit 24, as shown in FIG.
It comprises a control register 61, a flag set circuit 62, an AND gate 63, a sequence counter 64, a timing decoder 65, and a data latch 66.

The DMA control register 61 includes:
The bus line 15 of the CPU 11 is connected, and a start command from the CPU 11 is written when performing data transfer. When a start command is written into the DMA control register 61, a signal indicating that the start command has been written is supplied to the flag set circuit 62. Then, the flag setting circuit 62 sets an enable flag and supplies a bus use right request signal (HREQ) to the CPU 11.

The bus use right request signal (HREQ) from the flag set circuit 62 is supplied to an AND gate 63. The AND gate 63 is also supplied with a bus use right permission signal (HACK) from the CPU 11, and the AND gate 63 outputs a bus use right request signal (HRE).
When both Q) and the bus use permission signal (HACK) are input, an enable signal (EN) is supplied to the sequence counter 64.

When the enable signal (EN) is supplied from the AND gate 63, the sequence counter 64 starts a counting operation, and the read signal (R), the write signal (W), and the DACK for the RAM 13 and the like via the timing decoder 65. , SEL_S / D, etc., and supplies them to the bus line 15.

When a read signal (R) and a write signal (W) are generated for the RAM 13 and the like, the transfer source address is latched in the data latch 66. This address is also supplied to the bus line 15 as address data.

The DMA control register 6
1, when the TC signal is supplied from the transfer number counter 23, the bus use right request signal (HREQ) is released and the DM
The A transfer process ends, and the bus line is released to the CPU 11.

In the embodiment of the present invention having such a configuration, for example, the transfer source ROM 12 shown in FIG.
Is transferred to a part of the address space of the RAM 10 as shown in FIG. 10, the following DMA transfer processing is performed. In this example, as shown in FIG. 5, the CG data stored at the transfer source addresses continuous from address 0 to address 8 is
This is a case where transfer is performed to intermittent transfer destination addresses such as addresses 500 to 502, addresses 600 to 602, and addresses 700 to 702.

The DMA transfer processing in such an example is as follows.
First, a transfer source address, a transfer destination address, and the like are set in the DMA control circuit 14. This setting only needs to be performed once.

That is, the transfer source register 31 in the DMA control circuit 14 stores "0" which is the first address of the transfer source.
Is set. Subsequently, the transfer source addition data of the transfer source address is set in the transfer source addition data register 32. In this example, since the transfer source is a continuous address, "1" is set as transfer source addition data.

Similarly, the first address "500" of the transfer destination is set in the transfer destination register 41. Subsequently, the address difference of the discontinuous portion at the transfer destination is set in the transfer destination addition data register 42 as transfer destination addition data. In this example, the transfer destination is discontinuous between addresses 502 and 600, and addresses 602 and 70
Since it is discontinuous with address 0, "98" which is the difference between the addresses is set as transfer destination addition data.

Further, the number of consecutive addresses at the transfer destination address is set in the line count register 51. In this example, since the transfer destinations are continuous at addresses 500 to 502, addresses 600 to 602, and addresses 700 to 702, “2” is set in the line count register 51. As a result, "2" is set in the counter 52 as the initial value of the down count. Further, “8” which is the final address of the transfer source is set in the transfer number counter 23.

Next, by writing a start command to the DMA control register 61, the flag setting circuit 6
2, an enable flag is set, and a bus use request signal (HREQ) is output to the CPU 11. In response to this, the CPU 11 sends the bus use permission signal (HACK)
Is returned, the sequence counter 64 starts operating, and generates a read signal (R), a write signal (W), DACK, and internal signals of SEL_S / D for the RAM 13.

Then, the data of the first address "0" is read from the transfer source ROM 12, and the data latch 6
6 is temporarily stored. Then, the adder 33 updates the address to the next transfer source address. That is, in this case, the selector 3 of the transfer source address controller 21
Since “1” is selected by the select signal (RC) supplied to 5, the address of the transfer source register 31 incremented by +1 by the adder 33 is supplied to the transfer source register 31.

Next, the SEL_S / D signal is changed by the CPU 11, and the output of the address selector 26 is changed from the output of the transfer source register 31 to the output of the transfer destination register 41. The first transfer destination is the address 500 of the RAM 13, and the data stored in the data latch 66 shown in FIG. At this time, the adder 43 updates to the next transfer destination address. That is, in this case, since “1” is selected by the select signal (RC) supplied to the selector 45 of the transfer destination address controller 22,
The destination register 41 is supplied with the address incremented by one by the adder 43 to the destination register 41.

The DMA transfer processing of such continuous addresses is performed until the counter 52 of the line byte counter 25 becomes "0". As a result, 3-byte data is transferred. That is, it is read from addresses 0, 1, and 2 of the ROM 12 and
The addresses are written at addresses 501, 502, respectively.

When the counter 52 of the line byte counter circuit 25 becomes "0", the select signal (RC) is output.
Is switched, and the selector 35 of the transfer source address controller 21 selectively outputs the value set in the transfer source addition data register 32. In this example, "1" is set in the transfer source addition data register 32, and since the transfer source address is currently indicating "2", +1 is added to that address, and the transfer source register 31 has the previous value. A continuous address “3” is shown in the same manner as in FIG.

Similarly, the output of the selector 45 of the destination address controller 22 selectively outputs the value set in the destination addition data register 42.
However, in this example, the transfer destination addition data register 42
Is set to "98", and the transfer destination address currently indicates "502".
Is added, and the transfer destination register 41 indicates a discontinuous address “600”.

Since the selector signal (RC) is also a load signal (LD) for the counter 52 of the line byte counter circuit 25 at the same time, when the selector signal (RC) is switched, the line count register 51 is switched.
Will be reloaded. After loading, the selector signal (RC) returns to its original state.

In this way, the above-described processing is repeatedly performed, and the addresses “0”, “1”, “2”,
The data of “3”, “4”, “5”, “6”, “7”, “8” are stored in the RAM 13 as “500”, “501”, “50”.
2 "," 600 "," 601 "," 602 "," 70 "
0, 701, and 702.

When the transfer number counter 23 becomes "0", a TC signal indicating the end of the DMA transfer is output, and the DM signal is output.
The A control register is cleared, and the DMA transfer processing ends. As a result, the right to use the bus is released to the CPU 11.

As described above, even when the source data is a continuous address and the destination is an intermittent address,
By setting the address difference of the discontinuous portion of the intermittent address in the transfer destination register 41 as the transfer destination addition data in advance, the DMA transfer process can automatically perform the transfer destination address even at the discontinuity portion of the transfer destination address. Is automatically updated, the DMA transfer process is stopped in this part,
It is not necessary to set the transfer destination address again and restart the DMA transfer processing. As a result, the speed of the entire data transfer process can be further increased, and the processing capability by the DMA can be sufficiently exhibited.

In this embodiment, the case where the source data is a continuous address and the destination is an intermittent address as shown in FIG. 5 has been described as an example.
The present invention is not necessarily limited to this. For example, as shown in FIG. 6, when window-shaped data "A" is taken out between buffers of the RAM 13 and copied in another memory address window-shape as shown in FIG. As described above, both the transfer source and the transfer destination are intermittent addresses, but the present invention can be applied to such a case.

In this case, the transfer source addition data register 32 of the transfer source address controller 21 stores 10 bits from address 2, which is a discontinuous portion of the address, as transfer source addition data.
“98” which is the difference between address 0 is set, and “98” which is the difference between address 502 and address 600, which is a discontinuous portion of the address, is added to the destination addition data register 42 of the destination address controller 22 as destination addition data. Is set, the address is automatically updated even in the discontinuous portion of the transfer destination and transfer source addresses. With this, the same effect as described above can be obtained.

Further, as shown in FIG. 8, the present invention can be applied to a case where the data at the transfer source is an intermittent address and the data at the transfer destination is a continuous address. In this case, “98”, which is the difference between address 2 and address 100, which is a discontinuous portion of the address, is set in the transfer source addition data register 32 of the transfer source address controller 21 as the transfer source addition data.
If "1" is set as the transfer destination addition data in the transfer destination addition data register 42 of the transfer destination address controller 22, the address is automatically updated at the discontinuous portion of the transfer source address. With this, the same effect as described above can be obtained.

[0055]

As described in detail above, according to the present invention, there is provided a direct memory access control device capable of speeding up data transfer processing by sufficiently exhibiting transfer processing capability by direct memory access. You can do it.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a circuit configuration according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a DMA control circuit shown in FIG.

FIG. 3 is a block diagram showing a part of the detailed circuit configuration of the DMA control circuit shown in FIG. 2;

FIG. 4 is a block diagram partially showing a detailed circuit configuration of a DMA control circuit shown in FIG. 2;

FIG. 5 is a diagram showing an example of transfer data when a transfer source is a continuous address and a transfer destination is an intermittent address in the present embodiment.

FIG. 6 is a diagram illustrating a case where transfer data is moved from a part of an address space to another part in the present embodiment.

FIG. 7 is a diagram showing an example of transfer data in the case shown in FIG. 6;

FIG. 8 is a diagram showing an example of transfer data when a transfer source is an intermittent address and a transfer destination is a continuous address in the present embodiment.

FIG. 9 is a diagram showing an example of transfer data serving as a continuous address.

10 is a diagram showing an example of transfer data when the transfer destination shown in FIG. 9 is an intermittent address.

11 is a view for explaining a case where the transfer data shown in FIG. 9 is transferred to the address space shown in FIG. 10 in the conventional direct memory access control device.

12 is a flowchart showing control performed by the CPU when transferring the transfer data shown in FIG. 9 to the address space shown in FIG. 10 in the conventional direct memory access control device.

[Explanation of symbols]

14 DMA control circuit 21 Transfer source address controller (transfer source address generation unit) 22 Transfer destination address controller (transfer destination address generation unit) 24 DMA control hold timing generation circuit 25 Line byte counter circuit 26 Address selector 31 ... Transfer source register 32 ... Transfer source addition data register 33 ... Adder 35 ... Selector 41 ... Transfer destination register 42 ... Transfer destination addition data register 43 ... Adder 45 ... Selector

Claims (3)

[Claims] 1. A direct memory access for controlling a data transfer process by a direct memory access for directly exchanging data by obtaining a right to use a bus line and switching a transfer source address and a transfer destination address of data to be transferred. In the control device, the preset transfer source addition data and the unit addition data for updating the continuous address are determined according to the continuity or discontinuity of the address determined based on the transfer count number of the preset continuous address portion. A transfer source address generator for selecting and adding the selected addition data to the transfer source address, thereby updating the transfer data as the transfer source address of the transfer data to be transferred next;
Unit transfer data for updating preset transfer destination addition data and continuous addresses is selected according to the continuity or discontinuity of addresses of transfer data determined based on the transfer count number of the predetermined continuous address portion. And a transfer destination address generator for adding the selected addition data to the transfer destination address to update the transfer data as the transfer destination address of the transfer data to be transferred next. 2. A direct memory access for controlling a data transfer process by a direct memory access for directly exchanging data by obtaining a right to use a bus line and switching a transfer source address and a transfer destination address of data to be transferred. In the control device, a transfer source address generating unit that updates the transfer source address of transfer data to be transferred next by adding unit addition data for updating consecutive addresses to the transfer source address; The addition data and the unit addition data for updating the continuous addresses are selected according to the continuity or discontinuity of the addresses of the transfer data determined based on the transfer count number of the preset continuous address portion, and the selected addition is performed. By adding data to the transfer destination address, the next transfer data to be transferred And a transfer destination address generator for updating the transfer destination address as a transfer destination address. 3. A direct memory access for obtaining a right to use a bus line and controlling a data transfer process by a direct memory access for directly exchanging data by switching a transfer source address and a transfer destination address of data to be transferred. In the control device, the preset transfer source addition data and the unit addition data for updating the continuous address are determined according to the continuity or discontinuity of the address determined based on the transfer count number of the preset continuous address portion. A transfer source address generator for selecting and adding the selected addition data to the transfer source address, thereby updating the transfer data as the transfer source address of the transfer data to be transferred next;
A transfer destination address generator for adding a unit addition data for updating successive addresses to a transfer destination address to thereby update the transfer data as a transfer destination address of transfer data to be transferred next. Access control device.