JPH10111839A - Storage circuit module - Google Patents

Abstract

(57) Abstract: An object of the present invention is to provide a storage circuit module capable of performing ECC error correction detection using a memory such as an existing SIMM. A data storage unit for storing data, an ECC storage unit for storing an error correction code for data stored in the data storage unit, a correction code generation unit for generating an error correction code for the data, A correction / detection unit that performs error correction / detection using an error correction code stored in a storage unit, wherein the ECC storage unit is configured by a storage element having no error correction function. .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage circuit module, and more particularly to a SIMM (Single I / O) used for a personal computer, an image processing apparatus, a printer, and the like.
nline Memory Module) or DIMM (Dual Inline Memor)
The present invention provides a storage circuit module having a novel configuration to which an error correction circuit is added in order to improve the reliability of the storage circuit module such as y Module).

[0002]

2. Description of the Related Art In recent years, with the widespread use of computer systems, inexpensive storage circuit modules have been used in large quantities for computer main storage and image memories. In particular, in personal computers, SIMM or DIM
M is supplied as a memory module board called M. As these memory module boards become inexpensive, the mounted memory capacity is increasing. In fields such as workstations and servers that require a high degree of reliability for memory read and write, ECC (Error Checking and Correction) has already been used.
code) error correction system is employed to perform advanced error detection and correction.

On the other hand, SIMMs provided at low cost in personal computers and the like use either a type that does not perform error detection (type without parity) or a type that performs error detection using parity (type with parity). I have. In the non-parity type SIMM, when reading and writing data, even if a bit error occurs, it is not detected, and reading or writing is performed erroneously. On the other hand, with the parity type, bit error detection can be easily performed.

Further, in a computer system such as a printer server on a network that performs a large amount of data communication, an expensive SIMM board adopting an ECC error correction method is used. A 16-Mbit DRAM or a 4-Mbit high-speed SRAM having a Fit number (soft error failure rate) of about 1000 is used as a storage element of a SIMM board of a SIMM or an ECC error correction system.

FIG. 4 is a block diagram showing a conventional configuration using SIMM. The CPU 100 is connected to the ROM memory 200 and the data memory 50 through a data bus and an address bus. The CPU 100
The program stored in the ROM memory 200 is read, and processing corresponding to the program is performed. At this time, when a data write operation occurs in the data memory 50, the CPU 100 specifies an address and specifies the address. The data is directly written to 50. Also, when reading data from the data memory 50, the CPU 100 directly reads data by designating an address.

Here, when a SIMM without parity is used for the data memory 50, as shown in FIG. 5, at the time of read and write operations, data is simply read and written directly to the SIMM 92. . That is, since no error check is performed, even if a bit error occurs, the CPU reads or writes the data with the error as it is.

[0007] Considering the case where a SIMM with parity is used for the data memory 50, a configuration as shown in FIG. 6 is usually employed. In this case as well, the basic operation is the same as described above, but the parity data is read or written simultaneously with the read or written data. In FIG. 6, SIM with parity
M92 is divided into a normal data storage area (32 bits) and a parity area (4 bits). CPU
Is written directly to the SIMM 92, and at the same time, is input to the parity generation circuit 91, where 4-bit parity data is generated, and
The data is stored at a position corresponding to the written data in the parity area of the MM 92.

Conversely, when the CPU 100 reads data from the SIMM 92, the parity data corresponding to the data is read to the error detection circuit 93. The error detection circuit 93 collates the data itself read from the SIMM 92 with the parity data to check whether an error has been detected, and outputs a 1-bit error detection presence / absence signal. The CPU 100 can detect whether or not an error has occurred by checking the presence / absence signal of the error detection.

FIG. 7 shows a memory configuration diagram when a conventional SIMM capable of performing ECC error correction is used. The SIMM 92 has a data memory area (32 bits)
And an ECC code memory area (8 bits). When data is written by the CPU, the data is input to the ECC code generation circuit 95 at the same time as the data is written to the data memory area, where the ECC code is generated and the SIMM 92
Is stored in the ECC code memory area.

Conversely, when the CPU reads data from the SIMM 92, an ECC code corresponding to the data is read by the data correction error detection circuit 94. The data correction error detection circuit 94 checks whether or not an error is detected by comparing the read data itself with the parity data. The output normal data is output to the CPU, and if "error exists" and cannot be corrected, the fact that an error has occurred is output to the CPU.
The SIMM capable of ECC error correction is formed integrally with the data correction error detection circuit 94 and the ECC code generation circuit 95 and supplied as one LSI. Also,
The SIMM 92 has a data bus and an address bus as input / output terminals, and has a structure that can be detached by a mounting operation so that it can be easily added or replaced.

[0011]

Conventionally, in a personal computer, the memory capacity of a SIMM to be mounted is at most about 8 Mbytes or 16 Mbytes.
Even if a SIMM without parity or with parity was used, there was no particular problem in reliability.

However, due to the recent decrease in the price of SIMMs, a memory of 32 Mbytes or 64 Mbytes or more is often mounted. Due to the reduction in the price of the memory in the future, there is a possibility that a larger capacity memory will be mounted. Is high. Therefore, the larger the capacity of the memory to be mounted, the higher the probability of occurrence of a bit error. Therefore, if the currently used SIMM without parity or with parity is used, reading and writing of the memory can be performed. It is expected that reliability will be an issue more often.

On the other hand, "ECC" which can secure sufficient reliability
The error-correction SIMM is currently expensive and difficult to obtain. Furthermore, "SIM of the ECC error correction system"
M ”and“ SIM without parity or with parity ”
There is no pin compatibility with "M".

[0014] Therefore, a user who has mounted an inexpensive “SIMM with parity” at present can use the “SIMM with parity” to improve the reliability when adding memory.
"MM" cannot be exchanged for "SIMC of the ECC error correction system". That is, in order to increase the memory while ensuring sufficient reliability, it was necessary to purchase a device using a highly reliable “ECC error correction system SIMM” from the beginning.

The personal computer can be used in various ways from a user who uses only one application and does not need a large-capacity memory to a user who requires a large-capacity memory for image creation and processing. Therefore, it is necessary to be able to select a mountable memory capacity according to a user's request.
Therefore, for users who only need a small amount of memory, a computer that can use the current inexpensive “SIMM without parity” even though the reliability is somewhat low is desired, and users who are planning to add more memory in the future. In some cases, a computer with a memory configuration that allows use of an inexpensive SIMM at the beginning and that can be replaced with a highly reliable memory that is compatible with an inexpensive SIMM or that can be expanded in the future is desired. It is.

Accordingly, the present invention has been made in view of the above circumstances, and it is possible to perform ECC error correction while using a conventional SIMM without parity or with parity. It is an object to provide a storage circuit module that is compatible with a SIMM without parity or with parity.

[0017]

According to the present invention, there is provided a data storage unit for storing data, an ECC storage unit for storing an error correction code of data stored in the data storage unit, and a method of generating an error correction code for the data. A correction code generator for performing
A correction / detection unit that performs error correction / detection using an error correction code stored in a CC storage unit, wherein the ECC storage unit is configured by a storage element having no error correction function. A storage circuit module is provided. Further, the data storage unit and the ECC storage unit may be a SIMM memory with parity or a SIMM memory without parity. Furthermore, a switching unit that activates / deactivates the operation of the correction code generation unit and the correction / detection unit may be further provided, and the availability or non-use of the error correction code may be arbitrarily selected. Here, it is preferable that the SIMM memory is constituted by any one of a flash memory, a DRAM and an SRAM.

Generally, for 32-bit data,
An 8-bit ECC data error correction code is generated. As a SIMM used for the data storage unit,
In the case of using one 4 Mbyte, 32-bit bus, one SIMM having the same capacity may be used for the ECC storage unit. At this time, in order to store the ECC error correction code, the SIMM of the ECC storage unit uses a quarter capacity.

When an 8-Mbyte data storage unit is configured by using two 4-Mbyte SIMMs, one-half of a 4-Mbyte SIMM is used as an ECC storage unit, and a 12-Mbyte data storage unit is used. In the case of a 16 Mbyte configuration, the ECC storage unit uses 3/4, 4/4 of a 4 Mbyte SIMM.

Incidentally, the failure rate (the number of fits) is usually used as a measure of the reliability of the storage element. The number of fits indicates a failure rate. For example, 16
In the case of the M-bit DRAM, the 4-Mbit DRAM, and the 4-Mbit high-speed SRAM, the number of fits is about 1000, and the number of fits of the 1-Mbit high-speed SRAM is 25.
It is about. Here, the failure rate refers to the failure rate at time t / the number remaining until time t. The case where the failure rate becomes 10 ^-9 is called 1 fit.

Using 64 4 Mbit DRAMs, 32
Assuming that an M-byte storage circuit module is configured and 1000 storage circuit modules are operated for 250 hours per month, an error occurs approximately every 15.75 hours if error detection by ECC or parity is not performed. Occurs,
When ECC error correction is performed, 1 in 15873 hours
Errors will occur. That is, when error correction by ECC is performed, it can be said that the reliability can be improved about 1000 times.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on an embodiment shown in the drawings. Note that the present invention is not limited to this. FIG. 1 is a block diagram showing a configuration of an embodiment of a storage circuit module according to the present invention. Here, the conventional configuration block diagram shown in FIG.
The difference is that a CC circuit 300 and an ECC code memory 60 are added. The data memory 50 and the ECC code memory 60 are both commercially available S
IMM shall be used. Here, using either “SIMM without parity” or “SIMM with parity”, a slot dedicated to the SIMM is provided on the board, and is attached to and detached from the slot.

The data memory 50 and the ECC code memory 60 can be configured to be easily added, changed, and deleted in the same manner as the conventional SIMM can be easily mounted. That is, in order to mount a large-capacity memory, the SIM
A plurality of M slots may be provided in advance. further,
The ECC code memory 60 is not directly attached to the substrate, but is provided with a dedicated slot so that it can be removed.

As described above, by adopting a configuration in which the ECC code memory 60 can be attached and detached, a small-capacity memory configuration is used, especially when ECC error correction is not required.
Although the SIMM as the C-code memory 60 is not mounted, if the large-capacity memory configuration requires ECC error correction, the SIM as the ECC-code memory 60 is required.
M can be implemented.

Next, referring to FIG. 1, an outline of data read and write operations in this embodiment will be described. First, when an operation of writing certain data A to the data memory 50 occurs, the CPU 100 specifies the address of the data memory 50 and performs the data A writing operation. At this time, since the data bus is connected to the ECC circuit 300, the data A is transmitted to the ECC circuit 300.
Is written.

When the data A is written, the ECC circuit 300 stores the data A in the data memory 50, generates an ECC code therein, and
The code is stored in the ECC code memory 60. At this time, the address of the data memory 50 where the data A is written and the ECC where the ECC code of the data A is written
The addresses of the code memory 60 are associated with each other on a one-to-one basis, and generally have the same address.

When reading certain data B from the data memory 50, the CPU 100
The read operation of the data B is performed by designating the address of. At this time, data B is transferred from data memory 50 to EC.
The ECC code corresponding to the data B is read from the ECC code memory 60 while being read by the C circuit 300.

The ECC circuit 300 generates an ECC code for the read data B, and generates the generated ECC code.
The CC code is compared with the read ECC code.
When they match, the data B is sent to the CPU 100 as it is. When an error is detected, the error detection information is sent to the CPU 100. In addition, according to the ECC error correction, a one-bit error can be corrected using an ECC code. Therefore, correct data B corrected inside the ECC circuit is generated and sent to the CPU 100. The above is the outline of the memory read and write operations in one embodiment of the present invention. Next, an embodiment of the configuration of the ECC circuit 300 will be described.

FIG. 2 is a block diagram showing the configuration of the ECC circuit 300 according to one embodiment of the present invention. In the figure, except for the data memory 50 and the ECC code memory 60, E
It corresponds to the CC circuit 300. The bus switching unit 41 includes a CPU
100 is connected by a data bus and a write signal line and a read signal line, and performs an operation of switching a data bus leading to the memory in a write direction (right direction in FIG. 2) or in a read direction (left direction in FIG. 2). Yes, TTL or CM
It is composed of a logic element such as an OS. Here, the direction of the data bus is switched by a write signal and a read signal.

The switching byte control unit 42 permits the use of each bit line of the data bus ("C" in FIG. 2) leading to the data memory 50 in accordance with the number of bytes of data stored in the data memory 50.・ It controls the impossibility, TT
It is constituted by a logic element such as L or CMOS. Here, the switching of the number of bits uses four byte enable signals 0 to 3 sent from the CPU 100.

In this embodiment, the data memory 5
SIMM is used for the 0 and ECC code memory 60, and both have a 32-bit configuration and can store data of a maximum of 32 bits.
When data is actually stored, byte enable signals 0 to 3 are used in order to divide the memory space into four blocks of 8 bits.

FIG. 3 shows byte enable signals 0-3,
The relationship between the number of effective bits of data written to a SIMM memory is shown. That is, when writing 32-bit data, to enable all bits, all byte enable signals 0 to 3 are set to the ON state (“H” level), and only the lower 8 bits of 0 to 7 bits are set to 8 bits. When writing data, only the byte enable 0 signal
N state (“H” level). In other cases, data of a predetermined bit length can be written to a predetermined block by appropriately turning on or off the byte enable signals 0 to 3.

The parity generating section 80 is a circuit for generating the parity of the data output to the signal line "c" in FIG. 2, but it may be a conventionally used circuit. The ECC code generation unit 20 is a circuit that generates an ECC code of the data output to the “C” part in FIG. 2, and a circuit that has been conventionally used may be used.

The parity ECC switching unit 70 corresponds to a switching unit, and uses a parity as an error check code stored in the ECC code memory 60 or an ECC code.
This is a circuit for switching whether to use the C code or not, and this switching is performed by a switching signal sent from the CPU 100.
For example, when a 1-bit switching signal is used, the following settings may be made. When it is "1", the signal lines "H" and "R" are connected, and the ECC code is written into the ECC code memory 60. When it is "0", the signal lines "g" and "g" are connected, and the ECC code is written into the ECC code memory 60.

When the error is not detected by the ECC code or the parity, the parity ECC switching unit 70 connects the “R” part of the signal line to both the “G” part and the “H” part of the signal line. What should be done is not. This is because, for example, 2-bit data is used as a switching signal, and when "00", the signal line "R" is not connected,
If the signal line is “01”, the signal lines “R” and “G” are connected, and if it is “10”, the signal lines “R” and “H” are connected. realizable.

When the parity or the ECC code is not stored, the slot of the ECC code memory 60 is
The IMM may not be mounted. The parity check unit 90 detects a parity error, and may use the same one as the error detection circuit 93 shown in FIG. The error correction detection section 30 detects an error using an ECC code, and may use the same one as the data correction error detection circuit 94 shown in FIG. When the data read from the data memory 50 is input, both the parity check unit 90 and the error correction detection unit 30 generate a parity or an ECC code of the data and read out the parity and the ECC code from the ECC code memory 60, respectively. Outputs the presence / absence of an error in comparison with the data.

Hereinafter, an embodiment in which an ECC code is generated and an error check is performed will be described. First, a case where 32-bit data is written to the data memory 50 will be described. In this case, the signal line "c" portion 3
Since all two bits are used, the CPU 100 turns on all the byte enable signals 0 to 3. To generate the ECC code, the CPU 100 sets the switching signal to the ON state, that is, sets the parity signal to “1”.
This is given to the C switching unit 70. At this time, as described above, the signal lines “H” and “H” are connected, and the ECC code generator 2
0 is the ECC code memory 6
Written to 0.

It is assumed that the CPU 100 performs an operation of writing certain data A into the data memory. The CPU outputs data A on the data bus and an address to be written on the address bus, and outputs a write signal at a predetermined timing. Upon receiving this write signal, the bus switching unit 41 switches the bus direction to the write direction, that is, the right direction in FIG.
In addition, in response to the byte enable signals 0 to 3, the switching byte control unit 40 selects the number of valid bits and switches the data bus to the right in FIG.

Bus switching unit 41 and switching byte control unit 40
In such a state, the data A given from the CPU 100 is written to the data memory 50 through the signal line "c". The data A is input to the parity generator 80 and the ECC code generator 20 through the signal line “C”, and the parity and the ECC for the data A are respectively input.
Code is generated. The parity ECC switching unit 70
Although the signal line “H” and the “R” are connected, the signal line “G” is not connected anywhere, so that the parity generated by the parity generator 80 is not stored. on the other hand,
The ECC code generated by the ECC code generator 20 is
The data is stored at the address of the ECC code memory 60 specified by the address bus via the signal line “R” via the parity ECC switching unit 70. EC stored here
The C code is 7 bits.

Next, a case where an ECC code is generated and data other than 32-bit length data, for example, 8-bit data B is written in the data memory 50 will be described.
At this time, “1” is output as the switching signal, and the signal line “H” and “R” are connected. When the data to be written is 8 bits from the 0th bit to the 7th bit, only the byte enable 0 signal is turned on.
That is, the CPU 100 outputs the byte enable 0 signal as an ON state and the byte enable 1 to 3 signals as an OFF state.

When this byte enable signal is supplied to the bus switching unit 41 and the switching byte control unit 40, only eight signal lines of 0 to 7 bits are valid in the signal lines "a" and "b". . Then, the 8-bit data B given from the CPU 100 is output to the 0th to 7th bits of the “c” portion through the signal lines “a” and “b”.

First, the data memory 50 is connected to the address bus.
When the CPU 100 performs a byte write in a state in which the address is output, the 32-bit data stored at that address in the data memory 50 is read and output to the signal line “d”. Similarly, when the CPU performs a byte write, the 7-bit ECC stored in the same address of the ECC code memory 60 is stored.
The code is read and output to the signal line “e”.

Next, the 32-bit data output to the signal line “D” and the ECC code output to the signal line “E” are supplied to the error correction detector 30. In the error correction detection unit 30, the 32-bit data and the signal line "e"
The presence / absence of an error is determined from the ECC code given by the section. After determining whether there is an error, the error correction detection unit 30
Indicates "1 bit error" or "2
CPU error through a signal line
Notify to When the error is 1 bit, the error correction detection unit 30 corrects the bit and corrects the corrected 3 bit.
The 2-bit data is output to the signal line “F”. If there is no error, the data input to the error correction detection unit 30 is output to the signal line “F” as it is.

Thereafter, 32 output to the signal line "F"
The bit data is supplied to the switching byte control unit 42, and the 32-bit data of the signal line “F” is used for the 31st to 8th bits of the signal line “C”. Also, the 0th to 7th bits of the signal line “C” portion are the signal line “B”.
The data passed through the department is used.

As described above, the switching byte control unit 40
It is preferable to provide a selector circuit for synthesizing the data input from the “b” section and the “f” section. This selector circuit can be configured using a logic element such as TTL or CMOS. Also, synthesized as described above,
The 32-bit data output to the signal line “C” is written into the data memory 50. Also, the 32-bit data of the "C" portion is stored in the ECC code generator 20.
To generate an ECC code, which is written to a predetermined address of the ECC code memory 60.

Next, an embodiment for reading data written in the data memory 50 will be described. here,
Regarding reading of data, the same processing is performed regardless of whether the data length is 32 bits or 8 bits. CP
U100 outputs an address to be read from data memory 50 onto an address bus, and further outputs a read signal at a predetermined timing. The read signal is sent to the bus switching unit 4
When input to 1, the bus switching unit 41 switches the bus direction to the read direction, that is, the left direction in FIG. In the case of reading, the byte enable signals 0 to 3 are ignored, and the signal lines “a”, “b”, and “c” always have 3 signals.
2-bit data is input / output.

The reading process from the data memory 50 will be described below. First, when an address is applied to the data memory 50 through the address bus and a read signal is applied, the 32-bit data stored at the address is output to the signal line “d”. Similarly, at this time, when the same address is given to the ECC code memory 60 and a read signal is given, the 7-bit ECC code stored at that address is transferred from the ECC code memory 60 to the signal line “e”. Section. Thereafter, the 32-bit data output to the signal line “d” is
The 7-bit ECC code output to the signal line "e" is supplied to the error correction detection unit 30, where error detection or correction is performed.

The error correction detector 30 receives the input 32
ECC code of bit data is generated, and E
If an error is detected in comparison with the CC code,
"One bit error" or "two or more bits error" is notified to the CPU through a signal line. Error correction detector 30
In the case of "1 bit error", since the correction is possible, the 32-bit data after correcting the 1 bit is output to the signal line "f". The 32-bit data output to the signal line “F” is sent to the left in FIG. 2 through the bus switching unit 41 and is transferred to the CPU 100 via the signal line “A”. When data is read, the CPU 1
The data transferred to 00 is 32 bits, but if the required data is 8 bits, the CPU 100
What is necessary is just to take in only the necessary 8 bits.

As described above, the data memory 50 and the EC
By providing the C code memory 60 and storing the ECC code separately from the data storage, the error check by the ECC can be performed even when the existing SIMM without parity is used for these memories. The reliability of the data storage circuit can be improved. Also, without using the expensive ECC error correction SIMM,
Since an existing SIMM can be used, cost increase can be minimized, and further, it can be used as a storage circuit module compatible with a conventional SIMM.

Next, a description will be given of an embodiment in which error detection by parity is performed in the configuration block shown in FIG. In this case, the configuration is the same as the error correction detection by the ECC described above, but it can be realized by changing the functioning part by setting the switching signal to the OFF state, that is, to “0”.

In the above-described error correction detection by ECC,
The parity ECC switching unit 70 connects the signal line “H” and the “R” unit so that the ECC code is stored in the ECC code memory 60. This time, the signal line “H” is Then, the signal lines “g” and “g” are connected, and the parity generated by the parity generator 80 is stored in the ECC code memory 60. That is, when data is read from or written to the data memory 50 from the CPU, the storage circuit module of the present invention can be operated by simply switching the switching signal to the ON or OFF state.
It is possible to easily determine whether to perform error correction detection by CC or error detection by parity. This is also one of the features of the present invention.

The process of writing or reading data by detecting an error using parity will be described below. In the following processing, the CPU 100 always outputs the OFF state (“0”) as the switching signal. As a result, the signal line “g” and “g” are connected inside the parity ECC switching unit 70, and the parity generated by the parity generation unit 80 through this path is stored in the ECC code memory 60. Is done.

First, a process for writing 32-bit data A to the data memory 50 will be described. As in the case of the ECC error correction, the CPU 100 outputs an address to be written on the address bus, and outputs a write signal at a predetermined timing. At this time, in response to the write signal, the bus switching unit 41 switches the bus direction to the write direction, that is, the right direction in FIG. When all the byte enable signals 0 to 3 are turned on, all the bits become valid bits, and the switching byte control unit 40 switches the data bus to the right in FIG.

In this state, the 32-bit data A is written to the designated address of the data memory 50 through the signal lines "a", "b" and "c". Further, the 32-bit data A is input to the parity generation unit 80 through the signal line “C”, and the parity is generated. At this time, the parity is usually generated separately for each byte, that is, for every 8 bits, but is not limited to this. Here, the 32-bit data is transmitted through the signal line “C” to the EC.
Although the signal is input to the C code generator 20, the signal line “H” is not connected to the “R”, so even if an ECC code is generated, it is not stored in the ECC code memory 60.

Since the signal line “g” and “ri” are connected by the parity ECC switching unit 70, the generated parity passes through the signal line “g” and the “ri”, and is used for the ECC code. The data is sent to the memory and stored at the specified address output on the address bus. The above is the processing of writing the 32-bit data A to the data memory 50 and, at the same time, writing the parity of the data A to the ECC code memory 60. In the case of 8-bit data, the bits that are enabled by the byte enable signal Data writing can be performed by almost the same process except for the number. For example, if only the bit enable 0 signal is turned on and the others are turned off, 0 to 7 bits of the signal line "c" become effective bits, and 8-bit data is written to the corresponding data memory 50 position. Then, the parity of the 8-bit data is written into the position of the ECC code memory 60 corresponding to 0 to 7 bits.

Next, a process for reading data from the data memory 50 will be described. The CPU 100 outputs an address of data to be read from the data memory 50 onto an address bus, and further outputs a read signal at a predetermined timing. At this time, the bus switching unit 41 switches the bus in the left direction in FIG. When a read signal is input to the data memory 50, the 32-bit data stored at the address output on the address bus is read to the signal line "d". Similarly, the parity stored at the same address in the ECC code memory 60 is read out to the signal line “e”.

When the 32-bit data read to the signal line “d” and the parity read to the signal line “e” are input to the parity check unit 90, the parity check unit 90 The parity of the 32-bit data is calculated and compared with the input parity. If the result of this comparison is not correct, a "parity error" is notified to the CPU 100 via a signal line. If it is correct, 32 read from the parity check unit 90 to the signal line “F”
The bit data is output as it is, and the bus switching unit 4
1, the 32-bit data is output to the signal line "i", that is, the data bus of the CPU 100. In addition, EC
Similar to the read operation for C error correction detection, the read processing is the same whether the data to be read is 36 bits, 8 bits, or any other number of bits.

If the CPU 100 reads the 32-bit data and then takes in the required number of bits out of the 32-bit data on the CPU 100 side, it is not necessary to discriminate the processing according to the number of bits read in the storage circuit module. Absent. As described above, the data memory 50 and E
By separately providing the CC code memory 60 and storing the parity in the ECC code memory 60,
It can also be configured as a storage circuit module having a parity check function using an existing SIMM.

[0059]

According to the present invention, it is possible to perform error correction detection by ECC using an existing parity-less or parity-attached SIMM without using an expensive ECC error correction system SIMM. It is possible to provide a highly reliable storage circuit module which is kept low. In addition, by providing a switching unit that activates / deactivates the operations of the correction code generation unit and the correction detection unit, a configuration that can easily cope with both cases where high reliability is required and cases where high reliability is not required is provided. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration according to an embodiment of the present invention.

FIG. 2 is a detailed configuration block diagram of an ECC circuit according to one embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a relationship between a byte enable signal used in the present invention and the number of effective bits of data.

FIG. 4 is a configuration block diagram of a conventional storage circuit module using a SIMM.

FIG. 5 is a configuration block diagram using a conventional SIMM without parity.

FIG. 6 is a configuration block diagram using a SIMM with parity in the related art.

FIG. 7 shows a conventional SIM that performs ECC error correction.
It is a block diagram using M.

[Explanation of symbols]

 Reference Signs List 20 ECC code generation unit 30 Error correction detection unit 41 Bus switching unit 42 Switching byte control unit 50 Data memory 60 ECC code memory 70 Parity ECC switching unit 80 Parity generation unit 90 Parity check unit 100 CPU 200 ROM 300 ECC circuit

Claims (4)

[Claims] A data storage unit that stores data; an ECC storage unit that stores an error correction code of data stored in the data storage unit; a correction code generation unit that generates an error correction code of the data; A correction / detection unit that performs error correction / detection using an error correction code stored in an ECC storage unit, wherein the ECC storage unit is configured by a storage element having no error correction function. Storage circuit module. 2. The storage circuit module according to claim 1, wherein the data storage unit and the ECC storage unit are a SIMM memory with parity or a SIMM memory without parity. 3. The apparatus according to claim 1, further comprising a switching unit that activates / deactivates the operation of the correction code generation unit and the correction / detection unit, and enables or disables use of the error correction code. 3. The storage circuit module according to 2. 4. The storage circuit module according to claim 2, wherein said SIMM memory is constituted by one of a flash memory, a DRAM, and an SRAM.