JPH10107277A - Semiconductor device - Google Patents

Abstract

(57) [PROBLEMS] To provide a semiconductor device capable of preventing a reduction in withstand voltage between a drain and a source even when a high potential wiring is connected to a drain region from the outside of an element isolation region across an element isolation region. provide. SOLUTION: N in a substantially central portion of an element forming region 4 is provided.
An n + -type drain region 5 is formed on the surface of the n-type epitaxial layer 2, surrounds the n + -type drain region 5, and is in contact with the p + -type element isolation region 3. The + source region 7 is formed on the surface of the element forming region 4 so as to be formed and included in the p type well region 6. Then, the p-type well region 6 and n
A plurality of n + -type impurity regions 12 are provided concentrically at a constant interval on the surface of the element forming region 4 in the drift region between the n + -type drain region 5 and the n + -type drain region 5. A plurality of resistance elements 13 are connected between the n + drain region 5 and the n + source region 7, and the resistance elements 13 are connected to the n + -type impurity regions 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly, to an LDMOSFET.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional LDMOSFET.
(A) is a schematic plan view showing a state viewed from above, and (b) is a schematic sectional view taken along line EE 'in (a). Conventional horizontal double diffusion M with high withstand voltage
OS field effect transistor, so-called LDMOSFET
In the (Lateral Double Diffused MOSFET), an N-type epitaxial layer 2 is formed on a P-type semiconductor substrate 1, and a p + -type element isolation region 3 reaching the P-type semiconductor substrate 1 from the surface is formed in the N-type epitaxial layer 2. Thus, an element forming region 4 which is insulated and separated from other portions by the p + type element isolation region 3 is formed.

An n + -type drain region 5 is provided on the surface of the N-type epitaxial layer 2 at a substantially central portion of the element forming region 4.
Is formed, surrounding the n + type drain region 5, and
A p-type well region 6 is formed on the surface of element formation region 4 in contact with p + -type element isolation region 3, and an n + type source region 7 is formed on the surface of element formation region 4 so as to be included in p-type well region 6. Have been.

[0004] An insulating film 8 is formed on the N-type epitaxial layer 2, and a source electrode 9 is formed so as to be electrically connected to the n + -type source region 7 and the p + -type element isolation region 3. On p-type well region 6 between region 7 and n + -type drain region 5, gate electrode 10 is formed via insulating film 8, and drain electrode 11 is formed to be electrically connected to drain region 5. And the drain electrode 1
Numeral 1 extends outside the element formation region 4 from a direction in which the p-type well region 6 and the n + -type source region 6 are not formed.

In the above-mentioned LDMOSFET, a high potential is applied to the drain electrode 11 and a low potential is applied to the source electrode 9 to deplete the entire N-type epitaxial layer 2 and relax the surface electric field to thereby withstand the drain-source breakdown voltage. Is maintained at a high voltage. This is the so-called RESURF (Reduced
Surface Field) principle (JAApplelsand
HMJVaes, "HIGH VOLTAGE THIN LAYER DEVICE
S (RESURF DEVICES), IEEE, pp. 238-241 (1979)).

[0006] Such an LDMOSFET can be applied to a level shifter or the like of a high-side driver circuit by being integrated with another signal processing circuit on the same chip. When this LDMOSFET is integrated as an IC, a shape in which an n + type drain region 5 is arranged at the center and the periphery is surrounded by an n + type source region 7 is often used as shown in FIG. , N + type drain region 5
When a wiring for applying a high voltage is connected, it is necessary to connect a wiring to the inside n + type drain region 5 across the p + type element isolation region 3 from outside the element formation region 4.

[0007]

However, in the LDMOSFET having the above-described structure, the potential of the high potential wiring affects the potential distribution of the N-type epitaxial layer 2 thereunder via the insulating film 8 immediately below. There was a problem.

When a high potential is applied to the drain electrode 11, an electric field is concentrated near the p + -type element isolation region 3 by the drain electrode 11 as shown in FIG. In particular, in this case, since the voltage of the gate electrode 10 is low, the surface electric field of the N-type epitaxial layer 2 is concentrated on the edge of the gate electrode 10 on the side of the n + -type drain region 5, and exceeds the critical electric field, so that the drain-source There is a problem that the withstand voltage between the electrodes greatly decreases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object the purpose of connecting a high potential wiring to the drain region from outside the element isolation region across the element isolation region. Another object of the present invention is to provide a semiconductor device capable of preventing a decrease in withstand voltage between a drain and a source.

[0010]

According to the first aspect of the present invention,
A first conductivity type semiconductor substrate, a second conductivity type epitaxial layer formed on the semiconductor substrate, and a high concentration first conductivity type element isolation region formed so as to reach the semiconductor substrate from a surface of the epitaxial layer. And an element formation region insulated and isolated by the element isolation region; a high-concentration second conductivity type drain region formed on the surface of the element formation region; and the element electrically connected to the drain region; A drain electrode extending outside the formation region, and a first conductive layer formed on a surface of the element formation region so as to surround the drain region except for a portion near a lower portion of the drain electrode and to be in contact with the element isolation region. A well region, a high-concentration second-conductivity-type source region formed on the surface of the element formation region so as to be included in the well region, and an insulator formed on the epitaxial layer. A film, a gate electrode formed on the well region between the source region and the drain region via the insulating film, and a source electrode electrically connected to the source region. In semiconductor devices,
An impurity region is formed on the surface of the element formation region in the drift region between the well region and the drain region so as to surround the drain region, and a plurality of impedance elements are provided between the drain region and the source region. And an arbitrary point between the impedance elements is connected to the impurity region.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, a high-concentration second conductivity type impurity region is used as the impurity region.

According to a third aspect of the present invention, in the semiconductor device according to the first aspect, a high-concentration first-conductivity-type impurity region included in a first-conductivity-type impurity region is used as the impurity region. Is what you do.

According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, a resistance element is used as the impedance element.

According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, a capacitive element is used as the impedance element.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In this embodiment, the first conductivity type is p-type and the second conductivity type is n for convenience of explanation.
Although described as a type, the present invention is also applied to a case where p-type and n-type are reversed. The basic configuration of the LDMOSFET according to the present embodiment is the same as that of the LDMOSFET shown in FIG. 7 as a conventional example. FIGS. 1A and 1B are schematic diagrams showing an LDMOSFET according to an embodiment of the present invention, wherein FIG. 1A is a schematic plan view showing a state viewed from above, and FIG. FIG. The LDMOSFET according to the present embodiment is a conventional example of the LDMOSFET shown in FIG. 7, which surrounds the n + -type drain region 5 on the surface of the element forming region 4 in the drift region between the p-type well region 6 and the n + -type drain region. As described above, the plurality of n + -type impurity regions 12 are provided concentrically at regular intervals.

The n + type drain region 5 and the n + type source region 7 are connected by a series circuit of a plurality of resistance elements 13 having a high resistance value. This series circuit divides the voltage between the drain and the source into equal voltages. The connection portions of the resistance elements 13 are connected to the n + -type impurity regions 12, respectively.

Therefore, in the present embodiment, the potential divided into the equal voltage by the series circuit is applied to the n + -type impurity region 1.
2, the surface potential distribution of the N-type epitaxial layer 2 can be made uniform, as shown in FIG. It is possible to prevent a decrease in withstand voltage during the operation. Here, the current flowing in the series circuit connected between the drain and the source is very small, and is in a range that does not cause a problem in the transistor operation.

In this embodiment, the resistance element 1
3 is provided outside the LDMOSFET. However, the present invention is not limited to this. It may be formed inside the LDMOSFET. As a technology for forming the inside, a SIPOS (Semi-insulating Polycrystalline Si
licon).

In this embodiment, the n + type impurity region 12 is formed as the impurity region.
The present invention is not limited to this. For example, as shown in FIG. 3, the surface of the element forming region 4 in the drift region between the p-type well region 6 and the n + -type drain region 5 surrounds the n + -type drain region 5. The p-type impurity region 14 is formed as described above, and the p + -type impurity region 15 is formed on the surface of the element forming region 4 at a constant interval in the p-type impurity region 14 and concentrically. The connection portion may be connected to the p + -type impurity region 15.

In this embodiment, the resistance element 1
3, the voltage between the drain and the source is divided into equal voltages. However, the present invention is not limited to this. For example, as shown in FIGS. 4 and 5, a capacitive element 16 may be connected. In this case, the capacitance element 16 is connected in parallel between the drain and the source to form a snubber circuit, and noise at the time of switching can be reduced.

Here, in FIG. 4 and FIG.
6 is connected to the outside, but is not limited to this. For example, as shown in FIG.
Two polysilicon layers 17 may be formed in the FET, and capacitive coupling using an oxide film (not shown) between the two polysilicon layers 17 may be used.

In this embodiment, the impurity regions 12 and 15 are formed at regular intervals. However, the present invention is not limited to this. For example, if the impurity regions 12 and 15 are formed at different intervals, Any point between them may be connected to impurity region 12 or impurity region 15.

[0023]

According to the present invention, the first conductivity type semiconductor substrate, the second conductivity type epitaxial layer formed on the semiconductor substrate, and the semiconductor substrate reach from the surface of the epitaxial layer. High-concentration first-conductivity-type element isolation region formed as described above, an element formation region insulated and isolated by the element isolation region, a high-concentration second-conductivity-type drain region formed on the surface of the element formation region, and a drain region. A drain electrode that is electrically connected to and extends outside the element formation region; and a surface of the element formation region surrounding the drain region except near a lower portion of the drain electrode and in contact with the element isolation region. A first conductivity type well region formed on the epitaxial layer, a high-concentration second conductivity type source region formed on the surface of the element formation region so as to be included in the well region, and formed on the epitaxial layer. Semiconductor device having an insulating film formed, a gate electrode formed on the well region between the source region and the drain region via the insulating film, and a source electrode electrically connected to the source region Forming an impurity region on the surface of the element formation region in the drift region between the well region and the drain region so as to surround the drain region, and forming a plurality of resistance elements, capacitance elements, and the like between the drain region and the source region. Even if a high-potential wiring is connected to the drain region from outside the element isolation region across the element isolation region, an arbitrary point between the impedance elements is connected to the impurity region. A semiconductor device capable of preventing a decrease in withstand voltage between the drain and the source can be provided.

[Brief description of the drawings]

FIGS. 1A and 1B are schematic diagrams showing an LDMOSFET according to an embodiment of the present invention, wherein FIG. 1A is a schematic plan view showing a state viewed from above, and FIG. FIG.

FIG. 2 is a schematic diagram showing a potential distribution in an element formation region of the LDMOSFET according to the embodiment.

FIG. 3 shows an LDMOSFET according to another embodiment of the present invention.
(A) is a schematic plan view showing a state viewed from above, and (b) is a schematic cross-sectional view taken along BB 'in (a).

FIG. 4 is an LDMOSFET according to another embodiment of the present invention.
(A) is a schematic plan view showing a state viewed from above, and (b) is a schematic cross-sectional view taken along CC ′ in (a).

FIG. 5 shows an LDMOSFET according to another embodiment of the present invention.
(A) is a schematic plan view showing a state viewed from above, and (b) is a schematic sectional view taken along line DD ′ in (a).

FIG. 6 shows an LDMOSFET according to another embodiment of the present invention.
FIG. 3 is a schematic cross-sectional view showing a part of FIG.

7A and 7B are schematic views showing an LDMOSFET according to a conventional example, in which FIG. 7A is a schematic plan view showing a state viewed from above, and FIG. 7B is a schematic cross-sectional view taken along line EE ′ in FIG. It is.

FIG. 8 is a schematic diagram showing a potential distribution in an element formation region of an LDMOSFET according to a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 P-type semiconductor substrate 2 N-type epitaxial layer 3 p + -type element isolation region 4 element formation region 5 n + -type drain region 6 p-type well region 7 n + -type source region 8 insulating film 9 source electrode 10 gate electrode 11 drain electrode 12 n + -type Impurity region 13 Resistive element 14 P-type impurity region 15 P + -type impurity region 16 Capacitance element 17 Polysilicon layer

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yosuke Hagiwara 1048 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Works, Ltd.

Claims (5)

[Claims] A first conductive type semiconductor substrate; a second conductive type epitaxial layer formed on the semiconductor substrate; and a high concentration first conductive layer formed to reach the semiconductor substrate from a surface of the epitaxial layer. A conductive element isolation region, an element formation region insulated and separated by the element isolation region, a high-concentration second conductivity type drain region formed on the surface of the element formation region, and electrically connected to the drain region. And a drain electrode extending outside the element formation region, and surrounding the drain region except near the lower portion of the drain electrode, and formed on the surface of the element formation region so as to be in contact with the element isolation region. A first conductivity type well region,
A high-concentration second-conductivity-type source region formed on the surface of the element formation region so as to be included in the well region, an insulating film formed on the epitaxial layer, and the source region and the drain region. A semiconductor device comprising: a gate electrode formed on the well region between the gate electrodes via the insulating film; and a source electrode electrically connected to the source region. On the surface of the element formation region in the drift region between
An impurity region is formed so as to surround the drain region, the drain region and the source region are connected by a plurality of impedance elements, and an arbitrary point between the impedance elements is connected to the impurity region. A semiconductor device characterized by the following. 2. The semiconductor device according to claim 1, wherein a high-concentration second conductivity type impurity region is used as said impurity region. 3. The semiconductor device according to claim 1, wherein a high-concentration first-conductivity-type impurity region included in the first-conductivity-type impurity region is used as the impurity region. 4. The semiconductor device according to claim 1, wherein a resistance element is used as said impedance element. 5. The semiconductor device according to claim 1, wherein a capacitance element is used as the impedance element.