JPH10106281A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the electric field applied to a tunnel film by changing the load characteristic in accordance with a threshold value of a memory cell when electrons are emitted from a floating gate of the memory cell. SOLUTION: A comparator 7 compares a cell read data SD from a sense circuit 5 and an expected value data ED after a first stage electron emission, and sends a comparison result COMP to an electron emission operation control circuit 6. When the circuit 6 detects that all memory cells pass to emit electrons at the first stage, the circuit 6 outputs a second electron emission signal EES2 to a source voltage control circuit 10 and a verification voltage generation circuit 9. The circuit 9 outputs an electron verification voltage Vver to a row decoder 2 so as to judge by a threshold value of a memory cell whether or not electrons of a predetermined count are emitted. The circuit 10 supplies in compliance with the signal EES2 a source voltage Vsc lower than at the first stage to a source of a memory cell array 1 to perform second stage electron emission.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device such as a flash EEPROM capable of electrically rewriting data.

[0002]

2. Description of the Related Art A flash EEPROM (Electrically Erasable and Prog
In a nonvolatile semiconductor memory device such as a rammable read only memory (RAM), each memory cell forming a memory cell array has a structure having a floating gate electrically insulated between a control gate of a MOS transistor and a silicon substrate. ing.

In such a nonvolatile semiconductor memory device, electrons accumulated in the floating gate are released by setting the drain of the memory cell to a floating state, applying 0 V to the control gate, and applying an electron emission voltage (eg, 12 V) to the source. ) Is applied.
In such a state, a high electric field is generated from the source of the memory cell to the floating gate, and an FN (Fowler-Nordheim) current flows from the source of the memory cell to the floating gate. As is well known, electrons flow in the direction opposite to the direction of the current, so that electrons are emitted from the floating gate.

Here, the electron emission voltage applied to the source of the memory cell in the electron emission operation is generally supplied through a source voltage control circuit. Further, conventionally, as shown in FIG. 17, the source voltage control circuit has been configured by one pMOS transistor in which 0 V is input to the gate and a voltage of 12 V is supplied to the source. The load characteristics of such a source voltage control circuit are as shown in FIG. here,
Voltage V _s applied to the current I _s and the source flowing in the memory cell having a source supplied with voltage from a source voltage control circuit having such load characteristics, and load characteristics of the source current characteristic and the source voltage control circuit of the memory cell Is determined at the intersection of The source current characteristic of the memory cell is determined by the number of electrons stored in the floating gate. Further, as understood from FIG. 18, the voltage applied to the source of the memory cell increases as the electron emission operation shifts from the initial stage to the later stage.

[0005]

However, the conventional nonvolatile semiconductor memory device has the following problems.

That is, as described above, the voltage applied to the source of the memory cell rises as the electron emission operation shifts from the initial stage to the later stage. On the other hand, as the electron emission operation shifts from the initial stage to the later stage, the potential of the floating gate of the memory cell also increases. Here, when comparing the source voltage of the memory cell and the potential of the floating gate of the memory cell, the source voltage of the memory cell rises from the early stage to the late stage of electron emission, and the floating gate of the memory cell is higher than the source voltage. The potential rises. Therefore, the electric field applied to the tunnel film between the silicon substrate and the floating gate becomes highest at the initial stage of electron emission.

The high electric field applied to the tunnel film in the early stage of the electron emission deteriorates the tunnel film, and adversely affects the repetition characteristics of data rewriting and the data retention characteristics after repetition of data rewriting. .

[0008] Also, when the electron emission voltage application to the source of the memory cell by the conventional source voltage control circuit with respect to current I _s flowing to the source, as will be understood from FIG. 18, the electron emission initial current I _s Has a large current and a large current fluctuation from the early stage of electron emission to the late stage of electron emission.

As a nonvolatile semiconductor memory device capable of reducing a large current flowing between a source and a substrate due to these problems, Japanese Patent Application Laid-Open Nos. Hei 5-182483 (conventional example 1) and Hei 6-37285 (Conventional Example 2) and JP-A-7-235190 (Conventional Example 3), each of which has the following problems.

The nonvolatile semiconductor memory device of the prior art 1 has a depletion type nMOS for the source voltage control circuit.
It has a transistor. Here, the depletion type nMOS transistor requires a step of diffusing impurities into the channel region in order to set the threshold value to 0 V or less. That is, the depletion type nMOS transistor has a higher PMOS compared to the enhanced type nMOS transistor or pMOS transistor.
R number (photoresist number), that is, the number of steps is required. Therefore, the nonvolatile semiconductor memory device of Conventional Example 1 has a problem that the number of steps is increased as a whole since it includes a depletion type nMOS transistor.

The nonvolatile semiconductor memory device of Conventional Example 2 controls the rise time of the voltage applied to the source of the memory cell when electrons are emitted from the floating gate of the memory cell, or increases the voltage stepwise. A simple source voltage control circuit. However, in the nonvolatile semiconductor memory device of Conventional Example 2, since the voltage itself in the early stage of electron emission is not lowered, a high electric field is still applied to the tunnel film between the silicon substrate and the floating gate. Had a problem.

In the nonvolatile semiconductor memory device of Conventional Example 3, the electric charge accumulated in the floating gate of the memory cell is extracted via the source, and the threshold is shifted to an intermediate level between the threshold in the writing state and the target threshold. Thereafter, there is further provided a means for extracting the electric charge of the floating gate through the source and shifting the threshold from the intermediate level to the target threshold. However, the nonvolatile semiconductor memory device described in the conventional example 3 has no difference from the conventional technology described with reference to FIG.
As a matter of course, there was a problem that a high electric field was applied to the tunnel film between the silicon substrate and the floating gate at the initial stage of electron emission. Further, in the nonvolatile semiconductor memory device of the conventional example 3, a predetermined voltage is applied to the source of the memory cell in two stages at the time of electron emission, but a source voltage control circuit is not mentioned. No consideration is given to the source current characteristics of the memory cell and the load characteristics of the source voltage control circuit. As can be understood from consideration of the source current characteristics and the like of these memory cells, it is difficult to apply a constant voltage to the source of the memory cell for a certain period. That is, the nonvolatile semiconductor memory device of Conventional Example 3 also has a problem that it cannot be implemented.

As described above, none of the conventional examples is sufficient to reduce the high electric field applied to the tunnel film in the early stage of electron emission, which is a problem in the present invention.

An object of the present invention is to provide a nonvolatile semiconductor memory device capable of reducing a high electric field applied to a tunnel film at an early stage of electron emission in order to solve the above-mentioned problems.

[0015]

In order to solve the above-mentioned problems, the present invention focuses on the load characteristics of a source voltage control circuit for applying a voltage to the source of a memory cell.
By controlling the load characteristics, the current flowing to the source of the memory cell at the initial stage of electron emission is made lower than the current flowing to the source of the memory cell at the initial stage of electron emission by the conventional source voltage control circuit. The high electric field applied to the tunnel film in the early stage of electron emission is reduced.

Further, the present invention provides the following first to tenth nonvolatile semiconductor memory devices as means for solving the above-mentioned problems.

That is, according to the present invention, as a first nonvolatile semiconductor device, a memory cell having a control gate and a floating gate and capable of electrically erasing data, and a floating gate of the memory cell A source voltage control circuit that controls a voltage applied to the source of the memory cell when emitting electrons stored in the memory cell. A non-volatile semiconductor memory device characterized in that load characteristics can be changed according to a threshold value of the memory cell when emitting electrons.

According to the invention, as the second nonvolatile semiconductor memory device, in the first nonvolatile semiconductor memory device, the source voltage control circuit may include a plurality of pMOs.
An S transistor and a gate voltage control means,
The plurality of pMOS transistors each have a source connected to a power supply, a drain connected to a source of the memory cell, and the gate voltage control unit connected to a gate of each of the plurality of pMOS transistors. A nonvolatile semiconductor device for controlling voltages input to respective gates, wherein the load characteristics can be changed by controlling voltages input to the gates of the plurality of pMOS transistors. A storage device is obtained.

According to the present invention, as a third nonvolatile semiconductor memory device, in the first nonvolatile semiconductor memory device, the source voltage control circuit includes a pMOS transistor and a gate voltage control means. And p
The source of the MOS transistor is a power supply terminal connected to a power supply, and the drain of the pMOS transistor is
The gate voltage control means is connected to a source of the memory cell, is connected to a gate of the pMOS transistor, and controls a voltage input to the gate, and inputs a voltage to the gate of the pMOS transistor. A nonvolatile semiconductor memory device characterized in that the load characteristics can be changed by changing the voltage.

Further, according to the present invention, as a fourth nonvolatile semiconductor memory device, in the first nonvolatile semiconductor memory device, a control gate voltage control circuit for controlling a voltage applied to the control gate of the memory cell. Wherein the control gate voltage control circuit applies a negative voltage to the control gate when emitting electrons from the floating gate of the memory cell. can get.

According to the present invention, as a fifth nonvolatile semiconductor memory device, a memory cell having a control gate and a floating gate and capable of electrically erasing data; A source voltage control circuit for controlling a voltage applied to the source of the memory cell when emitting electrons stored in the gate, wherein the source voltage control circuit comprises a depletion type nMO.
The memory cell is configured not to include an S transistor, and has a load characteristic such that a source current of the memory cell at an early stage of electron emission and a source current of the memory cell at a late stage of electron emission are substantially the same. As a result, a nonvolatile semiconductor memory device having the features described above is obtained.

According to the invention, as a sixth nonvolatile semiconductor memory device, in the fifth nonvolatile semiconductor memory device, the source voltage control circuit may include a plurality of pMOs.
A nonvolatile semiconductor memory device comprising an S transistor and having load characteristics such that the source current of the memory cell is substantially the same from the early stage of electron emission to the late stage of electron emission is obtained.

According to the present invention, as a seventh nonvolatile semiconductor memory device, in the sixth nonvolatile semiconductor memory device, the source voltage control circuit emits electrons from a floating gate of the memory cell. The first pMO in which an electron emission signal indicating whether or not
An S transistor, a second pMOS transistor connected in series to the first pMOS transistor,
And a second gate voltage control means for applying a second gate control voltage having a voltage value between a ground voltage and a power supply voltage to the gate of the second pMOS transistor. A non-volatile semiconductor memory device is obtained.

According to the present invention, as an eighth nonvolatile semiconductor memory device, in the seventh nonvolatile semiconductor memory device, the second gate voltage control means may include a third p-type semiconductor memory device.
A source of the first pMOS transistor is a power supply terminal connected to a power supply; and a source of the second pMOS transistor is connected to a drain of the first pMOS transistor. A drain of the second pMOS transistor is connected to a source of the memory cell; a source of the third pMOS transistor is a power supply terminal connected to a power supply; Are connected to the gate of the second pMOS transistor, and the resistor is connected to the third pMOS transistor.
One end is connected to the drain of the pMOS transistor of
Since the other end is grounded, the second pMOS
A nonvolatile semiconductor memory device characterized by applying a second gate control voltage having a voltage value between the ground voltage and the power supply voltage to the gate of the transistor is obtained.

According to the present invention, as a ninth nonvolatile semiconductor memory device, in the eighth nonvolatile semiconductor device, the source voltage control circuit further includes an enhanced type nMOS transistor. nMO
The drain and gate of the S transistor are connected to the second p
Connected to the source of the MOS transistor.
The source of the OS transistor is connected to the drain of the second pMOS transistor, so that a nonvolatile semiconductor memory device is obtained.

Further, according to the present invention, as a tenth nonvolatile semiconductor memory device, in the fifth nonvolatile semiconductor memory device, a control gate voltage control circuit for controlling a voltage applied to the control gate of the memory cell. Wherein the control gate voltage control circuit applies a negative voltage to the control gate when emitting electrons from the floating gate of the memory cell. can get.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) As shown in FIG. 1, a nonvolatile semiconductor memory device according to a first embodiment of the present invention includes a memory cell array 1, a row decoder 2, a column decoder 3, , A column selection switch 4, a sense circuit 5, an electron emission operation control circuit 6, a comparator 7, an internal address generation circuit 8, a verify voltage generation circuit 9, and a source voltage control circuit 10. It is.

The memory cell array 1 has a control gate and a floating gate, and is formed by arranging a plurality of memory cells capable of electrically writing and erasing data in an array. A predetermined number of memory cells forming an arbitrary row have a control gate commonly connected to a row decoder 2, and a predetermined number of memory cells forming an arbitrary column have a drain commonly connected to a column selection switch 4. Have been. The sources of all the memory cells constituting the memory cell array 1 are commonly connected and connected to the source voltage control circuit 10.

Row decoder 2 has an internal address generation circuit 8
The row designated by, those for applying a voltage V _ver electron emission verification supplied by the verify voltage generating circuit 9.

The column decoder 3 includes an internal address generation circuit 8
The column selection switch 4 is controlled so as to read the data of the column specified by (1).

The sense circuit 5 detects and amplifies data of the memory cells in the column selected by the column selection switch 4 among the memory cells in the row specified by the row decoder 2, and
It outputs cell read data SD.

The electron emission operation control circuit 6 sends expected value data ED after electron emission to the comparator 7. The electron emission operation control circuit 6 sends a predetermined value to the internal address generation circuit 8 and the verify voltage generation circuit 9. And outputs an electron emission verify signal EEVS for verifying whether a predetermined number of electrons have been emitted from the memory cells. Further, the electron emission operation control circuit 6 includes the source voltage control circuit 1
0, an electron emission signal EES and a second electron emission signal EES2 for controlling the source control voltage V _SC when electrons are emitted from the memory cell, and the verify voltage generation circuit 9 also outputs the second electron emission signal EES2. Electron emission signal EES2
Is output.

The comparator 7 compares the cell read data SD received from the sense circuit 5 with the expected value data ED after the electron emission received from the electron emission operation control circuit 6, and compares the comparison result COMP with the electron emission operation. It is output to the control circuit 6.

The internal address generating circuit 8 from the electron emitting operation control circuit 6 receives the electron emission verify signal EEVS, generates an internal address I _ad electron emission verification,
And outputs an internal address I _ad for electron-emitting verify the row decoder 2 and column decoder 3.

The verify voltage generating circuit 9 determines whether a predetermined number of electrons have been emitted to the row decoder 2 based on the threshold value of the memory cell in accordance with the electron emission verify signal EEVS and the second electron emission signal EES2. and it outputs a voltage V _ver for electron emission verification.

The source voltage control circuit 10 has a plurality of load characteristics, and changes the load characteristics according to the electron emission signal EES and the second electron emission signal EES2 to supply the source control voltage V to the source of the memory cell array. _SC
Is controlled.

In the nonvolatile semiconductor memory device having such a configuration, electrons stored in the memory cells are emitted by performing the following operation processing.

First, according to the electron emission signal EES from the electron emission operation control circuit 6, the source voltage control circuit 10
Source control voltage V with respect to the source of memory cell array 1
_The first stage electron emission is performed by supplying _SC .

Next, the electron emission operation control circuit 6 outputs an electron emission verification signal EEVS to the internal address generation circuit 8 and the verification voltage generation circuit 9, and the internal address generation circuit 8 outputs the electron emission verification signal. EE
According to VS, for the row decoder 2 and the column decoder 3,
Outputs the internal address I _ad electron emission verify, the verify voltage generating circuit 9, according to the electron-emitting verify signal EEVS, voltage V _ver electron emission verification first stage (eg, 5V) to the row decoder 2 Output.

Next, the internal address I _ad for electron emission verify received by the row decoder 2 from the internal address generation circuit 8
Of the first-stage electron emission verify voltage V received from the verify voltage generation circuit 9 for the row specified by
supplies _ver, to control whether the column decoder 3 for column select switch 4 in accordance with the internal address I _ad electron emission verification, selects which columns.

Next, the sense circuit 5 detects and amplifies the data in the specified memory cell by an internal address I _ad electron emission verification, sends to the comparator 7 as the cell read data SD. On the other hand, from the electron emission operation control circuit 6, the expected value data ED after the first-stage electron emission is sent to the comparator 7.

The comparator 7 compares the cell read data SD with the expected value data ED after the first-stage electron emission to determine whether all the memory cells have passed the first-stage electron emission. Then, the comparison result COMP is sent to the electron emission operation control circuit 6.

When the electron emission operation control circuit 6 determines that all the memory cells have passed the first-stage electron emission,
The second electron emission signal EES2 is output to the source voltage control circuit 10 and the verify voltage generation circuit 9.

The source voltage control circuit 10 supplies the source voltage V _SC to the source of the memory cell array 1 in accordance with the second electron emission signal EES2 to perform the second-stage electron emission.

Thereafter, similarly, the data of the memory cell is detected to determine whether or not the second-stage electron emission has been completed. However, the voltage V for the second stage electron emission verification
_ver is a lower voltage than the first one (eg 3V)
It is.

More specifically, in the present embodiment, as shown in FIGS. 2 and 3, the source voltage control circuit 10 includes two pMOS transistors MP1 and MP2,
Gate voltage control means for controlling voltages input to the respective gates of the two pMOS transistors MP1 and MP2 according to the electron emission signal EES and the second electron emission signal EES2. The level shifter circuit 11 has an input terminal IN and first and second output terminals THVOUT and B
HVOUT is a circuit that changes a voltage level according to an input signal. Also, the first output terminal T
From HVOUT, a voltage that changes in the same manner as the input signal input to the input terminal IN is output, and the second output terminal B
HVOUT outputs a voltage that changes by inverting the input signal.

As shown in FIG. 4, the source voltage control circuit 10 having the above configuration has the first load characteristic when only the pMOS transistor MP1 is turned on, and the two pMOS transistors MP1 and MP1. It has two load characteristics, the second load characteristic when both MP2s are on, and operates, for example, as shown in FIG.

In FIG. 5, between time t ₁ and time t ₂ ,
An electron emission period of the first stage, only the pMOS transistor MP1 is turned on, as the source control voltage V _SC, to supply the power supply voltage V _pp. In this case, the load characteristics of the source voltage control circuit 10 are the first load characteristics shown in FIG. The voltage supplied to the source of the memory cell is a voltage determined at the intersection (points a and b in FIG. 4) of the current characteristic of the memory cell and the first load characteristic of the source voltage control circuit 10.

[0050] During time t ₂ ~ time t ₃ is an electron emission verify period of the first stage to verify whether the first stage of the electron emission has been completed, the voltage V _ver as, for example, 5V for electron emission verification, Perform electron emission verify. Here, assuming that all the memory cells passes the electron emission first stage, but advances the story below, if all of the memory cells does not pass electron emission first step, again the time t ₁ ~ Time it goes without saying that performs processing between t _2.

The period from time t ₃ to time t ₄ is a second stage electron emission period, in which both the two pMOS transistors MP 1 and MP 2 are turned on, and the power supply voltage V _pp is supplied as the source control voltage V _SC I do. The load characteristic of the source voltage control circuit 10 in this case is the second load characteristic shown in FIG. Further, the voltage supplied to the source of the memory cell is a voltage determined at the intersection (points c and d in FIG. 4) of the current characteristic of the memory cell and the second load characteristic of the source voltage control circuit 10.

[0052] Time t ₄ ~ time t ₅ between is an electron emission verify period of the second stage to the second stage of the electron emission is to verify whether the end, as the voltage V _ver for electron emission verify for example 3V, Perform electron emission verify. Here, when all the memory cells pass the second-stage electron emission, the electron emission operation ends. On the other hand, if all the memory cells do not pass the second-stage electron emission,
Carry out the process between the time t ₃ ~ time t ₄ again.

As described above, in the nonvolatile semiconductor memory device according to the present embodiment, the source voltage control circuit 10 has two load characteristics. The determined voltage is supplied to the source of the memory cell, and then the electrons stored in the memory cell are determined based on the threshold value of the memory cell. In the later stage of the electron emission, the voltage determined by the second load characteristic is supplied to the source of the memory cell. can do.

Therefore, in this embodiment, since the current flowing to the source of the memory cell at the initial stage of electron emission can be suppressed, the electric field applied to the tunnel film of the memory cell can be reduced.

In the present embodiment, the source voltage control circuit 10 has been described as having the first and second load characteristics determined by the two pMOS transistors MP1 and MP2, but based on the same principle. Needless to say, a configuration in which more pMOS transistors, for example, four pMOS transistors are arranged in parallel, may have four load characteristics. In that case, it goes without saying that the voltage applied to the source of the memory cell can be set more finely.

In this embodiment, two pM
Although the size of the OS transistors MP1 and MP2 is not mentioned, the two pMOS transistors M
By making the transistor sizes of P1 and MP2 the same or different, the relationship between the two load characteristics of the source voltage control circuit 10 can be adjusted, and thus the voltage applied to the source of the memory cell can be adjusted. It goes without saying that you can do it.

(Second Embodiment) A nonvolatile semiconductor memory device according to a second embodiment of the present invention is a modification of the nonvolatile semiconductor memory device according to the first embodiment, and includes a source voltage control circuit 10a. It is characterized by the following.

Source voltage control circuit 10a of the present embodiment
Is a pMOS transistor MP as shown in FIG.
And the electron emission signal EES and the second electron emission signal EES2
Gate voltage control means for controlling the voltage input to the gate of the pMOS transistor MP in accordance with
PMOS transistors MP1, MP2, MP3 and n
By supplying one of the first voltage determined by the MOS transistor MN1 and the second voltage determined by the pMOS transistor MP4 and the nMOS transistor MN2 to the gate of the pMOS transistor MP, Similar to the first embodiment, it has two load characteristics and operates, for example, as shown in FIG. Note that an electron emission verify signal EEVS, an expected value data ED after electron emission, a cell read data SD, a comparison result COMP, an electron emission verification internal address I _ad , and an electron emission verification voltage V _ver not shown in FIG. The operation related to FIG.

In FIG. 7, between time t ₁ and time t ₂ ,
This is the first-stage electron emission period, in which the pMOS transistor MP1 and the nMOS transistor MN1 are turned on and the pM
OS transistor MP4 and nMOS transistor MN
2 is turned off, and three pMOS transistors MP1, MP2, MP
3 and the first voltage determined by the nMOS transistor MN1 (for example, 6V when the power supply voltage _Vpp is 12V). In this case, the load characteristics of the source voltage control circuit 10a are the first load characteristics shown in FIG.

[0060] During time t ₂ ~ time t ₃ is an electron emission verify period of the first stage to verify whether the first stage of the electron emission has been completed, as the voltage V _ver for electron emission verify, for example 5V, Perform electron emission verify. Here, assuming that all the memory cells passes the electron emission first stage, but advances the story below, if all of the memory cells does not pass electron emission first step, again the time t ₁ ~ Time it goes without saying that performs processing between t _2.

The period from time t ₃ to time t ₄ is the second stage electron emission period, in which only the nMOS transistor MN2 is turned on and the gate of the pMOS transistor MP is set to 0V.
Is supplied. In this case, the load characteristics of the source voltage control circuit 10a are the second load characteristics shown in FIG.

[0062] Time t ₄ ~ time t ₅ between is an electron emission verify period of the second stage to the second stage of the electron emission is to verify whether the end, as the voltage V _ver for electron emission verify for example 3V, Perform electron emission verify. Here, when all the memory cells pass the second-stage electron emission, the electron emission operation ends. On the other hand, if all the memory cells do not pass the second-stage electron emission,
Carry out the process between the time t ₃ ~ time t ₄ again.

As described above, also in the nonvolatile semiconductor memory device of the present embodiment, as in the first embodiment, the source voltage control circuit 10a has two load characteristics, In the early stage of the emission, a voltage determined by the first load characteristic is supplied to the source of the memory cell, and then the electrons stored in the memory cell are determined by the threshold value of the memory cell. Can be supplied to the source of the memory cell.

Therefore, in the present embodiment, the current flowing to the source of the memory cell at the initial stage of electron emission can be suppressed, so that the electric field applied to the tunnel film of the memory cell can be reduced.

In the present embodiment, it has been described that the voltage supplied to the gate of pMOS transistor MP assumes two voltage values, and that source voltage control circuit 10a has two load characteristics. However, based on the same principle, the voltage supplied to the gate of the pMOS transistor MP may take a larger voltage value, in which case the load characteristics of the source voltage control circuit 10a further increase, It goes without saying that the voltage supplied to the source of each memory cell can be set more finely.

(Third Embodiment) A nonvolatile semiconductor memory device according to a third embodiment of the present invention is similar to that of the nonvolatile semiconductor memory device according to the first embodiment, as in the second embodiment. This is a modification and has a feature in the source control circuit 10b.

Source voltage control circuit 10b of the present embodiment
Is a pMOS transistor MP as shown in FIG.
And the electron emission signal EES and the second electron emission signal EES2
Gate voltage control means for controlling the voltage input to the gate of the pMOS transistor MP in accordance with the following formula. A voltage determined by the resistor R and one of the two nMOS transistors MN1 or MN2 is applied to the gate of the pMOS transistor MP. By being supplied, it has two load characteristics as in the second embodiment, and operates, for example, as shown in FIG. The electron emission verify signal EEVS not shown in FIG. 9, the expected value data ED after electron emission, the cell read data SD, the comparison result COMP, the internal address I _ad electron emission verification,
And operations related to voltage V _ver for electron emission verification,
The description is omitted because it is the same as FIG.

In FIG. 9, between time t ₁ and time t ₂ ,
This is the first-stage electron emission period, in which the pMOS transistor MP1 and the nMOS transistor MN1 are turned on and the pM
The gate of the OS transistor MP has a resistor R and an nMOS
A first voltage determined by a connection point with the transistor MN1 (for example, when the power supply voltage _Vpp is 12 V and the resistance ratio of the resistor across the connection point is 1: 1, 6 V)
Is supplied. In this case, the load characteristics of the source voltage control circuit 10b are the first load characteristics shown in FIG.

[0069] During the time t ₂ ~ time t ₃ is an electron emission verify period of first stage to verify whether the first stage of the electron emission is completed, as the voltage V _ver electron emission verification example 5V, Perform electron emission verify. Here, assuming that all the memory cells passes the electron emission first stage, but advances the story below, if all of the memory cells does not pass electron emission first step, again the time t ₁ ~ Time it goes without saying that performs processing between t _2.

The period between time t ₃ and time t ₄ is the second stage electron emission period, in which the pMOS transistors MP1 and nM
The OS transistor MN2 is turned on, and 0 V is supplied to the gate of the pMOS transistor MP. in this case,
The load characteristics of the source voltage control circuit 10b are the second load characteristics shown in FIG.

[0071] Time t ₄ ~ time t ₅ between is an electron emission verify period of the second stage to the second stage of the electron emission is to verify whether the end, as the voltage V _ver for electron emission verify for example 3V, Perform electron emission verify. Here, when all the memory cells pass the second-stage electron emission, the electron emission operation ends. On the other hand, if all the memory cells do not pass the second-stage electron emission,
Carry out the process between the time t ₃ ~ time t ₄ again.

As described above, also in the nonvolatile semiconductor memory device of the present embodiment, as in the second embodiment, the source voltage control circuit 10b has two load characteristics, In the early stage of the emission, a voltage determined by the first load characteristic is supplied to the source of the memory cell, and then the electrons stored in the memory cell are determined by the threshold value of the memory cell. Can be supplied to the source of the memory cell.

Therefore, in this embodiment, since the current flowing to the source of the memory cell at the initial stage of electron emission can be suppressed, the electric field applied to the tunnel film of the memory cell can be reduced.

In the present embodiment, it has been described that the voltage supplied to the gate of pMOS transistor MP assumes two voltage values, and that source voltage control circuit 10b has two load characteristics. However, based on the same principle, the voltage supplied to the gate of the pMOS transistor MP may take a larger voltage value. In this case, the load characteristics of the source voltage control circuit 10b are further increased. It goes without saying that the voltage supplied to the source of each memory cell can be set more finely.

(Fourth Embodiment) As shown in FIG. 10, a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention includes a memory cell array 1, a row decoder 2, a column decoder 3, , A column selection switch 4, a sense circuit 5, an electron emission operation control circuit 6a, a comparator 7, an internal address generation circuit 8, a source voltage control circuit 10, and a control gate voltage control circuit 13. Things.
Note that, in FIG. 10, the same reference numerals are given to components performing the same operations as the components illustrated in FIG.

The electron emission operation control circuit 6a operates in substantially the same manner as the electron emission operation control circuit 6 shown in FIG. 1 except that the electron emission verification signal EEVS is replaced with a control gate voltage control circuit instead of the verification voltage generation circuit 9. 13 and also outputs an electron emission signal EES and a second electron emission signal EES2 to the control gate voltage control circuit 13.

The control gate voltage control circuit 13
In accordance with the electron emission verify signal EEVS and the second electron emission signal EES2, the electron emission verifying voltage V applied to the control gate when electron emission is verified.
_ver to the row decoder 2 and, in accordance with the electron emission signal EES and the second electron emission signal EES2,
A control gate control voltage V, which is a negative voltage applied to the control gate of the memory cell when emitting electrons from the floating gate of the memory cell
_{The CGC} is output to the row decoder 2.

In this embodiment, when emitting electrons,
The example in which the method of applying a negative voltage to the control gate of the memory cell is applied to the nonvolatile semiconductor memory device of the first embodiment has been described, but the nonvolatile semiconductor memory of the second and third embodiments has been described. It goes without saying that the present invention can be similarly applied to a storage device. That is, the source voltage control circuit 10 of the present embodiment may be replaced with the source voltage control circuit 10a or 10b of the second or third embodiment.

(Fifth Embodiment) As shown in FIG. 11, a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention comprises a memory cell array 1, a row decoder 2, a column decoder 3, , A column selection switch 4, a sense circuit 5, an electron emission operation control circuit 6b, a comparator 7, an internal address generation circuit 8, a verify voltage generation circuit 9, and a source voltage control circuit 12. It is. Note that, in FIG. 11, the same reference numerals are given to components performing the same operations as the respective components shown in FIG.

The electron emission operation control circuit 6b operates in substantially the same manner as the electron emission operation control circuit 6 shown in FIG.
Output only ES.

The source voltage control circuit 12 does not include a depletion type nMOS transistor, and the source current of the memory cell in the early stage of electron emission and the source current of the memory cell in the late stage of electron emission are substantially equal. The load characteristics are the same as those described above.

More specifically, the source voltage control circuit 12
As shown in FIG. 12, the main part is composed of first and second pMOS transistors MP1 and MP2 and second gate voltage control means 14. Further, the second gate voltage control means 14 controls the third pMOS transistor MP
3 and a resistor R. The power supply voltage V _pp is supplied to the source of the first pMOS transistor MP1, and the source of the second pMOS transistor MP2 is
The drain of the first pMOS transistor MP1 is connected. The drain of the second pMOS transistor MP2 is connected to the source of the memory cell array 1. The power supply voltage V _pp is supplied to the source of the third pMOS transistor MP3, and the drain and gate of the third pMOS transistor MP3 are connected to one end of the resistor R. Further, the third pMOS transistor M2 is connected to the gate of the second pMOS transistor MP2.
A second gate control voltage, which is a potential determined by P3 and the resistor R and has a voltage value between the ground voltage and the power supply voltage, is supplied.

The source voltage control circuit 12 according to the present embodiment having such a configuration has load characteristics as shown in FIG. 13, and suppresses the current flowing to the source of the memory cell array 1 at the initial stage of electron emission. Can be.

Therefore, according to the source voltage control circuit 12 having a load characteristic, the electric field applied to the tunnel film of the memory cell can be reduced at the initial stage of electron emission.

(Sixth Embodiment) A nonvolatile semiconductor memory device according to a sixth embodiment of the present invention is an improved version of the fifth embodiment, and therefore has a configuration other than the source voltage control circuit 12a. Elements are similar to those of the nonvolatile semiconductor memory device according to the fifth embodiment.

Source voltage control circuit 12a of the present embodiment
As shown in FIG. 14, the main part of the source voltage control circuit 12 of the fifth embodiment is nMO
It has a configuration in which an S transistor MN1 is added.

As shown in FIG. 15, the source voltage control circuit 12a having the above-described structure has the load characteristic shown in FIG. 13 and the added nMOS transistor MN.
The load characteristics of the memory cell array 1 are combined with the load characteristics of the memory cell array 1, and the current flowing to the source of the memory cell array 1 in the early stage of electron emission can be suppressed and the electron emission can be started in the same manner as in the fifth embodiment. It is possible to shorten the time until the above.

Therefore, according to the source voltage control circuit 12a having such a configuration, at the initial stage of electron emission,
The electric field applied to the tunnel film of the memory cell can be reduced, and compared with the fifth embodiment,
The time required for electron emission can be reduced.

(Seventh Embodiment) As shown in FIG. 16, a nonvolatile semiconductor memory device according to a seventh embodiment of the present invention comprises a memory cell array 1, a row decoder 2, a column decoder 3, , A column selection switch 4, a sense circuit 5, an electron emission operation control circuit 6c, a comparator 7, an internal address generation circuit 8, a source voltage control circuit 12, and a control gate voltage control circuit 13. Things.
In FIG. 16, the same reference numerals are given to components that perform the same operations as the respective components shown in FIG.

The electron emission operation control circuit 6c operates in substantially the same manner as the electron emission operation control circuit 6b shown in FIG. 11 except that the electron emission verification signal EEVS is replaced with a control gate voltage control circuit instead of the verification voltage generation circuit 9. 13 and also outputs an electron emission signal EES to the control gate voltage control circuit 13.

The control gate voltage control circuit 13
According electron emission verify signal EEVS, an electron emission voltage V _ver for verification to be applied to the control gate during the verify the electron emission, and outputs the row decoder 2, according to the electron-emitting signal EES, the memory cell floating gate A control gate control voltage V _CGC , which is a negative voltage applied to the control gate of the memory cell when electrons are emitted from the memory cell, is output to the row decoder 2.

In this embodiment, when emitting electrons,
The example in which the method of applying the negative voltage to the control gate of the memory cell is applied to the nonvolatile semiconductor memory device of the fifth embodiment has been described. However, it goes without saying that the same can be applied. That is, the source voltage control circuit 12 of the present embodiment may be replaced with the source voltage control circuit 12a of the sixth embodiment.

[0093]

As described above, according to the present invention, the source voltage control circuit for controlling the voltage applied to the source of the memory cell array has one of the following two characteristic load characteristics. , The electric field applied to the tunnel film of the memory cell at the initial stage of electron emission can be reduced.

Here, one of the features of the source voltage control circuit of the present invention is that it has a plurality of load characteristics and can change the load characteristics according to the threshold value of the memory cell.

The other feature of the source voltage control circuit of the present invention is that the source current of the memory cell at the initial stage of electron emission is:
It has a load characteristic such that the source current of the memory cell at the latter stage of electron emission is substantially the same.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a source voltage control circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a configuration of a level shifter circuit used in a source voltage control circuit.

FIG. 4 is a diagram showing load characteristics of the source voltage control circuit according to the first embodiment of the present invention.

FIG. 5 is a timing chart showing the operation of the first exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating a configuration of a source voltage control circuit according to a second embodiment of the present invention.

FIG. 7 is a timing chart showing the operation of the second exemplary embodiment of the present invention.

FIG. 8 is a diagram illustrating a configuration of a source voltage control circuit according to a third embodiment of the present invention.

FIG. 9 is a timing chart showing the operation of the third embodiment of the present invention.

FIG. 10 is a block diagram illustrating a configuration of a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 11 is a block diagram illustrating a configuration of a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 12 is a diagram illustrating a configuration of a source voltage control circuit according to a fifth embodiment of the present invention.

FIG. 13 is a diagram illustrating load characteristics of a source voltage control circuit according to a fifth embodiment of the present invention.

FIG. 14 is a diagram illustrating a configuration of a source voltage control circuit according to a sixth embodiment of the present invention.

FIG. 15 is a diagram illustrating load characteristics of a source voltage control circuit according to a sixth embodiment of the present invention.

FIG. 16 is a block diagram illustrating a configuration of a nonvolatile semiconductor memory device according to a seventh embodiment of the present invention.

FIG. 17 is a diagram showing a configuration of a conventional source voltage control circuit.

FIG. 18 is a diagram showing load characteristics of a conventional source voltage control circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Memory cell array 2 Row decoder 3 Column decoder 4 Column selection switch 5 Sense circuit 6 Electron emission operation control circuit 6a Electron emission operation control circuit 6b Electron emission operation control circuit 6c Electron emission operation control circuit 7 Comparator 8 Internal address generation circuit 9 Verify Voltage control circuit 10 Source voltage control circuit 10a Source voltage control circuit 10b Source voltage control circuit 11 Level shifter circuit 12 Source voltage control circuit 12a Source voltage control circuit 13 Control gate voltage control circuit 14 Second gate voltage control means SD cell readout data ED Electronics expected value data COMP the comparison result EEVS emission verify signal I _ad electron emission verifying internal address V _ver electron emission verifying voltage V _CGC control gate control voltage EES emission signal after release EES2 first Electron emission signal V _SC source control voltage

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshikatsu Jimbo 5-7-1 Shiba, Minato-ku, Tokyo Inside NEC Corporation (72) Inventor Kazuhisa Ninomiya 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation

Claims (10)

[Claims] 1. A memory cell having a control gate and a floating gate and capable of electrically erasing data, and a source of the memory cell when emitting electrons stored in the floating gate of the memory cell. A source voltage control circuit that controls a voltage applied to the memory cell, wherein the source voltage control circuit is configured to emit electrons from a floating gate of the memory cell according to a threshold value of the memory cell. And a load characteristic that can be changed. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said source voltage control circuit includes a plurality of pMOS transistors and a gate voltage control means, and each of said plurality of pMOS transistors has a source. A gate connected to a power supply, a drain connected to a source of the memory cell, the gate voltage control unit connected to each gate of the plurality of pMOS transistors, and controlling a voltage input to each of the gates; Wherein the load characteristics can be changed by controlling voltages input to the gates of the plurality of pMOS transistors. 3. The nonvolatile semiconductor memory device according to claim 1, wherein said source voltage control circuit comprises a pMOS transistor and a gate voltage control means, and a source of said pMOS transistor is connected to a power supply. A power supply terminal, a drain of the pMOS transistor is connected to a source of the memory cell, and the gate voltage control means is connected to a gate of the pMOS transistor and controls a voltage input to the gate. And wherein the load characteristics can be changed by changing a voltage input to the gate of the pMOS transistor. 4. The nonvolatile semiconductor memory device according to claim 1, further comprising a control gate voltage control circuit for controlling a voltage applied to said control gate of said memory cell, wherein said control gate voltage control circuit comprises: A non-volatile semiconductor memory device, wherein a negative voltage is applied to the control gate when electrons are emitted from the floating gate of the memory cell. 5. A memory cell having a control gate and a floating gate and capable of electrically erasing data, and a source of the memory cell when emitting electrons stored in the floating gate of the memory cell. A source voltage control circuit that controls a voltage applied to the memory cell, wherein the source voltage control circuit is configured not to include a depletion type nMOS transistor, A nonvolatile semiconductor memory device having a load characteristic such that a source current and a source current of the memory cell at a later stage of electron emission become substantially the same. 6. The nonvolatile semiconductor memory device according to claim 5, wherein said source voltage control circuit includes a plurality of pMOS transistors, and a source current of said memory cell is increased from an early stage of electron emission to a late stage of electron emission. A nonvolatile semiconductor memory device having load characteristics that are substantially the same. 7. The nonvolatile semiconductor memory device according to claim 6, wherein said source voltage control circuit inputs an electron emission signal indicating whether or not electrons are emitted from a floating gate of said memory cell to said gate. A first pMOS transistor, a second pMOS transistor connected in series to the first pMOS transistor, and a voltage between a ground voltage and a power supply voltage with respect to a gate of the second pMOS transistor. And a second gate voltage control means for applying a second gate control voltage having a value. 8. The nonvolatile semiconductor memory device according to claim 7, wherein said second gate voltage control means includes a third pMOS transistor and a resistor, and wherein a source of said first pMOS transistor is a power supply. And a source terminal of the second pMOS transistor is connected to the first terminal.
The drain of the second pMOS transistor is connected to the source of the memory cell, and the source of the third pMOS transistor is a power supply terminal connected to a power supply. A drain and a gate of the third pMOS transistor are connected to a gate of the second pMOS transistor; the resistor has one end connected to a drain of the third pMOS transistor and the other end grounded; Accordingly, a second gate control voltage having a voltage value between a ground voltage and a power supply voltage is applied to the gate of the second pMOS transistor. 9. The nonvolatile semiconductor memory device according to claim 8, wherein said source voltage control circuit is an enhanced type nM.
An OS transistor, wherein the drain and gate of the nMOS transistor are connected to the source of the second pMOS transistor, and the source of the nMOS transistor is connected to the second pMO
A nonvolatile semiconductor memory device, which is connected to a drain of an S transistor. 10. The nonvolatile semiconductor memory device according to claim 5, further comprising a control gate voltage control circuit for controlling a voltage applied to said control gate of said memory cell, wherein said control gate voltage control circuit comprises: A non-volatile semiconductor memory device, wherein a negative voltage is applied to the control gate when electrons are emitted from the floating gate of the memory cell.