JPH10106258A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain simplification and a large capacity of the circuit of a semiconductor memory device by providing the device with a discharging element for discharging electric charges of a write word line corresponding to one off operations of first and second control elements which are controlled by a bit selection line and a word selection line. SOLUTION: When both bit selection lien 54 and word selection lien 55 are selected for writing data, N-ch type transistors 51, 52 are turned on, and a write word line or a write word line 56 is charged to be at an H level. When the transistors 51, 52 have the same charge speed to the write word line 56 for the N-ch type transistor as in the prior art, it can be realized with a smaller area than in the prior art. When a write address is non-selected, any one of the bit selection line 54 and the word selection line 55 is non-selected, the N-ch type transistor 51 or 52 is turned off, and electric charges of the write word line are set at an L level by a transistor 53 which is always turned on.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a memory cell group including a plurality of dynamic memory cells.

[0002]

2. Description of the Related Art FIG. 1 shows a peripheral circuit of a memory cell. In FIG. 1, reference numeral 300 denotes a dynamic memory cell 10.
A memory cell group consisting of 0s, and a portion indicated by 300 in FIG. 1 indicates a memory cell for one address having an n-bit width configuration. 1 is a bit select line, 2 is a word select line, 20
0 is a NOR circuit for controlling signals on the bit select line 1 and the word select line 2, 3 is a write word line for performing a write operation at the output of the NOR circuit, that is, a write word line, 4.6 is a write bit line, that is, a write bit line, Reference numerals 5 and 7 are read bit lines, that is, read bit lines, and 8 is a read word line, that is, read word lines.

FIG. 2 shows a dynamic memory cell 10.
0 shows a circuit diagram. In FIG. 2, 21 is a write access transistor, 22 is a charge storage capacitance, 23 is a read bit line or read bit line drive transistor, 24 is a read access transistor, 25 is a write bit line or write bit line, 26 Is a write word line or write word line, 27 is a read word line or read word line,
28 is a read bit line, that is, a read bit line.

FIG. 8 shows a conventional NOR circuit 2.
FIG. 31 and 32 are P-channel transistors (hereinafter referred to as Pch transistors),
34 is an N-channel transistor (hereinafter, referred to as an Nch transistor), 35 is a bit selection line, 36 is a word selection line, and 37 is a write word line, that is, a write word line.

The operation of the conventional semiconductor memory device configured as described above will be described. First, when a write address is selected, as shown in FIG. 3, control is performed by the NOR circuit 200 of FIG. 1 in order to write data only at an address crossed by a bit decoder and a word decoder. That is, when both the bit select line and the word select line are at L level, the output of the NOR circuit 200 shown in FIG. 8 is charged to the H level by turning on the Pch transistor 31 or 32, and the write access signal shown in FIG. The transistor 21 is turned on, and data is written from the write bit line, that is, the write word line 37, to the charge storage capacitance.

Next, when the write address is not selected,
Either the bit selection line or the word selection line becomes a non-selection line, and the Pch type transistor 31 or 32
Is turned off, and conversely, the Nch type transistor 33 or 3
4 is turned on, the charge of the write word line, that is, the write word line 37 is pulled down to L level by the Nch type transistor, and the write transistor of the memory is turned off.

[0007]

Here, one NOR circuit is required at one address, and as the memory capacity increases, the number of NOR circuits increases in proportion thereto. This NOR circuit is composed of four transistors as shown in FIG. 8 and occupies a large area. This makes it difficult to increase the capacity of the memory.

The present invention has been made to solve such a problem, and provides means for increasing the capacity, which has been difficult until now, by simplifying the NOR circuit. is there.

According to a first aspect of the present invention, first and second control units are connected between a write word line and a ground unit, are always in a conductive state when a power supply is applied, and are controlled by a bit select line and a word select line. A discharge element for discharging the electric charge of the write word line in response to one of the off-operations of the element;
And NO composed of the second control element and the discharging element
An object of the present invention is to provide a semiconductor memory device that can simplify the R circuit and increase the capacity.

According to a second aspect of the present invention, the first and second control elements and the discharging element are constituted by transistors, and the first and second control elements and the discharging element are formed of N.
An object of the present invention is to provide a semiconductor memory device which can simplify an OR circuit and can increase the capacity.

According to a third aspect of the present invention, the first and second control elements are connected by connecting a gate of a transistor constituting a discharging element to a power supply, connecting a source to a ground portion, and connecting a drain to a write word line. Another object of the present invention is to provide a semiconductor memory device that can simplify a NOR circuit including a discharge element and can increase the capacity.

According to a fourth aspect of the present invention, a transistor constituting a discharging element is an N-channel transistor, and a NOR comprising first and second control elements and a discharging element is provided.
It is an object of the present invention to obtain a semiconductor memory device whose circuit can be simplified and whose capacity can be increased.

According to a fifth aspect of the present invention, the first and second control elements are constituted by transistors, and the discharge element is constituted by resistors, so that a NOR circuit comprising the first and second control elements and the discharge element is provided. Is intended to obtain a semiconductor memory device capable of simplifying the process and increasing the capacity.

According to a sixth aspect of the present invention, one end of a resistor constituting a discharging element is connected to a ground portion, and the other end is connected to a write word line, and comprises a first and a second control element and a discharging element. It is an object of the present invention to obtain a semiconductor memory device in which a NOR circuit can be simplified and a capacity can be increased.

According to a seventh aspect of the present invention, the first and second control elements are constituted by N-channel transistors, so that the NOR circuit comprising the first and second control elements and the discharging element can be simplified, and a large capacity can be obtained. It is an object of the present invention to obtain a semiconductor memory device that can be integrated.

[0016]

According to a first aspect of the present invention, there is provided a semiconductor memory device including a memory cell group including a plurality of dynamic memory cells and a read for transmitting a signal read from the memory cell group to an output. A bit line, a write bit line for writing input data to the memory cell group, a write word line for controlling writing to the memory cell, a read word line for controlling reading from the memory cell, A bit selection line for selecting a bit line, a word selection line for selecting the write word line, and a write control circuit that receives the bit selection line and the word selection line as inputs and outputs a write word line. A semiconductor memory device comprising a line memory provided with a write control circuit, wherein the write control circuit is controlled by a bit select line. A control element is controlled by said word select line, and a second control element connected between the write word line and a power source in series with the first control element,
It is connected between the write word line and the ground portion and is always in a conductive state when a power supply is applied, and is used for turning off one of the first and second control elements controlled by the bit select line and the word select line. And a discharge element for discharging the charge of the write word line accordingly.

In the semiconductor memory device of the second invention,
The first and second control elements and the discharging element are constituted by transistors.

In the semiconductor memory device of the third invention,
A memory cell group including a plurality of dynamic memory cells, a read bit line for transmitting a signal read from the memory cell group to an output, and a write bit line for writing input data to the memory cell group; A write word line for controlling writing to the memory cell, a read word line for controlling reading from the memory cell,
A bit selection line for selecting the write bit line;
A word selection line for selecting the write word line;
In a semiconductor memory device including a line memory including a write control circuit that inputs the bit select line and the word select line and outputs a write word line, the write control circuit is controlled by the bit select line. 1 control element, a second control element controlled by the word select line, connected in series with the first control element between the write word line and a power supply, and the write word line and a grounding unit. And a transistor that constitutes a discharge element of the write control circuit, wherein a gate is connected to a power supply, a source is connected to a ground, and a drain is connected to a write word line. It is characterized by having been done.

In the semiconductor memory device of the fourth invention,
The transistor constituting the discharging element is an Nch transistor.

In the semiconductor memory device of the fifth invention,
The first and second control elements are constituted by transistors, and the discharge elements are constituted by resistors.

In the semiconductor memory device of the sixth invention,
A memory cell group including a plurality of dynamic memory cells, a read bit line for transmitting a signal read from the memory cell group to an output, and a write bit line for writing input data to the memory cell group; A write word line for controlling writing to the memory cell, a read word line for controlling reading from the memory cell,
A bit selection line for selecting the write bit line;
A word selection line for selecting the write word line;
In a semiconductor memory device including a line memory including a write control circuit that inputs the bit select line and the word select line and outputs a write word line, the write control circuit is controlled by the bit select line. 1 control element, a second control element controlled by the word select line, connected in series with the first control element between the write word line and a power supply, and the write word line and a grounding unit. And a discharge element connected between the write control circuit and the resistor constituting the discharge element of the write control circuit, wherein one end is connected to a ground portion, and the other end is connected to a write word line. I do.

In the semiconductor memory device of the seventh invention,
It is characterized in that the first and second control elements are constituted by Nch transistors.

The embodiment of the present invention has the following means for solving the problem. In the first embodiment,
A memory cell group composed of dynamic memory cells, a write bit select line output from a bit decoder, a write word select line output from a word decoder, a NOR circuit controlling the bit select line and the word select line, NO
A write word line, ie, a write word line, which is an output of the R circuit and is connected to a write access transistor of the memory; a write bit line, ie, a write bit line for transmitting input data to the memory cell; and data from the memory cell, which is transmitted to the output. A read bit line, a read word line output from a word decoder, that is, a read word line, power supply, and ground are provided, and the NOR circuit is constituted by three Nch transistors as shown in FIG. Is what you do.

In the second embodiment, a memory cell group composed of dynamic memory cells, a write bit select line output from a bit decoder, a write word select line output from a word decoder, a bit select line and a word select line The NOR circuit to control, the output of the NOR circuit,
And a write word line connected to a write access transistor of the memory, that is, a write word line, a write bit line that transmits input data to a memory cell, a read bit line that transmits data from the memory cell to an output. And a read word line output from a word decoder, that is, a read word line, power supply, and ground. As shown in FIG. 6, the NOR circuit includes two Nch transistors and one resistor. It is a feature.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 shows a peripheral circuit of a memory cell of a semiconductor memory device according to the present invention. In FIG. 1, reference numeral 300 denotes a memory cell group including dynamic memory cells 100, 1 denotes a bit selection line, 2 denotes a word selection line, and 200 denotes a NOR which controls signals on the bit selection line 1 and the word selection line 2.
Circuit 3, a write word line for performing a write operation with the output of the NOR circuit, that is, a write word line, 4.6, a write bit line, that is, a write bit line, 5.7, a read bit line, that is, a read bit line, That is, it is a read word line.

FIG. 2 shows a dynamic memory cell 100.
FIG. In FIG. 2, 21 is a write access transistor, 22 is a charge storage capacitance, 23 is a read bit line drive transistor,
24 is a read access transistor, 25 is a write bit line or write bit line, 26 is a write word line or write word line, 27 is a read word line or read word line, and 28 is a read bit line or read bit line.

FIG. 3 shows a selection operation by the bit decoder and the word decoder. When a write address is selected, as shown in FIG. 3, writing is performed only at an address crossed by the bit decoder and the word decoder. Is controlled by the NOR circuit 200.

FIG. 4 is a circuit diagram of the NOR circuit. 51
52 and 53 are Nch transistors, 54 is a bit select line, 55 is a word select line, and 56 is a write word line, that is, a write word line.

The operation of the semiconductor memory device thus configured according to the present embodiment will be described. First,
Data writing is performed when the bit selection line 54 and the word selection line 55 are both selected.
1 and 52 are turned on, the write word line, that is, the write word line 56 is charged to H level, and the write access transistor 21 (FIG. 2) of the memory is opened.

Here, transistors 51 and 52 are Nch
Since it is constituted by a type transistor, it is possible to realize a smaller area than before in the case where the charging speed to the write word line, that is, the write word line 56 is made equal to that in the conventional case.

Next, when the write address is not selected,
Either the bit selection line 54 or the word selection line 55 is deselected, the Nch type transistors 51 or 52 are turned off, and the charge of the write word line, that is, the write word line 56, is constantly turned on.
And the write transistor 21 (FIG. 2) of the memory is turned off.

Here, in order to make the discharge speed of the write word line, that is, the write word line 56 equal to that in the related art,
The channel width of the Nch transistor 53 is set to Nc in FIG.
It is necessary to be the same as two of the h-type transistors 33 and 34, but by using only one Nch-type transistor, which has conventionally been constituted by two, it is possible to realize a smaller area. .

FIG. 6 is a layout diagram of a NOR circuit according to this embodiment, and FIG. 9 is a layout diagram of a conventional NOR circuit. As described above, the area is significantly reduced as compared with the conventional example, and the effect of reducing the chip area is further increased in the case of a large-capacity memory.

Embodiment 2 FIG. 1 shows a peripheral circuit of a memory cell of a semiconductor memory device according to the present invention. In FIG. 1, reference numeral 300 denotes a memory cell group composed of dynamic memory cells 100, 1 denotes a bit select line, 2 denotes a word select line, 200 denotes a NOR circuit controlling signals on the bit select line 1 and the word select line 2, 3 Is a write word line that performs a write operation at the output of the NOR circuit, that is, a write word line;
4 and 6 are write bit lines, that is, write bit lines;
7 is a read bit line or read bit line, and 8 is a read word line or read word line.

FIG. 2 shows a dynamic memory cell 100.
FIG. In FIG. 2, 21 is a write access transistor, 22 is a charge storage capacitance, 23 is a read bit line drive transistor,
24 is a read access transistor, 25 is a write bit line or write bit line, 26 is a write word line or write word line, 27 is a read word line or read word line, and 28 is a read bit line or read bit line.

FIG. 5 is a circuit diagram of the NOR circuit. 61
62 is an Nch transistor, 63 is a resistor made of polysilicon or the like, 64 is a bit select line, 65 is a word select line, and 66 is a write word line, that is, a write word line.

The operation of the semiconductor memory device thus configured according to the present embodiment will be described. First,
When writing data, when both the bit selection line 64 and the word selection line 65 are selected, the Nch transistors 61 and 62 are turned on, and the write word line, that is, the write word line 66 is charged to the H level, and the memory write operation is performed. By opening the access transistor 21 (FIG. 2). Here, since the transistors 61 and 62 are constituted by N-channel transistors, it is possible to reduce the area required for charging the write word line, that is, the write word line 66, to be equal to that of the related art with a smaller area. .

Next, when the write address is not selected,
Either the bit select line 64 or the word select line 65 becomes unselected, the Nch-type transistor 61 or 62 is turned off, and the charge of the write word line, that is, the write word line 66 is pulled down to the L level through a resistor, and This is performed by turning off the writing transistor 21 (FIG. 2). Here, even if the discharge speed of the write word line, that is, the write word line 66 is made equal to that of the related art, it is possible to realize a smaller area than the related art.

FIG. 7 shows a layout diagram of the NOR circuit in this embodiment. in this way,
The area is greatly reduced as compared with the conventional example in which the layout diagram of the NOR circuit is shown in FIG. 9, and in the case of a large capacity memory, the effect of reducing the chip area is further increased.

[0040]

According to the first aspect of the present invention, the first and second memory cells, which are connected between the write word line and the ground portion and are always in a conductive state when a power supply is applied, are controlled by the bit select line and the word select line. By providing a discharging element for discharging the charge of the write word line in response to one off operation of the second control element, the NOR circuit including the first and second control elements and the discharging element can be simplified, and a large capacity can be obtained. Thus, a semiconductor memory device which can be implemented can be obtained.

According to the second aspect, the first and second control elements and the discharging element are constituted by transistors, and the NOR circuit comprising the first and second control elements and the discharging element can be simplified. As a result, a semiconductor memory device capable of increasing the capacity can be obtained.

According to the third aspect, the gate of the transistor constituting the discharging element is connected to the power supply, the source is connected to the ground, and the drain is connected to the write word line. N consisting of control element and discharge element
A semiconductor memory device in which the OR circuit can be simplified and the capacity can be increased can be obtained.

According to the fourth aspect, the transistor constituting the discharge element is an N-channel transistor.
A NOR circuit including the first and second control elements and the discharging element can be simplified, and a semiconductor memory device capable of increasing the capacity can be obtained.

According to the fifth aspect, the first and second control elements are constituted by transistors, and the discharge element is constituted by resistors, and are constituted by the first and second control elements and the discharge element. The NOR circuit can be simplified,
It is possible to obtain a semiconductor memory device capable of increasing the capacity.

According to the sixth aspect, one end of the resistor constituting the discharge element is connected to the ground, and the other end is connected to the write word line, so that the first and second control elements and the discharge element are connected. , And a semiconductor memory device capable of increasing the capacity can be obtained.

According to the seventh aspect, the first and second control elements are constituted by N-channel transistors,
And NO composed of the second control element and the discharging element
A semiconductor memory device in which the R circuit can be simplified and the capacity can be increased can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a memory cell peripheral circuit of a semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing a memory cell of the semiconductor memory device according to the present invention.

FIG. 3 is an explanatory diagram showing an operation of selecting a write address by a bit decoder and a word decoder according to the present invention.

FIG. 4 is a circuit diagram showing a NOR circuit according to one embodiment of the present invention.

FIG. 5 is a circuit diagram showing a NOR circuit according to another embodiment of the present invention.

FIG. 6 is a layout diagram of a NOR circuit according to one embodiment of the present invention;

FIG. 7 is a layout diagram of a NOR circuit according to another embodiment of the present invention.

FIG. 8 is a circuit diagram showing a NOR circuit in a conventional example.

FIG. 9 is a layout diagram of a NOR circuit in a conventional example.

[Explanation of symbols]

100 memory cells, 300 memory cell group, 1 bit select line, 2 word select line, 200 NOR circuit, 3
Write word line, that is, write word line, 4.6
Write bit line or write bit line, 5.7 read bit line or read bit line, 8 read word line or read word line, 21 write access transistor, 22 charge storage capacitance, 23 read bit line drive transistor, 2
4 read access transistor, 25 write bit line or write bit line, 26 write word line or write word line, 27 read word line or read word line, 28 read bit line or read bit line, 31 • 32 Pch transistor, 33 • 34 Nch type transistor, 35 bit select line, 36 word select line, 37 write word line or write word line, 51, 52, 53 Nch type transistor, 54 bit select line, 55 word select line, 56 write word line or write word line ,
61/62 Nch type transistor, 63 resistor, 64
Bit select line, 65 word select line, 66 write word line, that is, write word line.

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[Procedure amendment]

[Submission date] November 19, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 1

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claim 3

[Correction method] Change

[Correction contents]

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] Claim 6

[Correction method] Change

[Correction contents]

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction contents]

According to a third aspect of the present invention, the first and second control elements are connected by connecting a gate of a transistor constituting a discharging element to a power supply, connecting a source to a ground portion, and connecting a drain to a write word line. and constituting the discharge element
Simplify the NOR circuit by, it is intended to obtain a semiconductor memory device capable of high capacity.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction contents]

[0016]

According to a first aspect of the present invention, there is provided a semiconductor memory device including a memory cell group including a plurality of dynamic memory cells and a read for transmitting a signal read from the memory cell group to an output. A bit line, a write bit line for writing input data to the memory cell group, a write word line for controlling writing to the memory cell, a read word line for controlling reading from the memory cell, A bit selection line for selecting a bit line, a word selection line for selecting the write word line, and a write control circuit that receives the bit selection line and the word selection line as inputs and outputs a write word line. A semiconductor memory device comprising a line memory provided with a write control circuit, wherein the write control circuit is controlled by a bit select line. A control element is controlled by said word select line, and a second control element connected between the write word line and a first control element in series with the first control element, said write word line Between the first and second control elements controlled by the bit select line and the word select line, and the write word line is connected between the first and second control elements. And a discharge element for discharging the electric charge of

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction contents]

In the semiconductor memory device of the third invention,
A memory cell group including a plurality of dynamic memory cells, a read bit line for transmitting a signal read from the memory cell group to an output, and a write bit line for writing input data to the memory cell group; A write word line for controlling writing to the memory cell, a read word line for controlling reading from the memory cell,
A bit selection line for selecting the write bit line;
A word selection line for selecting the write word line;
In a semiconductor memory device including a line memory including a write control circuit that inputs the bit select line and the word select line and outputs a write word line, the write control circuit is controlled by the bit select line. 1 control element and the word select line, and the write word line and the first control element are connected in series with the first control element .
A second control element connected between the control element and a discharge element connected between the write word line and a ground, and a transistor constituting the discharge element of the write control circuit is , The gate is connected to the power supply, the source is connected to the ground, and the drain is connected to the write word line.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction contents]

In the semiconductor memory device of the sixth invention,
A memory cell group including a plurality of dynamic memory cells, a read bit line for transmitting a signal read from the memory cell group to an output, and a write bit line for writing input data to the memory cell group; A write word line for controlling writing to the memory cell, a read word line for controlling reading from the memory cell,
A bit selection line for selecting the write bit line;
A word selection line for selecting the write word line;
In a semiconductor memory device including a line memory including a write control circuit that inputs the bit select line and the word select line and outputs a write word line, the write control circuit is controlled by the bit select line. 1 control element and the word select line, and the write word line and the first control element are connected in series with the first control element .
A second control element connected between the write element and a ground element, and a second control element connected between the write word line and the grounding part; , One end of which is connected to the ground portion, and the other end of which is connected to the write word line.

Claims (7)

[Claims] A memory cell group including a plurality of dynamic memory cells; a read bit line for transmitting a signal read from the memory cell group to an output; and a read bit line for writing input data to the memory cell group. A write bit line, a write word line for controlling writing to the memory cell, a read word line for controlling reading from the memory cell, a bit selection line for selecting the write bit line, and the write word line. A semiconductor memory device comprising a line memory including a word select line for selecting a line, and a write control circuit that receives the bit select line and the word select line as inputs and outputs a write word line; A first control element controlled by the bit select line and a first control element controlled by the word select line. A second control element connected in series with the first control element between the write word line and the power supply; and a second control element connected between the write word line and the ground portion, and is always in a conductive state when a power supply is applied. A discharge element for discharging a charge on a write word line in response to an off operation of one of first and second control elements controlled by the bit select line and the word select line. . 2. The semiconductor memory device according to claim 1, wherein the first and second control elements and the discharging element are constituted by transistors. 3. A memory cell group including a plurality of dynamic memory cells, a read bit line for transmitting a signal read from the memory cell group to an output, and a read bit line for writing input data to the memory cell group. A write bit line, a write word line for controlling writing to the memory cell, a read word line for controlling reading from the memory cell, a bit selection line for selecting the write bit line, and the write word line. A semiconductor memory device comprising a line memory including a word select line for selecting a line, and a write control circuit that receives the bit select line and the word select line as inputs and outputs a write word line; A first control element controlled by the bit select line and a first control element controlled by the word select line. A second control element connected in series with the first control element between the write word line and a power supply; and a discharge element connected between the write word line and a ground portion. A semiconductor memory device, wherein a transistor constituting a discharge element of a control circuit has a gate connected to a power supply, a source connected to a ground portion, and a drain connected to a write word line. 4. A transistor constituting a discharging element,
4. The semiconductor memory device according to claim 2, wherein the transistor is an N-channel transistor. 5. The semiconductor memory device according to claim 1, wherein the first and second control elements are constituted by transistors, and the discharging elements are constituted by resistors. 6. A memory cell group comprising a plurality of dynamic memory cells, a read bit line for transmitting a signal read from the memory cell group to an output, and a memory for writing input data to the memory cell group. A write bit line, a write word line for controlling writing to the memory cell, a read word line for controlling reading from the memory cell, a bit selection line for selecting the write bit line, and the write word line. A semiconductor memory device comprising a line memory including a word select line for selecting a line, and a write control circuit that receives the bit select line and the word select line as inputs and outputs a write word line; A first control element controlled by the bit select line and a first control element controlled by the word select line. A second control element connected in series with the first control element between the write word line and a power supply; and a discharge element connected between the write word line and a ground portion. A semiconductor memory device characterized in that one end of a resistor constituting a discharge element of a control circuit is connected to a ground portion, and the other end is connected to a write word line. 7. The semiconductor memory device according to claim 2, wherein said first and second control elements are constituted by N-channel transistors.