JPH10105412A - Object generation method for realizing efficient access to main storage - Google Patents

Abstract

(57) [Summary] [PROBLEMS] When a data area accessed in a loop in a program exceeds a cache capacity, a DRAM,
An object for efficiently accessing the main memory created by the SDRAM is generated. When a data area accessed in a loop exceeds a cache capacity and has a data dependence that can be vectorized, an object sequence that implements the same processing as a vector instruction by a plurality of scalar instructions using a vector register is used. Generate. [Effect] Compared with the method of accessing array references in a loop on average, a small number of arrays can be accessed intensively, the probability of accessing a plurality of elements with the same RAS address is increased, and efficient data access is realized. You.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for generating objects in a program for performing instruction level parallel processing, and more particularly to a method for generating an object suitable for a loop in a case where data accessed by the program is large and cannot be stored in a cache. .

[0002]

2. Description of the Related Art As one direction of a supercomputer, a parallel processing system using a scalar processor as a node processor is considered promising. Parallel supercomputers using scalar processors are expected to be improved by improving the clock frequency due to advances in semiconductor technology, and by realizing instruction-level parallel processing such as the superscalar method that makes effective use of multiple arithmetic units that can execute in parallel. The processing performance of the processor is dramatically improved.

However, its high scalar processor throughput is only achieved when the cache memory works effectively. In large-scale scientific and technical calculations, the data cache often does not work effectively because of the property that the data area is large and the locality of data is small. In that case,
The performance of the scalar processor is greatly reduced due to the main memory access penalty. Nakazawa, Nakamura, Park "Architecture of Massively Parallel Computer CP-PACS" Information Processing Vo
l. 37, no. 1, 1996; In Nos. 18 to 28, the concealment of the main memory access penalty was realized by a pipeline of the main memory access by using multiple banks of the main memory, a large number of registers, and a function of preloading the registers.

[0004]

With only the above-mentioned prior art, there is a problem that if the performance of the CPU of the scalar processor is improved in the future, it becomes impossible to secure a main storage bandwidth suitable for the operation. For example, if the frequency is 150 MHz,
One load instruction can be issued in one cycle, and the main memory is DR
Consider a computer having a 16-bank configuration based on AM. When the array in the loop is continuously accessed, if the cycle time of the element of the main memory is 106 ns (16/150) or less, the bandwidth of the main memory does not become a performance bottleneck. Current device cycle time is 100n
If it is s, it can be said that it is the last main memory bandwidth. However, it can be seen that the conventional approach has a limit, considering that the CPU performance can be improved at an annual rate of 50% to 100%, while the DRAM performance improvement is 10% or less.

There is a page mode as a method for improving the performance of a DRAM. Accessing a DRAM consists of two stages: a RAS access specifying the upper half of the address and a CAS access specifying the lower half of the address. The page mode is a high-speed mode in which a reference to the same RAS address is not accessed by the RAS address, but only accessed by the CAS address. Recently, a high-speed device called an SDRAM has appeared. This is an element improved so that data of the same RAS address can be accessed at one cycle pitch. In order to take advantage of these properties, data whose addresses are close to each other must be
It is necessary to process within a close time so that the address is not switched.

Here, consider a case in which there are n consecutive access references of an array in a loop in a loop process by a conventional scalar processor. One sequence reference A (I), I =
1,2. . , After one array reference A (1), A (2) is referenced in the next loop iteration. A
Since (1) and A (2) have the same RAS address, they should be able to be accessed efficiently. However, since n-1 data accesses for other arrays occur during one loop processing, RAS It is very likely that addresses will switch. That is, the conventional loop processing method has a problem that the page mode of the DRAM and the properties of the SDRAM cannot be utilized.

[0007] An object of the present invention is to provide a DRAM, when a data area accessed in a loop exceeds a cache capacity.
It is an object of the present invention to provide an object generation method for efficiently accessing a main memory made of an SDRAM.

[0008]

The object of the present invention is to execute the same processing as the vector instruction when the data area accessed in the loop exceeds the cache capacity and has a data dependence that can be vectorized. No. 249,594 “Processor having register configuration suitable for parallel execution control of loop processing” by generating a code realized by a plurality of scalar instructions using a multi-element register (vector register) and its control mechanism invented. Achieved.

This is because in vector processing, since a small number of arrays are intensively accessed, the probability of accessing a plurality of elements with the same RAS address is higher than in the conventional method.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a compiler according to the present invention.

Before describing the present invention, the relationship between instructions and registers of the architecture disclosed in Japanese Patent Application No. 8-249594, which is premised on the compiler of the present invention, will be briefly described with reference to FIG. . The instruction includes an operation code 150 and an operand field 151. The operand includes one write operand and two read operands. Each operand includes a register type flag 152 and a logical register number 153. Register type flag 1
When 52 is 0, it represents a normal scalar register, and when the register type flag 152 is 1, it is a vector register.

The operation when the vector register is specified will be described below. Each logical register number has a corresponding write pointer group 154 and a corresponding read pointer group 155. The mapping between the logical register number specified by the instruction and the vector register which is the actual large-capacity physical register file 170 is indicated by the write pointer corresponding to the specified logical register number 157 in the case of the write-side register. In the case of a read-side register, it indicates an element 161 indicated by a read pointer corresponding to a specified logical register number 160.
After reading the register, the read pointer is set, and after writing the register, the write pointer is set to 15
It is automatically updated by 9 and 162, and has the structure of a vector register that automatically accesses the register of the next element at the next access.

At the time of automatic updating, the pointer indicating the end of the register file is wrapped around so as to point to the beginning of the register file as indicated by 169. The initial value of the pointer is set by an immediate (or register) assignment instruction, with the read / write pointer values being the same value.

FIG. 1 shows the structure of the entire compiler. FIG.
Is converted into an intermediate language by the syntax analysis 2, and using the input as an input, the optimizing unit 3 which determines whether the data is in the cache or the main memory and performs the optimal program conversion is converted into the intermediate language 4. I do. Then, the code generation unit 5 converts the object code 6 into the object code 6 for the target machine. The present invention relates to 3 and 5, and relates to improving the execution efficiency of the object code 6.

FIG. 2 shows the structure of a part of the optimizing unit 3 shown in FIG. 1 which is related to optimization for efficient data access. As the source program 1 input in FIG. 2, the FORTRAN program in FIG. 5 will be described as an example. Reference numerals 30 and 31 in FIG. 5 indicate loops, which constitute a double loop. FIG. 2 performs the following processing on such a program to convert it into an intermediate language 4.

The processing of FIG. 2 sequentially processes the innermost loop in the source program. The judgment 10 judges whether or not the main storage target directive described by the user in the program exists in the loop. The main storage target directive is specified by the user immediately before the loop on the source program as described below when the probability that data exists in the cache is low. In this case, as described later, a conversion process 1 of the loop into a vector instruction
Go to 5.

* OPTION MEMTARGET DO 31 I = 1, L In the source program of FIG. 5, since there is no such designation in DO 31, the process proceeds to the access data amount calculation processing 11 of the target loop. The process 11 calculates the data amount to be accessed in the loop from the inner loop to the source program in FIG. That is, first, the innermost loop 31
Then, the arrays A32, 33 and B34 have the loop index I
Is a subscript, L elements of the loop length are required, and the array C35 accesses only one element because it is an invariant subscript in the loop.

Accordingly, the total number of elements is 2 * L + 1, and in the case of double precision data, it is (2 * L + 1) * 8 bytes. Similarly, in the loop 30, since the loop index K newly changes from 1 to M, the array A32,
33 is similar to loop 31, but array B34 is M * L
And the number of arrays C35 is M. Accordingly, (L
+ L * M + M) * 8 bytes of data.

At decision 12, the process branches to the following three processes based on the access data capacity of the target loop obtained at process 11.

First, when it is determined that the amount of access data is smaller than the cache capacity, normal software pipeline processing is performed on the assumption that data exists in the cache, so that the intermediate language is not changed.

Second, when it is determined that the access data amount is larger than the cache capacity, it is determined whether or not the loop can be vectorized. If the loop can be vectorized, the loop is converted into a vector intermediate language. Perform 15.
If vectorization cannot be performed, normal software pipeline processing is performed, and the intermediate language is not changed. The determination 13 as to whether or not to vectorize is to check whether vector processing-like data processing is possible from the data dependency.
Well-known Tanaka and Iwasawa, "Compilation Techniques for Vector Computers," Information Processing, Vol. 31, No. 6, pp.
736-743, 1990 and the like.

Third, the relationship between the amount of access data and the cache capacity is unknown. In the case of the program in FIG.
The access data amount is (L + L * M + M) * 8 bytes, but this is applicable because L and M are variables and their sizes are unknown at the time of compilation. At this time, it is determined whether or not the loop can be vectorized. If the loop can be vectorized, an intermediate language as shown in 16 is generated. That is, when the condition 36 when the access data amount is smaller than the cache capacity is satisfied, the normal software pipeline processing is performed on the assumption that data exists in the cache. If the access data amount is larger than the cache capacity, the data is converted into a vector intermediate language as shown in sentences 37 to 42.

Here, VLENG 37 is a vector intermediate language for setting a processing length for performing vector processing, VLD VTE
MP1, B (1: L, K) 38 are vector data B
(I, K) I = 1, 2,. . . , L into the vector register VTEMP1, VEMD, VEMD
VTEMP2, VTEMP1, C (K, J) 39 are a vector register VTEMP1 and scalar data C (K, J).
, And the result is stored in a vector register VTEM.
Vector intermediate language stored in P2, VLD VTEMP
3, A (1: L, J) 40 is vector data A (I,
J) I = 1, 2,. . . , L to the vector register VTE
VEADVTEM, a vector intermediate language to load into MP3
P4, VTEMP2, and VTEMP3 41 perform vector addition of the vector register VTEMP2 and the vector register VTEMP3, and store the result in the vector register VTEMP.
4, and the intermediate language stored in VST4 and VSTD VTE
MP4, A (1: L, J) 42 are vector registers VT
The data on EMP4 is stored in data area A (I, J) I =
1, 2,. . . , L stored in the vector intermediate language.

Next, a vector processing code generation method according to the present invention in the code generation unit 3 of FIG. 1 is shown in FIGS. FIG. 3 illustrates the operation when the vector instructions 37 to 42 in FIG. 5 are input. The vector instructions 37 to 4 shown in FIG. 6 are first executed by the instruction rearranging process 20 so that the vector instructions can be executed in the order most suitable for the hardware.
2 (the vector instructions 39 and 40 are exchanged). The method of rearranging instructions is described in the well-known document Mike Johnson "Super Scalar Processor" Nikkei B
P Publishing Center 1994, pp. The list scheduling method described in 190-193 may be applied.
Here, it is assumed that two memory operation units and two floating point operation units can be executed simultaneously.

In decision 21, it is decided whether the loop length is a variable or a constant. Since the loop length is L and a variable from the intermediate language 37, the process proceeds to processing 22. Process 22 selects a register configuration.
If the number of registers is 512, two vector registers of 256 elements, four sets of vector registers of 128 elements, eight sets of vector registers of 64 elements, sixteen sets of vector registers of 32 elements, and the like are selected. In this case, as described later, it is important to select a register element length that is substantially equal to the load latency. As a result, when the load latency is 50, the vector instruction 38
Since the required number of registers is 4 for .about.42, a register configuration of eight sets of 64-element vector registers is selected.

If the loop length is determined to be a constant as shown in the following example, the register length is selected in process 24 as long as the register capacity permits. In the following example, when the number of necessary registers is 4, a configuration of four sets of 128-element vector registers is selected.

DO 31 I = 1,1000 Processing 23 performs strip mining processing based on the element length of the selected register. The vector intermediate language 37 of FIG.
For 42, since the element length of the register is 64, the program is converted so that the vector processing length is 64 or less as shown at 50 to 68 in FIG. As a result, two vector intermediate word strings are generated. That is, the vector length is a vector intermediate word sequence 52 to 60 having a register length, and the vector length is a vector instruction sequence 61 to 68 having a fractional length. FIG.
, The former vector instruction sequence has a loop length of 64, and the latter vector intermediate sequence has a loop length of less than 64. Note that even though the original loop length is a variable, the former loop length is a constant. It is also apparent that when the original loop length is a constant, the vector length of the latter loop is also a constant.

Since the vector intermediate word strings 55 to 60 having a register length of the vector length in FIG. 6 have a constant vector length, the execution state is estimated by simulating the vector instruction corresponding to the vector intermediate word. Vector intermediate string 56 ~
Obviously, the vector instruction corresponding to 60 can simulate the execution status if hardware is provided. If there are two arithmetic units capable of simultaneously executing the load store instruction and two floating point arithmetic units capable of simultaneously executing the load store instruction, the state of the execution is as shown in FIG. Here, it is assumed that the load latency is 50 and the operation latency is 3. That is, an instruction using the result of the load instruction can start execution with a delay of 50 cycles, and an instruction using the result of the operation instruction can start execution with a delay of three cycles.

In step 27, the time at which the combination of simultaneously executed vector instructions is changed is obtained. In the example of FIG. 7, the black circle points indicate the time, and the sections a, b, c, d, and
e and f are divided into six.

In process 28, based on the change points obtained in process 27, a program conversion for implementing a code by scalar processing of vector execution is performed for each section between the change points. FIG. 8 shows the converted code. MSPTR130 ~
133 denotes four vector registers Q1, Q2, Q
3, indicates the initial offset from the 0th element of Q4, and indicates that each register is used as 64 elements.

Section a is a section in which two vector load instructions are simultaneously executed, and is a scalar intermediate language LDU 136, 137.
The same processing can be realized by generating an intermediate language that executes the process 50 times. Loop processing is scalar intermediate language 134,13
The loop can be realized at 5, 138. Here, the scalar intermediate language 134 sets the number of processing loops in the count register CTR. Scalar intermediate language 138 is CTR
If the content of CTR is 0 or more, the process branches to label label1 and decrements the content of CTR by one. The scalar intermediate language LDU 136, 137 is an intermediate language corresponding to a normal load instruction with address update. When the processes 134 to 138 are executed, the pointer is advanced by one when referring to the register, so that B (I1, K), B (I1 + 1, K),. , B (I
1 + 49, K) is stored in the twelfth vector register.
From the 8th element to the 177th element, A (I1, J), A (I1
+1, J),. , A (I1 + 49, J).

The section b is a section in which two vector load instructions and one vector multiplication instruction are executed.
DU141, 142, 3 scalar intermediate FMUL143
The same processing can be realized by generating an intermediate language to be executed twice. Here, FMUL is an intermediate language corresponding to a scalar multiplication instruction. As a result, B (I1 + 50, K) and B (I1 +
51, K) and B (I1 + 52, K) are transferred from the 178th element to the 180th element of the vector register by A (I
1 + 50, J), A (I1 + 51, J), A (I1 + 5
2, J) is stored in the sixth register of the vector register.
The result obtained by multiplying the contents of the 0th element to the 2nd element of the vector register by C (K, J) is stored from the 4th element to the 66th element.

Section c is a section in which two vector load instructions, one vector multiplication instruction and one vector addition instruction are executed, and scalar intermediate languages LDU147 and 148, scalar intermediate language FMUL149 and scalar intermediate language FADD150 are executed 11 times. The same processing can be realized by generating an intermediate language. Here, FADD is an intermediate language corresponding to a scalar addition instruction. As a result, the 53rd of the vector register
From the element to the 63rd element, B (I1 + 53, K), B (I
1 + 54, K),. . , B (I1 + 63, K) are transferred from the 181st element to the 191st element of the vector register by A (I1 + 53, J), A (I1 + 54,
J),. . , A (I1 + 63, J) are stored, and the 67th element to the 77th element of the vector register are
The contents of the third to thirteenth elements of the vector register and C
The result of multiplication by (K, J) is stored, and the contents of the 0th to 10th elements of the vector register and the contents of the 128th element to the 138th element of the vector register are stored from the 192nd element to the 202nd element of the vector register. The result of multiplying the contents is stored.

The section d is a section in which one vector multiplication instruction, vector addition instruction, and vector store instruction are executed, and the scalar intermediate language FMUL154 and the scalar intermediate language FADD15 are executed.
5. The same processing can be realized by generating an intermediate language that executes the scalar intermediate language SDU 156 50 times. Where S
DU is an intermediate language corresponding to a normal scalar store instruction with address update. As a result, the 78th of the vector register
The result obtained by multiplying the contents of the 14th to 63rd elements of the vector register by C (K, J) is stored in the 127th element from the element, and the 2nd element is stored in the second element from the 203rd element of the vector register.
The 52nd element is the 11th element to the 60th element of the vector register.
Element contents and first to 139th elements of the vector register
The result of multiplying the contents of the 88 elements is stored, and the values of the 192nd element to the 241st element of the vector register are stored in the data area A
(I1, J), A (I1 + 1, J),. . , A (I1 +
49, J).

Section e is a section where one vector addition instruction and one vector store instruction are executed, and is a scalar intermediate language FADD.
160, the same processing can be realized by generating an intermediate language that executes the scalar intermediate language SDU 161 three times. As a result, the result obtained by multiplying the contents of the 61st to 63rd elements of the vector register and the contents of the 189th element to the 191st element of the vector register is stored in the 253rd element to the 255th element of the vector register. Second
The value of the 42nd element to the 244th element is the data area A (I1 +
50, J), A (I1 + 51, J), A (I + 52,
J).

The section f is a section where one vector store instruction is executed, and the same processing can be realized by generating an intermediate language that executes the scalar intermediate language SDU 165 11 times. As a result, the values of the 245th element to the 255th element of the vector register are stored in the data areas A (I1 + 53, J) and A (I1 +
54, J),. . , A (I1 + 63, J).

Next, in the vector intermediate word strings 64 to 68 having a fractional vector length shown in FIG. 6, since the vector length is a variable, the corresponding vector instruction in the processing 26 is arranged in the chain slot to execute the vector instruction. Simulate. As shown in FIG. 9, a chain slot is obtained by collecting and grouping vector instructions that can be executed in parallel. Two arithmetic units that can execute load store instructions simultaneously,
If there are two floating point arithmetic units that can be executed simultaneously, a plurality of four slots 110 to 113 are arranged in the time axis direction until instructions are filled in the time axis direction. The corresponding vector instruction is placed in the chain slot under the condition shown at 26. In the case of the vector intermediate word strings 64-68, they are arranged as shown in FIG. Since the time slot 1 (114) has only load instructions that can be executed in parallel, the execution time of the chain slot is I2-I1 + 1 cycles, and the execution time of the time slot 2 (115) is that three instructions have a flow dependency. Therefore, if the operation latency is 3,
I2−I1 + 1 + 2 * 3 cycles.

In step 27, the time at which the combination of simultaneously executing vector instructions is changed for each time slot is determined. In the vector intermediate word strings 64 to 68 in FIG. 6, the points of black circles indicate the time, and the sections a, b, c, d, e, and f
Is divided into six.

In process 28, based on the change points obtained in process 27, program conversion for code generation by scalar processing of vector execution is performed for each section between the change points. If this conversion is performed in the same manner as in the case of the vector intermediate language strings 56 to 60, as a result, the vector processing by the scalar intermediate language of FIG. 10 can be realized.

Here, when the vector length is a variable, the reason for estimating the parallel execution status of the vector instruction by the concept of a chain slot, and the fact that a vector instruction having a flow dependency with a vector load instruction is separated into another chain slot. The reason for arranging is described below. When the vector length is a variable, the optimal parallel execution status for the vector intermediate word strings 64-68 is different from that estimated in FIG. If the loop length is 64, the load latency is 50 cycles,
When the operation latency is 3, as described above, FIG.
It is best to execute as follows. However, in this case, when the optimum execution situation is estimated, the number of combinations of the parallel execution situations becomes polynomially large depending on the number of instructions, the instruction execution latency, the instruction appearance pattern and the loop length. Generation is not possible. For this reason, when the loop length is large, the number of combinations is reduced using the concept of a chain slot in which mainly overlapping instructions are grouped.

That is, since the operation latency is generally low and the main storage latency is high, the operation instruction and the instruction using the result are placed in the same chain slot or thereafter, and the load instruction and the operation instruction using the same are placed in separate chain slots. It is realized by placing. Further, when selecting a register configuration, by selecting a register configuration close to the main storage latency, the execution of a load instruction and an operation instruction using the same can be optimized. If the loop length is large and strip mining is performed several times, it is ideal except for the final strip mining.

For the sake of simplicity, the code shown in FIG. 10 does not operate correctly when the loop length is 6 or less. For example, if the actual loop length is 1
At the time of, VEMD58, VEAD59, VSTD60
Are not executed at the same time, and the number of sections is three. In order to make the code operate correctly, it is necessary to add a branch for skipping the processing based on the loop length in the code portions of the sections b, c, e, and f.

[0043]

According to the object generating method of the present invention,
In the case where the data area accessed in the loop exceeds the cache capacity and has a data dependency that can be vectorized, a code that realizes the same processing as the vector instruction by a plurality of scalar instructions using a vector register can be generated. When this object sequence is executed, the probability of accessing a plurality of elements with the same RAS address increases, since a small number of arrays are intensively accessed compared to the conventional method of accessing array references in a loop on average. Efficient access to data is achieved. FIG. 12 shows an example of the effect. This figure shows the execution efficiency of the generated code for the kernel loop of the LU decomposition source program. The circles indicate the performance based on the code generated assuming that the data is in the cache. The black circles indicate the performance based on the scheduling by the conventional software pipeline assuming that the data is in the main memory. This shows the performance of the code that implements the same processing as in the scalar instruction. The cache target code shows high execution performance while the array is small and exists in the cache. In the conventional code scheduled in consideration of the main storage latency, the RAS miss of the SDRAM occurs and the performance is not generally high. In a code that realizes the same processing as vector processing by a scalar instruction assuming that data is in main memory, R
Since AS misses can be reduced, efficient execution can be achieved in a large area of the array.

Therefore, when the access data area described in the present invention is smaller than the cache capacity, the conventional loop scheduling code targeting the cache is used. When the access data area exceeds the cache capacity, the vector processing access is performed. By generating the code realized by the scalar instruction, efficient execution performance can always be realized as shown by the thick black line in the figure.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an entire compiler.

FIG. 2 shows an optimization unit for efficient access of data in a compiler.

FIG. 3 shows a vector processing code generation method 1 in a compiler.

FIG. 4 shows a vector processing code generation method 2 in a compiler.

FIG. 5 is an example after conversion relating to efficient access of a source program and data to the source program.

FIG. 6 is an example in which strip mining is applied to a vector intermediate language.

FIG. 7 is an explanatory diagram of a result of a simulation of a vector instruction when a vector processing length is a constant.

FIG. 8 is an example of a code sequence for implementing vector processing by a scalar instruction sequence when the vector processing length is a constant.

FIG. 9 is an explanatory diagram of a simulation result of a vector instruction when a vector processing length is a variable.

FIG. 10 is an example of a code sequence for implementing vector processing by a scalar instruction sequence when the vector processing length is a variable.

FIG. 11 is an explanatory diagram of an instruction and a register configuration of a prerequisite architecture.

FIG. 12 is an explanatory diagram of an effect.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Source program 2 Syntax analysis part 3 Optimization part 4 Intermediate language 5 Code generation part 6 Object code 150 Opcode 170 Physical register file.

Claims (10)

[Claims] 1. A method for compiling a source program into an object program, wherein a data area accessed by the loop part exceeds a cache capacity and has a data dependency that can be vectorized with respect to a loop part of the source program. In the object generation method, the same operation order as in the vector processing is realized by a scalar instruction. 2. A method for compiling a source program into an object program, wherein it is impossible to determine whether a data area accessed by the loop part exceeds a cache capacity for a loop part of the source program, and In the case of a data dependence relationship that can be vectorized, the code for calculating the size of the data access area and the size of the data access area and the cache capacity are compared with each other. An object generation method, comprising: generating a code realized by a scalar instruction and, when the cache capacity is smaller, a code of a scalar instruction in the same operation order as specified by the loop. 3. A compiler which reads a source program, performs syntax analysis, converts the intermediate program into an intermediate language, optimizes the intermediate language, and generates a code. For a loop portion, if the data area accessed by the loop portion exceeds the cache capacity and has a data dependency that can be vectorized, the intermediate portion of the loop portion is vectorized and converted into a vector intermediate language,
An object generation method, wherein the code generation unit converts the vector intermediate language into a scalar intermediate language in the same operation order as the execution of the vector intermediate language. 4. A compiler which reads a source program, parses the language, converts the language into an intermediate language, optimizes the intermediate language, and generates a code. If the data area accessed by the loop part cannot exceed the cache capacity and the loop part has a data dependency that can be vectorized, an intermediate part for calculating the size of the data access area is used. A word, an intermediate word for comparing the size of the data area with the cache capacity, and a vector intermediate word obtained by vectorizing the intermediate word of the loop part when the cache area is larger than the cache area. An intermediate language for executing the intermediate language of the loop is converted, and the code generator converts the intermediate language to a scalar intermediate language in the same operation order as the execution of the vector intermediate language. Object generation method which is characterized in that. 5. The object generating method according to claim 3, wherein at the time of converting the vector intermediate language into the scalar intermediate language, a simulation of an execution state of a vector instruction sequence corresponding to the vector intermediate language sequence is performed. Detecting a section where the combination of vector instruction sequences during parallel execution does not change, and converting a plurality of scalar intermediate words corresponding to the concurrently executed vector instructions into intermediate words that are repeatedly executed by loop processing for the number of cycles of the section. An object generation method characterized by the following. 6. The object generating method according to claim 4, wherein at the time of converting the vector intermediate language into the scalar intermediate language, a simulation of an execution status of a vector instruction sequence corresponding to the vector intermediate language sequence is performed. Detecting a section where the combination of vector instruction sequences during parallel execution does not change, and converting a plurality of scalar intermediate words corresponding to the concurrently executed vector instructions into intermediate words that are repeatedly executed by loop processing for the number of cycles of the section. An object generation method characterized by the following. 7. The object generating method according to claim 5, wherein in simulating the execution status of the vector instruction sequence corresponding to the vector intermediate word sequence, if the number of vector processes is a variable, the vector intermediate word sequence corresponds to the variable. An object generation method, wherein a vector load instruction and a vector instruction using a result stored in a vector register of the vector load instruction in a vector instruction sequence are scheduled so as not to be simultaneously executed. 8. The object generating method according to claim 6, wherein when simulating the execution status of the vector instruction sequence corresponding to the vector intermediate word sequence, if the number of vector processes is a variable, the vector intermediate word sequence corresponds to the variable. An object generation method, wherein a vector load instruction and a vector instruction using a result stored in a vector register of the vector load instruction in a vector instruction sequence are scheduled so as not to be simultaneously executed. 9. In the object generating method according to claim 3, when converting the vector intermediate language into the scalar intermediate language, if the vector processing length is a variable, the number of registers and the register length are the vector register configuration. Wherein the register length is set to a size close to the latency of the load vector instruction. 10. The object generating method according to claim 3,
When converting the vector intermediate language into the scalar intermediate language, if the vector processing length is a variable, in selecting the number of registers and the register length, which are the configuration of the vector register, set the register length to a value close to the latency of the load vector instruction. An object generation method characterized in that the object generation method is set to: