JPH0997494A - Semiconductor memory device - Google Patents

Abstract

(57) Abstract: In a semiconductor memory device using volatile memory cells, power consumption during refresh operation in a chip non-selected state is made extremely small, and battery backup for the refresh operation is possible. During a refresh operation, word line division control means 13 and 13 'respond to a signal of a main word line 6 by the word line division means 5 in response to a signal of a main word line 6 without depending on a decode signal. The word line dividing means 5 is controlled so that the word line dividing means 5 is selected, and the word line dividing control means 13 and 13 'are used for the word line dividing means 5 at the time of reading and writing of information.
Responds to the decode signal and the signal of the main word line 6 to control the word line dividing means 5 so that the corresponding divided word lines 7 and 7'are selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device using volatile memory cells, and more particularly to a MOS random access memory device capable of storing information by a battery.

[0002]

2. Description of the Related Art As a semiconductor memory device using a volatile memory cell, there is a dynamic type memory device or a pseudo static type memory device. Since these memory devices do not have a current supply means for statically holding information in the memory cells, the cell area can be reduced and they are suitable for high integration. (1985
IEE International Solid State Circus Conference (1985 IEEE Inte
rnational Solid-State Circuits Conference) February 15, 1985, pp. 250-251) (11th European Solid State Cir.
(Cuit Conference) September 16-18, 1985, pp. 139-146) However, in these memory devices, information cannot be refreshed with sufficiently low power, so that it is impossible to store information by a battery. .

[0003]

In the above conventional memory device, information reading (reading) and information writing (writing) are performed.
A so-called word line division technique in which only the minimum necessary word lines are activated, that is, the number of word lines is equivalently increased, in order to achieve low power consumption and high-speed operation in a chip selected state in which an operation is performed. Is used.

By the way, the power consumption P required to supply power to the bit line in the chip non-selected (standby) state in which the refresh (reproduction) operation of the information stored in the memory cell is performed.
_BP is expressed by the following equation.

P _BP = k · (ΔV _B / V _CC ) ² · C _BB · 2 ^N (1) where k is a constant, ΔV _B is the bit line voltage amplitude, V _CC is the power supply voltage, and C _BB is The bit line capacity per unit bit, N is the number of addresses required for word line selection (hence 2 ^N is the number of word lines). According to the above equation (1), the lead,
In order to satisfy the request during the write operation, the value of N must be increased, and therefore the power consumption during the refresh operation cannot be reduced to the extent that battery backup is possible.

In the above memory device, the lead,
In the chip selection state in which the write operation is performed, a so-called precharge period for charging the bit line within a fixed cycle time is required, so a power supply means to the bit line with large driving power, that is, large self-parasitic capacitance must be used. I have to.

On the other hand, in the chip non-selected state in which the refresh operation is performed, the cycle time is sufficiently long in the range where the information is not destroyed (100 times or more that in the chip selected state).
It is possible to However, in the conventional memory cell device described above, the same bit line power supply means is used regardless of whether the chip is selected or not selected. Therefore, the power for driving the bit line power supply means when the chip is not selected for refresh operation is used. There was a problem that could not be reduced.

The object of the present invention is to reduce the power consumption during the refresh operation in the chip non-selected state in the semiconductor memory device using the volatile memory cells as described above, and to enable the battery backup for the refresh operation. To do so.

[0009]

In order to achieve the above object, the semiconductor memory device of the present invention has a bit line, a first word line, and an intersection of the bit line and the first word line, respectively. A plurality of memory arrays each having a volatile memory cell that is provided and needs to be refreshed by a refresh operation; and a plurality of memory arrays arranged in parallel with the first word lines of the plurality of memory arrays. The main word line shared by the plurality of memory arrays and the first word line of the plurality of memory arrays are provided in correspondence with each other and are arranged outside the memory array, and the decode signal and the main word line are provided. Control signal in the refresh control signal line, and a plurality of word line dividing means for selecting the corresponding first word line in response to the signal of The word line division control means for receiving the word line division control means responds to the signal on the main word line in response to the signal on the main word line without the word line division means depending on the decode signal during the refresh operation. The word line dividing means is controlled so that the divided word lines can be selected, and at the time of reading or writing information, the word line dividing control means causes the word line dividing means to select the decode signal and the signal of the main word line. In response, the word line dividing means is controlled so as to select the corresponding divided word line.

Further, the volatile memory cell is composed of a memory cell having a self-amplifying function, and a bit line feeding means is provided between the bit line and the operating potential point.

Further, the memory cell having the self-amplifying function has a pair of MOSFs whose gates and drains are cross-connected.
ET and a pair of MOSFETs provided between the corresponding bit line and the drains of the pair of MOSFETs and having a gate connected to the corresponding first word line.

Further, the volatile memory cell is composed of a memory cell having one MOSFET and one capacitor, and bit line feeding means is provided between the bit line and the operating potential point. It is characterized by

The refresh operation of information is started by activating a word line, information of all memory cells connected to the word line is read onto each bit line, and this is amplified by the memory cell itself or a column amplifier. Then, the data is stored again in the memory cell and the process is completed. Therefore, in the refresh operation, some word lines can be shared in the range where the bit lines are not shared via the memory cells. That is, since the number of word lines can be equivalently reduced during the refresh operation as compared with the read and write operations, it is possible to achieve lower power consumption.

Further, the cycle time during the refresh operation in the chip non-selected state can be made about 100 times or more longer than the cycle time during the read and write operations. Therefore, the precharge period for charging the bit line can be similarly lengthened. Therefore, the drive power of the power supply means to the bit line can be reduced by that amount, that is, its self-parasitic capacitance can be reduced. As described above, by switching to the bit line power supply means having a smaller driving capacity than the read and write operations during the refresh operation, the power for driving the bit line power supply means is ideally 1/100 or less of the conventional power. It can be made small and low power consumption can be achieved.

That is, according to the present invention, a plurality of information are read or written by a signal of the main word line commonly provided for a plurality of memory arrays and a signal responsive to the decode signal and the refresh control signal from the control means. The divided word lines of the memory array are selectively activated, and a plurality of divided word lines are selected together by the signal of the main word line during the refresh operation. That is, by increasing the number of divided word lines selected at the time of refreshing, a large number of memory cells connected to a plurality of divided word lines can be refreshed at the same time. Therefore, the refresh cycle or interval can be lengthened, and the number of repetitions of the fresh operation to be performed within the unit time can be reduced. Therefore, the power consumption in the refresh operation can be reduced. That is, the signal of the main word line can be regarded as a selection signal for selecting a plurality of divided word lines in a plurality of memory arrays belonging to the main word line, and the signal to be supplied to the main word line is a plurality of memories. It can be formed by a circuit common to the array. That is,
Since the main word line driving circuit circuit such as the word driver and the decoder can be shared by a plurality of memory arrays, the number of operations at the time of refreshing the main word line driving circuit can be reduced and the power consumption in the refresh operation can be reduced. Can be reduced. As a result, by the signal formation by such a common circuit, the circuit scale can be sufficiently reduced and the power consumption can be sufficiently reduced.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic circuit diagram of a memory device according to a first embodiment of the present invention in which a volatile memory cell having a self-amplifying function is used, and FIGS. 2A is a diagram showing an example of the operation waveform, FIG. 2A is a signal timing chart at the time of the information read operation, and FIG. 2B is a signal timing chart at the time of the refresh operation.

In the figure, 1 and 1'are memory arrays,
2, 2'is an array of bit line feeding means, 3 is a memory cell,
4 is a bit line feeding means, 5 is a word line dividing means, 6 is a main word line, 7 and 7'are divided word lines, 8 is a bit line, 9
Is a power supply line, 10 is a bit line power supply means driving signal line, 11 is a refresh control signal line, 12 and 12 'are decode signal lines, 13 and 13' are word line division control means according to the present invention, and 14 and 14 'are words. The line division control signal line is shown.

The operation of the memory device having such a configuration is started when the input signal to the chip changes or when the refresh control signal inside the chip is activated.

First, all bit lines 8 in the memory array are precharged by the bit line feeding means 4. In the case of reading information from the memory cell or writing information to the memory cell, the refresh control signal line 11 is inactive, so that the decode signal lines 12 and 12 'by the address decoder are word line division control means. 13, 13 '
And the word line division control signal lines 14 and 14 'are directly input to the word line division means 5. Then
When a specific word line 6 is selected and activated, only one of the divided word lines 7 and 7'is activated (FIG. 2A).
Shows the case where the divided word line 7 is activated), and the read / write operation to the memory cell 3 is performed via the bit line 8.

On the other hand, in the refresh operation, since the refresh control signal line 11 is activated, the decode signal line 1 is activated by the word line division control means 13 and 13 '.
The word line division control signal lines 14 and 14 'are both activated regardless of the signals 2 and 12'. Therefore, next, when a specific word line 6 is activated, the divided word lines 7 and 7'are activated together. In this case, the specific bit line 8 is not selected, so that the charges precharged on the bit line 8 flow into the memory cell 3, and the stored information is rewritten by the amplifying function of the cell itself. In this case, since the cell itself has the function of amplifying the self-accumulation voltage, the time required for refreshing the information can be made minute, and therefore the voltage amplitude ΔV _B ((1)
Formula) can also be 0.5 V or less.

According to this embodiment, the number of word lines 2 ^N (equation (1)) at the time of the refresh operation can be halved as compared with the case where this embodiment is not applied. Further, the bit line voltage amplitude ΔV _B (equation (1)) can also be made minute as described above. Therefore, the power consumption when the chip for which the refresh operation is performed is not selected can be made extremely small, and a battery backup memory device requiring low power can be realized.

FIG. 3 is a diagram of an embodiment showing the embodiment of FIG. 1 more concretely, in which an insulated gate field effect transistor (hereinafter abbreviated as MOSFET) is used as the bit line feeding means 4 and the memory cell 3 is used. Is a case of using a cell composed of four MOSFETs.

FIG. 4 is a diagram of another embodiment specifically showing the embodiment of FIG. 1, in which one MOS is used as the memory cell 3.
This is the case of using a cell composed of an FET and one capacitor. In this case, since the memory cell itself does not have a self-amplifying function and the information read is destructive read, the column sense amplifier 15 is provided for each bit line 8.

Therefore, in this embodiment, the bit line voltage amplitude ΔV _B cannot be reduced as in the embodiment of FIG. 3, but the word line number 2 ^N during the refresh operation is not applied in this embodiment. Since it can be reduced to 1/2,
As is apparent from the equation (1), it is possible to reduce the power consumption during the refresh operation, and it is possible to realize a battery backup memory device.

The memory cell used in the present invention can be basically used as long as it is a volatile cell. In particular, FIG.
As in the embodiment of FIG.
Element type memory cell is most suitable, and this MOSFET is N
In the case of a channel, this memory cell is formed on a P-type substrate or in a P-type well formed on an N-type substrate. In addition, PMOSFET is a transfer transistor, NMO
It goes without saying that the present invention can also be applied to a 4MOS type memory cell using an SFET as a drive transistor. in this case,
When the word line is at the low level, the memory cell is selected and refreshed.

In the above embodiment, the number of word line divisions in the non-refresh (read and write operations) is set to 2 for simplification of description. However, lower power consumption and higher speed in read and write operations. To cope with this, it is necessary to further increase the number of word line divisions. In the above embodiment as well, the number of word line divisions can be increased, but in that case, the above effect can be further improved as is apparent from the equation (1).

Further, the present invention can be applied to all word lines that do not share a bit line via a memory cell.

FIG. 5 is a circuit diagram schematically showing the second embodiment of the present invention. In the figure, 3 is a memory cell,
Reference numeral 40 denotes a bit line power supply means that is activated by the drive signal line 10 when a chip is selected (during a read or write operation) and supplies electric charge to the bit line 8 from the power supply line 9, and 41 indicates a chip not selected (during a free-resh operation) The bit line power supply means 6 is activated by the drive signal line 10 'and supplies the electric charge to the bit line 8 from the power supply line 9, and 6 is a word line.

Access to the memory cell in the chip selected state is started by activating the bit line power supply means 40 having a large driving capability by the drive signal line 10 and precharging the bit line 8 at high speed. After that, a predetermined bit line and a word line are selected by the decode signal, and writing of information to a predetermined memory cell and reading of information from the memory cell are performed via the bit line. In this case, in order to shorten the cycle time required for the access operation, it is necessary to minimize the time required for the bit line precharge, that is, to increase the driving power of the bit line power supply means 40.

On the other hand, in the chip non-selected state, the information refresh operation is performed so that the information stored in the volatile memory cell is not destroyed. This operation is the drive signal line 1
The bit line power supply means 41 is activated by 0'and started by precharging the bit line 8, then a predetermined word line is selected, and the information data output on the bit line is transferred to the memory cell itself or a column sense amplifier or the like. By amplifying and rewriting to the memory cell. In this case, the point different from the chip selected state is that the cycle time required to refresh the information stored in the memory cell is sufficiently large within the range where the information is not destroyed (10 cycles of the access cycle time in the chip selected state).
0 times or more). Therefore, in this case, the time required for precharging the bit line can be similarly increased. That is, the drive power of the bit line power supply means 41 can be reduced. As a result, the parasitic capacitance of the bit line power supply means drive signal line can be dramatically reduced, so that the electric power for driving the bit line power supply means can be reduced.

According to this embodiment, the electric power required to drive the bit line feeding means when the chip is not selected can be ideally reduced to 1/100 or less as compared with the case where the present invention is not applied. Therefore, the power consumption when the chip is not selected can be made extremely small, which is very effective in realizing a battery device capable of backing up a battery that requires low power consumption.

FIG. 6 is a diagram of an embodiment specifically showing the embodiment of FIG. 5, in which NMOS is used as the bit line feeding means 40 and 41.
FET and four NMOSFETs as memory cells
This is the case when a cell configured by is used. 7 (a),
7B is a diagram showing an example of the operation waveform, and FIG.
Is a signal timing chart at the time of the information read operation, and FIG.

Chip selection state (during read and write operations)
When the access to the memory cell is started by an external signal or the like, the bit line power feeding means drive signal line 10 becomes high potential regardless of the state until then, the bit line power feeding means 40 is activated, and the bit line 8 Precharge at high speed. During the period when the predetermined word line 6 is selected, the signal becomes low potential, the bit line power supply means 40 is deactivated, and the information of the memory cell 3 is read out through the bit line 8 during this period. When the reading is completed, the bit line is precharged again by the signal of the drive signal line 10 at high speed to prepare for the next access. In this case, the drive signal line 10 'is fixed at a low potential and the bit line power supply means 41 is not activated.

On the other hand, in the chip non-selected state (during refresh operation), the drive signal line 10 is fixed at a low potential, the bit line power supply means 40 is not activated, and the drive signal line 10 ',
The bit line power supply means 41 performs the same operation as described above. However, since the cycle time in this case is sufficiently longer than that in the case described above, after the refresh is completed at a high speed by the information amplification function of the memory cell itself, the bit line feeding means 41 having a low driving capability precharges the bit line at a low speed. . Therefore, the electric power for driving the bit line power feeding means can be reduced.

FIG. 8 is a diagram of another embodiment specifically showing the embodiment of FIG. 5, in which NM is used as the bit line feeding means 40.
OSFET is used as the bit line power supply means 41 and PMOSF
This is the case when ET is used. In this case, FIG.
As shown in (b), by reversing the low potential side and the high potential side of the waveform of the drive signal line 10 'of the above embodiment, the same operation as that of the above embodiment can be performed.

The memory cell used in the present invention can be basically used if it is a volatile cell. In particular, FIG.
A four-element type memory cell composed of four NMOSFETs is optimum as in the embodiment of
It is formed on a P-type substrate or in a P-type well formed on an N-type substrate. In addition, 4M using PMOSFET as a transfer transistor and NMOSFET as a drive transistor
It goes without saying that it can also be applied to an OS type memory cell. In this case, the memory cell is selected and refreshed when the word line is at the low level.

Further, FIG. 10 is a view of still another embodiment specifically showing the embodiment of FIG. 5, in the case where a cell composed of one NMOS and one capacitor is used as a memory cell. 11A and 11B are diagrams showing an example of the operation waveforms thereof. FIG. 11A is a signal timing chart at the time of the information read operation and FIG. 11B is a signal timing chart at the time of the refresh operation. In this case, since the memory cell itself does not have the information amplification function and the reading of information from the cell is destructive reading, the read operation and the refresh operation are performed in the dummy cell 1.
6 and the column sense amplifier 15, the bit line driving method is the same as that of the above-described embodiment. Therefore, also in this case, as in the above-described embodiment, the power consumption during the refresh operation can be made extremely small.

[0038]

As described above, according to the present invention,
Since the power consumption during the refresh operation can be reduced without affecting the read / write operation of information, it is possible to realize a battery-backable memory that requires low power consumption.

[Brief description of drawings]

FIG. 1 is a circuit schematic diagram of an embodiment of a first embodiment of the present invention.

2A and 2B are diagrams showing operating waveforms of the circuit of FIG.

FIG. 3 is a circuit diagram showing a specific example of FIG.

FIG. 4 is a circuit diagram showing another specific example of FIG.

FIG. 5 is a circuit schematic diagram of a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a specific example of FIG.

7A and 7B are diagrams showing operation waveforms of the circuit of FIG.

FIG. 8 is a circuit diagram of another embodiment of FIG.

9A and 9B are diagrams showing operation waveforms of the circuit of FIG.

10 is a circuit diagram of yet another embodiment of FIG.

11A and 11B are diagrams showing operation waveforms of the circuit of FIG.

[Explanation of symbols]

1, 1 '... Memory cell array, 2, 2' ... Bit line feeding means array, 3 ... Memory cells, 4, 40, 41 ... Bit line feeding means, 5 ... Word dividing means, 6 ... Main word line,
7, 7 '... Divided word line, 8 ... Bit line, 9 ... Power supply line,
10, 10 '... Bit line feeding means driving signal line, 11 ... Refresh control signal line, 13, 13' ... Word line division control means, 14, 14 '... Word line division control signal line, 15
... column sense amplifier, 16 ... dummy memory cell.

Front page continuation (72) Inventor Osamu Minato 1-280, Higashi Koikekubo, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Shigeru Honjo 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi Central Research Co., Ltd. In-house (72) Toshiaki Masuhara 1-280, Higashi Koikekubo, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Nobuyuki Moriwaki 1450, Kamimizuhoncho, Kodaira-shi, Tokyo Inside Musashi Factory, Hitachi (72) Inventor Fumio Kojima 1448, Kamimizumoto-cho, Kodaira-shi, Tokyo Hitachi Ultra EPS Engineering Co., Ltd. In-house

Claims (4)

[Claims] 1. A bit line, a first word line, and
A plurality of memory arrays provided at the intersections of the bit lines and the first word lines and having volatile memory cells that need to be refreshed by a refresh operation; and arranged in parallel with the first word lines of the plurality of memory arrays. Are arranged in the plurality of memory arrays and are shared by the plurality of memory arrays in common with the first word lines of the plurality of memory arrays. A plurality of word line dividing means externally arranged to select the corresponding first word line by responding to the decode signal and the signal of the main word line, and word line dividing control for receiving a control signal on the refresh control signal line. In the refresh operation, the word line division control means is provided with the word line division means. The word line division control means controls the word line division means so as to select the corresponding division word line in response to the signal of the main word line without depending on the decode signal, and when reading or writing information, the word line division control means A semiconductor memory device, wherein the word line dividing means controls the word line dividing means so as to select a corresponding divided word line in response to the decode signal and the signal of the main word line. 2. The volatile memory cell comprises a memory cell having a self-amplifying function, and a bit line feeding means is provided between the bit line and an operating potential point. Item 2. The semiconductor memory device according to item 1. 3. The memory cell having the self-amplifying function,
A pair of MOSFETs whose gates and drains are cross-connected
And a pair of MOSFETs provided between the corresponding bit line and the drains of the pair of MOSFETs and having their gates connected to the corresponding first word line. Semiconductor memory device. 4. The volatile memory cell comprises one MOS.
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device comprises a memory cell having an FET and one capacitor, and bit line feeding means is provided between the bit line and the operating potential point.