JPH0993502A - Memory control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent occurrence of jitter even when a phase of a separated synchronizing signal is not coincident with a phase of composite video signal and to simplify the circuit configuration. SOLUTION: A horizontal synchronizing signal included in a composite video signal is separated by a synchronizing separator circuit 14 and a period of the separated synchronizing signal is measured by a period measurement circuit 16. The measured period is subtracted from a reference value by a subtractor 18 and a variable delay device 20 sets a delay according to the difference. A luminance signal Y and a chrominance signal C subjected to Y/C separation are written to and read out of line memories 26, 28 by a system clock outputted from a burst lock PLL circuit 12. A write address is reset by the separated synchronizing signal from the synchronizing separator circuit 14 and a read address is reset by the separated synchronizing signal from the variable delay circuit 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control circuit, and more particularly to a memory control circuit for writing and reading a luminance signal in a memory and resetting a write address and a read address.

[0002]

2. Description of the Related Art Referring to FIG. 6, in a conventional memory control circuit 1, a burst lock PLL circuit 2 generates a clock 1 which is locked to a burst signal, and a horizontal lock PLL circuit 3 separates a clock 1 into a sync separation circuit 4. The clock 2 locked to the separated sync signal thus generated is generated. Of these, clock 1
Accordingly, the input composite video signal is converted into a digital signal, separated into a luminance signal Y and a color signal C, and the color signal C is further converted into color difference signals RY and BY. The luminance signal Y and the color difference signals RY and BY are D / A converted at the rate of clock 1 and A / D converted at the rate of clock 2. The luminance signal Y and the color difference signal R-
Y and BY are once written in the line memories 6a to 6c included in the digital filter 5 and read out with a delay of one line period. Here, the line memories 6a to 6
When writing to and reading from c, clock 2
A write address and a read address are designated by counters 7a to 7c which are incremented by. Further, the write address and the read address are reset by the horizontal reference pulse outputted from the horizontal lock PLL circuit 3 and obtained by dividing the clock 2 by 910. The luminance signal Y and the color difference signals R-Y and B-Y read from the line memories 6a to 6c are then D
/ A converted and output.

[0003]

However, in such a conventional technique, a D / A converter and an A / D converter for converting the clock rate are required, and the circuit configuration becomes complicated. there were. If the clock 1 is applied to the line memories 6a to 6c instead of the clock 2 in order to omit the D / A conversion circuit and the A / D conversion circuit, the horizontal synchronizing signal included in the composite video signal is noisy. When it is deformed due to the influence of, the jitter of several dots occurs in the horizontal direction of the output image. That is, since the phase of the burst signal and the phase of the separation synchronization signal do not match, a phase shift of several clocks (dots) occurs between clock 1 and clock 2, which causes jitter in the horizontal direction. I will end up.

Therefore, a main object of the present invention is to provide a memory control circuit capable of simplifying the circuit configuration and preventing the occurrence of jitter.

[0005]

The present invention includes a clock generating means for generating a system clock, an A / D converting means for converting a luminance signal included in a composite video signal into a digital signal according to the system clock, and a composite video signal. A luminance separating signal is provided by a system clock, which is provided with a sync separating unit that separates the synchronizing signal and generates a separating synchronizing signal, a period measuring unit that measures the period of the separating synchronizing signal, and a variable delay unit that delays the separating synchronizing signal according to the measurement period. To and from the memory, reset the write address by the separate sync signal, and reset the read address by the separate sync signal output from the variable delay means.

[0006]

According to the system clock, the composite video signal is converted into a digital signal by, for example, an A / D converter and separated by Y / C by a Y / C separation circuit. As a result, a digital luminance signal is obtained.
The composite video signal is separated from the sync signal by the sync separation circuit, and the cycle of the separated sync signal is measured by, for example, the cycle measurement circuit. The measurement cycle is subjected to subtraction processing with a reference value by a subtractor, and the delay time of a variable delay device is set according to the subtracted value. The luminance signal is written to the write address designated by the system clock, and the write address is reset by the separated sync signal output from the sync separation circuit. The written luminance signal is then read from the read address designated by the system clock, and the read address is reset by the separated sync signal output from the variable delay unit.

[0007]

According to the present invention, the write address is reset by the separate sync signal output from the sync separating means, and the read address is reset by the separate sync signal output from the variable delay means. Even if the phase of the sync signal does not match the phase of the composite video signal, no jitter occurs in the horizontal direction of the output video. Also,
Since it is not necessary to match the phase between the system clock and the separated synchronization signal, the circuit configuration can be simplified.

The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a memory control circuit 10 of this embodiment includes a burst lock PLL circuit 12. The burst lock PLL circuit 12 outputs a system clock phase-locked to the burst signal included in the input composite video signal of the NTSC system and having a cycle of 1/910 of the horizontal synchronizing signal. The horizontal sync signal included in the composite video signal is also separated by the sync separation circuit 14, and the cycle of the separated sync signal is measured by the cycle measuring circuit 16. The subtractor 18 subtracts the period measured by the period measuring circuit 16 from the reference value T and gives the subtracted value to the variable delay device 20. The variable delay unit 20 sets a delay amount according to the subtracted value, and delays the separated sync signal according to the delay amount. The reference value T is set to the same value as the period H of the horizontal synchronizing signal included in the NTSC composite video signal.

The input composite video signal is A / D converted according to the system clock and Y / C separated by an A / D converter 22 and a digital Y / C separation circuit 24, and a luminance signal Y and a chrominance signal C, respectively. Are provided to the line memories 26 and 28 included in the digital filter 25 and having a capacity of 5 / 6H. The luminance signal Y and the chrominance signal C are written in the addresses (write addresses) corresponding to the count values of the counters 26a and 28a incremented by the system clock, and the written luminance signal Y and the chrominance signal C are written in the system clock. It is read from an address (read address) corresponding to the incremented count values of the counters 26b and 28b. The counters 26a and 28a are also reset by the fall of the separate sync signal output from the sync separator circuit 14, and the counters 26b and 28b are reset by the fall of the separate sync signal output from the variable delay unit 20. Line memory 2
The luminance signal Y and the chrominance signal C read from 6 and 28 are converted into analog signals by the D / A converters 30 and 32 in accordance with the system clock and output.

Upon receiving the subtraction value, the variable delay unit 20 sets the subtraction value + reference value T-offset β as a delay time, and after the delay time has elapsed from the time when the previous separation synchronization signal was output, the current separation synchronization signal. Is output. The offset β is a value larger than the pulse width α of the horizontal synchronizing signal, for example, 1
It is set to 6 dots. Due to this offset β, even if the subtracted value is the maximum value α, the read address is always reset before the reset of the next write address, and the data written in the line memories 26 and 28 is reset by the next write. Is also read first.

When the composite video signal shown in FIG. 2 (A) is input, if the falling phase of the separation sync signal fluctuates as shown by "↑" in FIG. The write addresses of the memories 26 and 28 are
As shown in FIG. 2C, it is incremented with the falling edge of the separated sync signal as a reference and reset at the next falling edge. The subtracted value output from the subtractor 18 is the value shown in FIG. When considering the offset β which is preset in the variable delay device 20, the variable delay device 20
As shown in FIG. 2E, when the reference value T + the subtraction value elapses from the output point of the previous separation synchronization signal, the separation synchronization signal of this time is output. As a result, the read address changes as shown in FIG. Therefore, as shown in FIG. 2 (G), the cycle of the output video signal delayed by about 1H becomes constant regardless of the fluctuation of the falling phase of the separation synchronization signal, and the video of each line is as shown in FIG. 2 (G). Is output at a fixed time interval.

For reference, FIG. 3 shows a timing diagram when the variable delay device 20 is not provided. In this case, both the write address and the read address are reset by the separated sync signal output from the sync separation circuit, as shown in FIGS. 3B and 3D, and therefore, as shown in FIG. In addition, the output video signal is affected by the phase shift of the separation synchronization signal, and the cycle in which the video of each line is output is also shown in FIG.
It changes as shown in (G).

Referring to FIG. 4, a memory control circuit 10 of another embodiment has a digital filter having two line memories 34a and 34b and line memories 36a and 36b for the luminance signal Y and the color signal C, respectively. Three
8 for controlling the line memories 34a to 36b. However, since the memory control circuit 10 is substantially the same as the memory control circuit 10 shown in FIG. 1, the same points are denoted by the same reference numerals, and a duplicate description will be omitted.

The separated sync signal output from the sync separation circuit 14 is used to reset the write address of the line memories 34a to 36b, and the separated sync signal delayed by the variable delay unit 20 is read out from the line memories 34a to 36b. Used to reset the. The result of the subtraction by the subtractor 18 is directly given to the adder 40, and the adder 4 is also passed through the latch circuit 42 that latches at the timing of the separation synchronization signal.
Given to 0. Therefore, the addition value of the subtraction result for two consecutive lines is output from the adder 40, whereby the delay amount of the variable delay device 20 is set. With such a configuration, when the falling phase of the separation sync signal with respect to the input composite video signal shown in FIG. 5A changes as shown in FIG. Is the value shown in FIG. The variable delay device 20 adjusts the phase of the separation synchronization signal based on the added value, and the read address is reset by the adjusted separation synchronization signal. Therefore, the phase of the video signal output with a delay of approximately two lines with respect to the input becomes constant as shown in FIG. 5 (G), and the video of each line is output at a constant cycle as shown in FIG. 5 (H). To be done.

In these embodiments, the write address is reset by the separate sync signal output from the sync separating circuit 14, and the read address is reset by the separate sync signal output from the variable delay unit 20. Even if the phase of the sync signal does not match the composite video signal, jitter does not occur in the horizontal direction of the output video. Moreover, since it is not necessary to match the phase between the system clock output from the burst PLL circuit 12 and the separated synchronization signal, the circuit configuration can be simplified. further,
Since the jitter is prevented by varying the delay amount of the separated sync signal, the phase of the burst signal and the phase of the horizontal sync signal may be changed due to fluctuations in the rotation cycle of the motor, etc., for the composite video signal reproduced from the home VTR. The effect is remarkable when is greatly varied.

Although the color signal C is filtered in these embodiments, the color difference signals RY and BY obtained by demodulating the color signal C are also filtered. Of course, this invention can be applied. In addition, this invention is a processor "SVP (Scanline Video Processo) of Texas Instruments Incorporated.
r) ”. Further, although the embodiments have described the case where the delay time between the input and the output is approximately 1H and 2H, when the delay time is kH, k measurement periods are used. It is necessary to set the delay amount of the variable delay device based on the integrated value of.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart showing a part of the operation of the embodiment in FIG.

FIG. 3 is a timing diagram showing a part of the operation of the background art.

FIG. 4 is a block diagram showing another embodiment of the present invention.

5 is a timing chart showing a part of the operation of the embodiment in FIG. 4; FIG.

FIG. 6 is a block diagram showing a conventional technique.

[Explanation of symbols]

10 ... Memory control circuit 12 ... Burst lock PLL 14 ... Sync separation circuit 16 ... Period measurement circuit 18 ... Subtractor 20 ... Variable delay device 26, 28, 34a, 34b, 36a, 36b ... Line memory 40 ... Adder 42 ... Latch circuit

Claims (3)

[Claims] 1. A clock generation means for generating a system clock, an A / D conversion means for converting a luminance signal included in a composite video signal into a digital signal according to the system clock, and a separation signal for separating a synchronization signal included in the composite video signal. Sync separation means for generating a synchronization signal, cycle measuring means for measuring a cycle of the separation synchronization signal, and variable delay means for delaying the separation synchronization signal in accordance with the measurement cycle, and the luminance signal stored in the system clock by the system clock A memory control circuit for writing and reading, resetting a write address by the separate sync signal, and resetting a read address by the separate sync signal output from the variable delay means. 2. The memory control circuit according to claim 1, further comprising subtraction means for performing subtraction processing between a reference value and the measurement cycle, wherein the variable delay means sets a delay time based on the subtraction value. 3. The memory control circuit according to claim 2, wherein the variable delay means delays the separation synchronization signal of this time after the delay time has elapsed from the output time of the separation synchronization signal of the last time.