JPH0992822A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control a reverse short channel effect and easily control an electrical characteristic of a semiconductor device. SOLUTION: An oxide film 5 is formed on the surface of a silicon substrate 10 to perform ion implantation of p-type impurities into the silicon substrate 10 by adopting the oxide film 5 as a buffer. The oxide film 6 of the second side layer is formed on the surface of the oxide film 5, and the oxide film 6 is selectively removed to form a groove 6a for forming a gate electrode 1, and the ion implantation of quantified p-type impurities is applied to the silicon substrate 10 by adopting the oxide film 6 as a mask. An oxide film at the bottom of the groove 6a is removed, a gate insulating film 4 is formed, an electrically conductive layer 1a for forming the gate electrode 1 is formed thereon, the electrically conductive layer 1a is flattened, and after that, the oxide film 6 is removed to form the gate electrode 1, and the ion implantation of n-type impurities is performed in order to form a source 2 and a drain 3. Therefore, re-distribution of impurities which is the cause of a reverse short channel effect can be controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
(Metal Oxide Semiconductor) The present invention relates to a method for manufacturing a semiconductor device such as a transistor.

[0002]

2. Description of the Related Art Generally, a semiconductor device such as a MOS is used.
In the transistor, when the gate length becomes short, the threshold voltage suddenly drops from a certain point. This is called the short channel effect and is a well-known phenomenon since ancient times.

Further, in recent years, with the miniaturization of LSIs, the gate length of MOS transistors has become shorter and more complicated, and as the gate length of MOS transistors becomes shorter, the threshold voltage of the transistors gradually increases. It has been reported that there is a phenomenon in which the threshold voltage rises rapidly and then the threshold voltage suddenly drops, and many reports have been made. This phenomenon of increasing the threshold voltage is called the reverse short channel effect.

For miniaturization of LSIs, it is required to shorten the gate length of MOS transistors. On the other hand, when the gate length of the MOS transistor becomes short, it becomes difficult to control the electrical characteristics such as the threshold voltage. One of the difficulties
One cause is the inverse short channel effect, and many studies have been published in recent years ("A Model for Anoma
lous Short-Channel Behavior in Submicron MOSFET '
s ", IEEE Electron Device Letters, Vol.14, No.12, D
ecember 1993, "Reverse Short-Channel Effect Due to
Lateral Diffusion of Point-Defect Induced by Sourc
e / Drain Ion Implantation ", IEEE Trans. on CAD of I
C and Systems, Vol.13, No.4, April 1994).

FIG. 8 is a schematic diagram showing the above-mentioned inverse short channel effect and short channel effect. In FIG. 8, the horizontal axis is M
The gate length of the OS transistor and the vertical axis represent the threshold voltage of the MOS transistor, respectively. The part where the threshold voltage of the MOS transistor rises as the gate length becomes shorter is due to the reverse short channel effect, and the part where the threshold voltage suddenly drops from somewhere is due to the short channel effect. Is.

Further, in FIG. 8, the broken line shows the change in the threshold voltage when there is no reverse short channel effect. As shown by the broken line in FIG. 8, when there is no reverse short channel effect, when the gate length becomes short, a phenomenon in which the threshold voltage suddenly drops from a certain point is observed. This is a generally known short channel. It is an effect.

The short channel effect is a phenomenon that is always seen in a normal MOS transistor, but the reverse short channel effect differs depending on the case. It is currently unclear when it will be significant. But mainly
Many results have been reported to be observed in MOS transistors having a current path near the surface of a semiconductor substrate.
In the following, such a MOS transistor having a current path near the surface of the semiconductor substrate (so-called surface channel type M
The cause of the reverse short channel effect will be described in detail with the OS transistor as a representative.

FIG. 9 shows, for example, an n-type MOS (hereinafter referred to as nM
It is a schematic sectional drawing which shows the cross section of a transistor called OS. FIG. 9A is a simplified cross-sectional view of a normal MOS transistor, and FIG. 9B is an LDD (Lightly Do).
FIG. 3 is a simplified cross-sectional view of a MOS transistor having a ped drain layer. In FIG. 9, 1 is the gate electrode of the nMOS transistor, 2 is the source of the nMOS transistor, 3 is the drain of the nMOS transistor, 2a and 3a.
Is an LDD layer, 4 is a gate insulating film, 8 is a sidewall spacer, and 10 is a silicon substrate.
Further, G is a terminal of the gate electrode 1, S is a terminal of the source 2,
D indicates the terminals of the drain 3, respectively. As shown, the gate electrode 1 is formed of, for example, polysilicon, the source 2 and the drain 3 are formed of n-type silicon, and the gate insulating film 4 is formed of, for example, silicon oxide (SiO ₂ ). .

FIG. 10 is a flow chart showing a manufacturing process of the MOS transistor shown in FIG. FIG. 11 is a simplified cross-sectional view showing a part of the manufacturing process of the MOS transistor. FIG.
In the sectional view of the nMOS transistor shown in, the same portions as those in the sectional view of FIG. 9 are denoted by the same reference numerals. In addition,
In FIG. 11, reference numeral 1a indicates a conductive layer forming the gate electrode 1. The manufacturing process of the conventional MOS transistor will be briefly described below in the order of manufacturing processes shown in the flowchart of FIG. 10 with reference to FIGS.

First, as in step S1, an oxide film made of silicon oxide (SiO ₂ ) is formed on the surface of the silicon substrate 10 by, for example, thermal oxidation treatment. This oxide film is used as a buffer in the next ion implantation step.

Then, the silicon substrate 1 is formed by ion implantation.
The process of step S2 of implanting a p-type impurity such as boron (B) into 0 is performed. By this step, the p well is formed in the silicon substrate 10. In addition, punch-through is suppressed and the threshold voltage of the MOS transistor is adjusted by this ion implantation process.

Then, the process shown in step S3 is performed,
The oxide film formed in the above step S1 is removed. Then, as shown in step S4, the gate insulating film 4 made of silicon oxide is formed on the surface of the silicon substrate 10 by, for example, a thermal oxidation process.

After forming the gate insulating film 4, step S
As shown in FIG. 5, on the surface of the gate insulating film 4, for example,
A conductive layer 1a having a two-layer structure composed of a polysilicon layer or a polysilicon layer and a refractory metal silicide layer such as a tungsten silicide layer is formed. FIG. 11A shows a state in which the gate insulating film 4 is formed on the silicon substrate 10 and the conductive layer 1 a is further formed on the gate insulating film 4.

Then, the conductive layer 1a is selectively removed to form the gate electrode 1 of the MOS transistor. FIG. 11B shows a state after the gate electrode 1 is formed.

Then, as shown in step S6, an n-type impurity such as phosphorus (P) is implanted into the silicon substrate 10 by, for example, ion implantation to form respective n ⁺ regions of the source 2 and the drain 3 of the MOS transistor. Form. FIG. 11C shows a state after the source 2 and the drain 3 are formed by ion implantation.

Then, heat treatment for activating impurities is performed, and finally wiring is formed to complete the manufacturing process of the MOS transistor.

As described above, the normal n-type MOS shown in FIG.
The manufacturing process of the (nMOS) transistor is shown. In addition,
In the manufacturing process of the MOS transistor having the LDD layers 2a and 3a shown in FIG. 9B, in addition to the above manufacturing process, before the step S6 is performed, an n-type impurity such as phosphorus (P) is used for ion implantation. The n-type LDD layer 2
After forming a and 3a, sidewall spacers 9 are formed as shown in FIG. After that, as in step S6 described above, the source 2 and the drain 3 are formed by ion implantation using the same n-type impurities as those used to form the LDD layers 2a and 3a.

As described above, taking the nMOS transistor as an example,
Normal nMOS transistor and LDD layers 2a and 3a
The manufacturing process of the nMOS transistor having the above has been described.
In the case of a p-type MOS (pMOS) transistor,
By changing the p-type impurity to the n-type and the n-type impurity to the p-type in the manufacturing process described above, the pMOS transistor can be configured by almost the same manufacturing process. Then, only the nMOS transistor has been described.

In the above-described manufacturing process, in step S2 of forming a p-well, ion implantation is performed on the entire surface of the silicon substrate 10 by using the same amount and the same amount of p-type impurities as the lower layer of the gate electrode 1, eg, boron (B). I do. LDD
Impurities of the opposite type to the lower layer of the gate electrode 1, that is, n-type impurities, for example, phosphorus (P) are implanted in the regions and the source / drain regions so as to cover the impurities.

FIG. 12 shows the impurity concentration distribution of the nMOS transistor formed by the above manufacturing process. FIG. 12A shows the normal nMOS shown in FIG. 9A.
FIG. 12B is a schematic diagram of the impurity concentration distribution along the line AA of the transistor, and FIG. 12B shows the impurity along the line BB of the nMOS transistor having the LDD layers 2a and 3a shown in FIG. 9B. It is a schematic diagram of concentration distribution.

As shown in FIG. 12A, step S2
The p-type impurity implanted by is distributed almost uniformly in the substrate. Actually, it is widely known that a change is observed near the PN coupling, but since it is smaller than the change in the concentration distribution shown in FIG. 13, it is omitted here. Then, in the n-type impurity region formed in step S6, for example, the source 2 region, the concentration of the n-type impurity implanted in the ion implantation process maintains a constant value in the source region, and in the lower layer of the gate electrode 1, n The concentration of mold impurities decreases. Further, as shown in FIG. 12B, it can be seen that in the nMOS transistor having the LDD layers 2a and 3a, the concentration of the n-type impurity is distributed in two stages. This is done before the ion implantation to form the source 2 and drain 3
This is because ion implantation was performed once to form a and 3a.

However, the schematic diagram of the distribution of impurities shown in FIG. 12 shows a classical distribution of impurities that does not take into consideration factors such as diffusion due to point defects and mutual diffusion between impurities. It is known that point defects are caused by ion implantation for forming an LDD region, ion implantation for forming a source / drain region, an oxidation process of the region, or the like.

In an actual MOS transistor, L
Due to the diffusion of the point defects of the impurities injected into the DD region, the source / drain region, etc., impurities of the same type as the impurities in the lower layer of the gate electrode 1 are transferred from the deep region under the gate electrode 1, the source / drain region, and the LDD region The phenomenon of diffusion to the lower layer of the electrode 1 and vice versa occurs, and the impurities in the lower layer of the gate electrode 1 are redistributed.

When the above-mentioned redistribution of the impurities occurs, the distribution of the impurities in the lower layer of the gate electrode changes depending on the gate length, so that the state of carriers flowing in the lower layer of the gate electrode also changes. Therefore, the threshold voltage of the MOS transistor also changes depending on the gate length, and the reverse short channel effect occurs.

FIG. 13 is a schematic diagram of the impurity concentration distribution of the nMOS transistor in consideration of the above point defect. FIG. 13A shows the normal nMOS shown in FIG. 9A.
FIG. 13B is a schematic diagram of the impurity concentration distribution along the line AA of the transistor, and FIG. 13B is an impurity along the line BB of the nMOS transistor having the LDD layers 2a and 3a shown in FIG. 9B. It is a schematic diagram of concentration distribution.

As shown in FIG. 13, when the point defect is taken into consideration, the impurity concentration in the lower layer of the gate electrode 1 of the MOS transistor is redistributed due to the point defect, and the impurity in the lower layer of the gate electrode 1 depends on the length direction of the gate. The concentration distribution of changes. The redistribution of the lower layer impurity concentration of the gate electrode 1 due to this point defect is the cause of the reverse short channel effect.

[0027]

In the case of a general LSI,
A plurality of MOS transistors having different gate lengths are formed in one semiconductor substrate. It is desired that the electrical characteristics of these various MOS transistors be controllable. However, the reverse short channel effect, which has become remarkable along with the scale-up and miniaturization of LSIs, makes it difficult to control the above electrical characteristics. This is because the reverse short channel effect is considered to be caused by the redistribution of impurities in the semiconductor, and it is difficult to control the redistribution of the impurities. As a result, the reverse short channel effect causes electrical conductivity of the MOS transistor. It is difficult to control the characteristics, for example, the threshold voltage, and in recent years, it has become more difficult to control the electrical characteristics of the MOS transistor with the increase in the scale and miniaturization of the LSI.

The present invention has been made in view of such circumstances, and an object thereof is to suppress an inverse short channel effect,
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can easily control electrical characteristics.

[0029]

In order to achieve the above object, the present invention provides two diffusion layers on a semiconductor substrate,
A method of manufacturing a semiconductor device in which a current path is formed between these two diffusion layers, the step of selectively implanting a first conductivity type impurity into a region of the semiconductor substrate, which becomes the current path, and the two diffusion layers. And a step of selectively implanting a second conductivity type impurity into a region to be a layer.

Further, in the present invention, the first conductivity type impurity is selectively implanted into a region which becomes a current path of the semiconductor substrate,
After forming a mask on the current path region in which the impurity is injected, the second conductivity type impurity for the diffusion layer is injected into the semiconductor substrate.

Further, in the present invention, the first conductivity type impurity is selectively implanted into a region which becomes a current path of the semiconductor substrate,
After forming the gate electrode on the current path region in which the impurity is injected, the second conductivity type impurity for the diffusion layer is injected into the semiconductor substrate.

The selective implantation of the first conductivity type impurity is performed as follows.
After forming a mask on the semiconductor substrate, the mask on the region to be the current path is selectively removed to form a groove,
Impurity implantation is performed by implanting the first conductivity type impurity from the trench portion, and also by providing an offset region on the sidewall of the mask in the trench.

The gate electrode is formed by encapsulating a conductive material in the groove and then removing the mask. Further, the mask formed on the semiconductor substrate is formed of an insulating film including a nitride film. .

Further, in the reverse order of the above manufacturing steps, in the present invention, the first conductivity type impurities are selectively implanted into the regions to be the two diffusion layers in the semiconductor substrate, and then the impurities are implanted. A mask is formed on the diffusion layer region, and second conductivity type impurities are selectively implanted into the semiconductor substrate.

According to the present invention, the first conductivity type impurity is selectively implanted by implanting a first conductivity type impurity into the semiconductor substrate by forming a mask on a region serving as a current path on the semiconductor substrate. By doing.

Further, in the present invention, an offset region is provided on the side wall of the mask, and impurities are selectively implanted into the region serving as the current path. Further, the mask formed on the diffusion layer is formed of an insulating film including a nitride film.

According to the present invention, the first-conductivity-type impurity is selectively implanted into the region of the semiconductor substrate which becomes the current path. This selective implantation of impurities is performed, for example, by forming a groove in a mask formed on the substrate, and the implantation of impurities is performed through this groove portion.

Then, after forming a mask or forming a gate electrode on the current path region into which the first conductivity type impurity has been implanted, the second conductivity type impurity for the diffusion layer is implanted.

Further, according to the present invention, a mask is formed on a portion serving as a current path on the semiconductor substrate, and ion implantation for the diffusion layer is performed on the semiconductor substrate using the first conductivity type impurity. .

Then, a mask is formed on the ion-implanted diffusion layer region and the mask on the current path region is selectively removed, and then ion implantation is performed to form a current path using the second conductivity type impurity. Then, the gate electrode is formed.

[0041]

1 is a flow chart showing a first embodiment of a method for manufacturing a semiconductor device according to the present invention. FIG.
Using the method for manufacturing a semiconductor device shown in the flowchart of FIG.
For example, it is a simplified cross-sectional view of an nMOS transistor showing a part of the process of manufacturing the nMOS transistor.

The method of manufacturing the nMOS transistor according to the first embodiment will be described below with reference to the flowchart of FIG. 1 and the simplified sectional view of FIG. The cross-sectional view of the nMOS transistor formed according to the first embodiment is the cross-sectional view of the conventional nMOS transistor shown in FIG.
Since it is the same as FIG. 9A and FIG. 9B, the same parts of the nMOS transistor in FIG. That is, 1 is the gate electrode of the nMOS transistor, 2 is the source of the nMOS transistor,
Reference numeral 3 denotes the drain of the nMOS transistor, 4 denotes the gate insulating film, and 10 denotes the silicon substrate. Also,
In FIG. 2, reference numerals 5 and 6 denote silicon oxide films.

According to the method of manufacturing a semiconductor device of the present invention,
When forming an nMOS transistor, first, the process of step S1 shown in FIG. 1 is performed, and the oxide film 5 is formed on the surface of the silicon substrate 10 by, for example, a thermal oxidation process.
This oxide film 5 is used as a buffer in the next ion implantation step.

Then, the silicon substrate 1 is formed by ion implantation.
The p-type impurity, for example, boron (B) or indium (In) is ion-implanted into 0 at step S2a. By this step, the p well is formed in the silicon substrate 10.

Then, as shown in step SI1, a second-layer oxide film 6 is formed on the surface of the oxide film 5 formed as a buffer for the above ion implantation, and then step S
The trench 6a for forming the gate electrode 1 is formed by performing the process of I2 and selectively removing the oxide film 6 of the second layer.
To form FIG. 2A shows a state after the second layer oxide film 6 is formed, and FIG. 2B shows a state after the second layer oxide film 6 is selectively removed. It shows the state.

Then, the processing of S2b shown in FIG. 2 is performed,
P is again applied to the silicon substrate 10 by ion implantation.
Type impurities are implanted. In this ion implantation process, the amount of impurities to be implanted is set in advance, and punch-through is suppressed and the threshold voltage of the MOS transistor is adjusted by this quantified ion implantation.

Then, the process of step S3 is performed to form the groove 6
a The oxide film on the bottom is removed. After that, as shown in step S4, the surface of the silicon substrate 10 at the bottom of the groove 6a is subjected to, for example, thermal oxidation treatment to form silicon oxide (Si
A gate insulating film 4 made of O ₂ ) is formed.

After the gate insulating film 4 is formed, as shown in step S5, on the surface of the gate insulating film 4, for example, a polysilicon layer or a two-layer composed of a polysilicon layer and a refractory metal silicide layer such as a tungsten silicide layer is formed. A conductive layer 1a having a structure is formed, and the conductive layer 1a is planarized to form a gate electrode 1. FIG. 2 (c)
Shows a state after the conductive layer 1a is formed, and FIG.
Shows a state in which the conductive layer 1a forming the gate electrode 1 is flattened.

Then, as in step SI3, the oxide film 6 is removed and the gate electrode 1 of the MOS transistor is formed. FIG. 2E shows a state after the gate electrode 1 is formed.

Then, as shown in step S6, an n-type impurity such as phosphorus (P) or arsenic (As) is implanted into the silicon substrate 10 by, for example, ion implantation, and each of the source 2 and the drain 3 of the MOS transistor is implanted. To form the n ⁺ region. FIG. 2F shows a state after the source 2 and the drain 3 are formed by ion implantation.

Then, as in step S7, the heat treatment for activating the impurities is performed, and finally, the process of step S8 is performed to form the wiring, and the manufacturing process of the MOS transistor is completed.

Although the normal nMOS transistor manufacturing process has been described above, in the manufacturing process of the MOS transistor having the LDD layers 2a and 3a, in addition to the above manufacturing process, an n-type impurity, For example, phosphorus (P) is used to perform ion implantation, and LDD layers 2a and 3a
And then the sidewall spacers 8 are formed. After that, as in step S6 described above, the source 2 and the drain 3 are formed by ion implantation using the same n-type impurities as those used to form the LDD layers 2a and 3a.

Further, in the above manufacturing process, in step SI2, when the oxide film 6 is selectively removed to form the groove 6a for forming the gate electrode 1, for example, a taper-shaped offset is used. The region 9 is formed, the process of step S2b is performed, and the p-type impurity is implanted again into the silicon substrate 10 by ion implantation.

As described above, by forming the offset region 9 on the side wall of the groove 6a and performing ion implantation, redistribution of impurities can be suppressed, and the reverse short channel effect based thereon can be suppressed.

As described above, taking the nMOS transistor as an example,
Normal nMOS transistor and LDD layers 2a and 3a
The manufacturing process of the nMOS transistor having the above has been described.
In the case of a pMOS transistor, by changing the p-type impurity to the n-type and the n-type impurity to the p-type in the above-described manufacturing process, the pMO
Since the S transistor can be configured, only the nMOS transistor has been described here to avoid duplication.

FIG. 3 is a diagram showing the distribution of the impurity concentration of the nMOS transistor manufactured according to the first embodiment. FIG. 3A shows the distribution of the impurity concentration corresponding to the line AA of FIG. 9A in the nMOS transistor of the present invention, and FIG. 3B shows the nMO having the LDD layers 2a and 3a.
The distribution of the impurity concentration corresponding to the BB line of FIG. 9B of the S transistor is shown.

As shown in FIG. 3, as a result of selectively implanting the impurities, the p-type impurities are distributed only in the lower layer of the gate electrode 1 and not in the source 2 and the drain 3. As a result, the redistribution of impurities due to point defects is suppressed, and the reverse short channel effect due to this is also suppressed.

As described above, according to the first embodiment, the oxide film 6 of the second layer is selectively removed, and after the groove 6a for forming the gate electrode 1 is formed, After implanting a p-type impurity such as boron (B) or indium (In) into the silicon substrate 10 and forming the gate insulating film 4 and the gate electrode 1, implanting an n-type impurity into the regions of the source 2 and the drain 3. Therefore, the p-type impurities are distributed only in the lower layer of the gate electrode 1, and the n-type impurities are distributed only in the regions of the source 2 and the drain 3. Thereby, the reverse short channel effect can be suppressed, and MO
The electrical characteristics of the S transistor, for example, the threshold voltage can be easily controlled.

FIG. 4 is a flow chart showing a second embodiment of the method for manufacturing a semiconductor device according to the present invention. The semiconductor device according to the second embodiment, for example, an nMOS transistor manufacturing method is different from that according to the first embodiment shown in FIG. 1 in that step SN1, step SN2, and step SN3 are added.

In the above-described first embodiment, the oxide film 5 may be penetrated when performing ion implantation for punch-through suppression and threshold voltage control in step S2b. In order to solve this, in the second embodiment, the step of forming the nitride film 7 is added before forming the oxide film 6 in step SI1.

The second embodiment will be described below with reference to FIGS. 4 and 5. In the following description, the same parts as those in the first embodiment will be omitted. In the second embodiment, the steps up to step S2a are the same as those in the above-described first embodiment, and the description thereof will be omitted here. In step S2a, a p-well is formed by implanting a p-type impurity into the silicon substrate 10, and the nitride film 7 is formed on the surface of the oxide film 5 formed as a buffer for ion implantation, as in step SN1. Form a film.

Then, the oxide film 6 is formed on the surface of the nitride film 7 as in steps SI1 and SI2 in the first embodiment, and the formed oxide film 6 is selectively removed. I do. FIG. 5A shows a state after the oxide film 5, the nitride film 7 and the oxide film 6 are formed.

Then, the process of step SN2 is performed to selectively delete the nitride film 7,
In the process of 2, the groove 6a for forming the gate electrode 1 is formed together with the process of step SI2. FIG. 5B shows a state after the oxide film 6 and the nitride film 7 are selectively removed to form the trench 6 a for forming the gate electrode 1.

Hereinafter, substantially the same processing as that of the first embodiment is performed, and as shown in FIGS. 5C and 5D, the same processing is performed until the planarization processing of the conductive layer 1a for forming the gate electrode 1. Performs various processing. Then, after the conductive layer 1a forming the gate electrode 1 is flattened, the process of step SI3 is performed to remove the oxide film 6, and the process of step SN3 is further performed to make the nitride film 7
Is removed. FIG. 5E shows a state after the oxide film 6 and the nitride film 7 are removed and the gate electrode 1 is formed. Then, as shown in step S6 of FIG.
By implanting n-type impurities into the silicon substrate 10 by ion implantation, the source 2 and drain 3 of the MOS transistor are
4 shows the state after the n ⁺ region forming the is formed.

Since the processing from here to the formation of the nMOS transistor is the same as that of the first embodiment, the description of the following processing will be omitted.

According to the second embodiment, the nitride film 7 is formed on the surface of the oxide film 5 in advance, the second-layer oxide film 6 is formed thereon, and the oxide film 6 is selectively removed. 6
Then, a groove 6a for forming the gate electrode 1 is formed in the nitride film 7. As a result, in the subsequent implantation of p-type impurities by ion implantation, they penetrate through the oxide film 5 and p
There is no possibility that the type impurities are injected into the diffusion layer. Therefore, it is possible to more effectively distribute the p-type impurities only in the lower layer portion of the gate electrode 1 and the n-type impurities only in the regions of the source 2 and the drain 3 as compared with the case of the first embodiment. The reverse short channel effect can be suppressed, and the electrical characteristics of the MOS transistor, for example, the threshold voltage can be easily controlled.

Further, in the second embodiment, when the trenches 6a for forming the gate electrode 1 are formed by selectively removing the oxide film 6 and the nitride film 7 by steps SI2 and SN2. 5B, an offset region 9 is formed on the side wall of the groove 6a, the process of step S2b is performed, and a p-type impurity is implanted again into the silicon substrate 10 by ion implantation. To do.

Thus, by performing the ion implantation after forming the offset region 9 on the side wall of the groove 6a, the redistribution of the impurities can be effectively suppressed, and the reverse short channel effect based thereon can be suppressed.

FIG. 6 is a flow chart showing a third embodiment of the method for manufacturing a semiconductor device according to the present invention. The semiconductor device according to the third embodiment, for example, a method for manufacturing an nMOS transistor, is different from the first and second embodiments in that ion implantation for threshold voltage control and punch-through suppression is performed. The difference is that it is performed after the drain region is formed. As a result, the heat treatment time after the ion implantation can be shortened, so that the abnormal diffusion of point defects can be suppressed and the redistribution of impurities can be effectively suppressed.

FIG. 7 is a schematic sectional view showing a part of the manufacturing process of the nMOS transistor in the third embodiment, for example. In FIG. 7, 1 is a gate electrode, 1a is a conductive layer, 2 is a source, 3 is a drain, 4 is a gate insulating film, 5 and 6 are oxide films, 7 is a nitride film, and 10 is a silicon substrate. Hereinafter, the manufacturing process of the MOS transistor of the third embodiment will be described with reference to FIGS.

First, step S1 of forming the oxide film 5 on the surface of the silicon substrate 10 by, for example, thermal oxidation treatment.
Is performed, and the formed oxide film 5 is used as a buffer for p
Type impurities such as boron (B) are ion-implanted and p
The process of step S2a for forming a well is performed. Then, the processes shown in Steps SI1 and SI2 are performed, an oxide film 6 is further formed on the oxide film 5, and the oxide film 6 is selectively removed to form a mask for forming the source 2 and the drain 3. Form. The oxide film 6 is patterned so that the selective deletion has the same length as the gate electrode 1.

Next, the processes shown in steps S6a and S7a are performed, and the semiconductor substrate 10 is ion-implanted with an n-type impurity, for example, phosphorus (P), using the oxide film 6 after the selective removal as a mask, and the source is removed. Regions of 2 and drain 3 are formed, and heat treatment for activating impurities is further performed. FIG. 7A shows a state after the source 2 and the drain 3 are formed.

Next, the processing shown in steps SN4 and SN5 is performed, a nitride film 7 is formed on the surface of the oxide film 6, and the nitride film 7 is flattened. FIG. 7B shows a state after the nitride film 7 is flattened.

Then, the process of step SI3 is performed to selectively remove the oxide film 6 and the oxide film 5 in the portion where the gate electrode 1 is to be formed, and the groove 6a for forming the gate electrode 1 is opened, as shown in step S2b. Then, a p-type impurity is implanted through the groove 6a to adjust the threshold voltage of the MOS transistor and suppress punch through. FIG. 7C shows a state in which p-type impurities are ion-implanted.

Then, the process of step S3 is performed, and the natural oxide film of silicon generated by natural oxidation in the groove 6a in the above manufacturing process is removed to form the gate insulating film 4 made of silicon oxide. . Then, the process of step S5 is performed, and the conductive layer 1a having a two-layer structure including, for example, a polysilicon layer or a polysilicon layer and a refractory metal silicide layer such as a tungsten silicide layer or a titanium silicide layer is formed on the gate insulating film 4. To form. FIG. 7D shows a state after the conductive layer 1a is formed.

Then, as shown in FIG. 7E, the conductive layer 1a is flattened, and then the process of step SN6 is performed. As shown in FIG. 7F, the nitride film 7 is removed and the gate electrode is removed. 1 is formed. After that, the process of step S8 for forming wiring is performed to form an nMOS transistor.

Although the manufacturing process of the nMOS transistor according to the present invention has been described above, the M having the LDD layers 2a and 3a has been described.
In the manufacturing process of the OS transistor, in addition to the manufacturing process described above, before performing step S6a, ion implantation is performed using an n-type impurity, for example, phosphorus (P), and the LDD layer 2 is formed.
a and 3a are formed. Then, as in step S6a, the same n as when forming the LDD layers 2a and 3a is used.
The source 2 and the drain 3 are formed by ion implantation using the type impurities. After forming the gate electrode 1, sidewall spacers 8 are formed on both sides of the gate electrode 1.
To form By adding the manufacturing process as described above, a MOS transistor having an LDD layer is formed.

As in the first and second embodiments, before ion-implanting the p-type impurity through the groove 6a, an offset region is formed on the side wall of the groove 6a as shown by the dotted line in FIG. 7C. By performing ion implantation after forming 9, the redistribution of impurities can be effectively suppressed, and the reverse short channel effect based thereon can be suppressed.

As described above, according to the third embodiment, after the regions of the source 2 and the drain 3 are formed by the ion implantation of the n-type impurity, the threshold voltage is changed by the ion implantation of the p-type impurity. And p-type impurity ion implantation for suppressing punch-through. That is,
Ion implantation is finally performed on the lower layer of the gate electrode 1.
When performing ion implantation into the lower layer of the gate electrode 1, a mask formed of the nitride film 7 is used on the regions of the source 2 and the drain 3. As a result, n-type impurities and p
The type impurities can be distributed separately. That is,
The p-type impurities can be distributed only in the lower layer of the gate electrode 1, and the n-type impurities can be distributed only in the regions of the source 2 and the drain 3.

Further, contrary to the usual manufacturing process, the source 2
After the formation of the drain 3 and the drain 3, ion implantation for adjusting the threshold voltage and suppressing punch-through is performed. As a result, after the ion implantation for adjusting the threshold voltage and suppressing punch-through, the time for heat treatment is shortened, whereby abnormal diffusion of point defects can be suppressed and redistribution of impurities can be suppressed. In general, according to the third embodiment, the abnormal diffusion of point defects can be suppressed, the redistribution of impurities can be suppressed, and the reverse short channel effect can be suppressed.

In the above description of the first, second and third embodiments, the oxide film 6 and the nitride film 7 are formed as a mask for ion implantation.
The present invention is not limited to this, and the ion implantation mask can be formed using a material that forms the gate electrode 1 and another material that can be easily selectively removed. Further, although the material forming the gate electrode 1 has a two-layer structure of polysilicon or polysilicon and a refractory metal silicide such as tungsten silicide, it goes without saying that other materials that can form the gate electrode can be used.

[0082]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the abnormal diffusion of point defects can be suppressed in the semiconductor substrate, and the redistribution of impurities can be suppressed. For this reason,
The reverse short channel effect due to the redistribution of impurities can be suppressed, and the electrical characteristics of the semiconductor device, such as the threshold voltage, can be easily controlled.

[Brief description of drawings]

FIG. 1 is a flowchart showing a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a simplified cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

FIG. 3 is a distribution diagram of impurity concentration of a MOS transistor.

FIG. 4 is a flowchart showing a second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a simplified cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment.

FIG. 6 is a flowchart showing a third embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a simplified cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment.

FIG. 8 is a schematic diagram showing an inverse short channel effect.

FIG. 9 is a simplified cross-sectional view showing a cross section of a MOS transistor.

FIG. 10 is a flow chart showing a conventional method of manufacturing a semiconductor device.

FIG. 11 is a simplified cross-sectional view showing a conventional manufacturing process.

FIG. 12 is a distribution diagram of impurities in a MOS transistor without considering point defects.

FIG. 13 is a distribution diagram of impurities of a MOS transistor considering a point defect.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Gate electrode 1a ... Conductive layer 2 ... Source 3 ... Drain 2a, 3a ... LDD layer 4 ... Gate insulating film 5, 6 ... Oxide film 6a ... Trench 7 ... Nitride film 8 ... Sidewall spacer 9 ... Offset region 10 ... Silicon Substrate G ... Gate electrode terminal S ... Source terminal D ... Drain terminal

Claims (11)

[Claims] 1. A semiconductor substrate having two diffusion layers formed thereon,
A method of manufacturing a semiconductor device in which a current path is formed between these two diffusion layers, the step of selectively implanting a first conductivity type impurity into a region of the semiconductor substrate, which becomes the current path, and the diffusion layer And a step of selectively implanting a second-conductivity-type impurity into the region to be formed. 2. A semiconductor substrate having two diffusion layers formed thereon,
A method of manufacturing a semiconductor device in which a current path is formed between these two diffusion layers, wherein a first conductivity type impurity is selectively injected into a region that becomes a current path of the semiconductor substrate, and the current injected with the impurity is A method for manufacturing a semiconductor device, comprising forming a mask on a path region and then implanting the second conductivity type impurity for the diffusion layer into the semiconductor substrate. 3. A semiconductor substrate having two diffusion layers formed thereon,
A method of manufacturing a semiconductor device in which a current path is formed between these two diffusion layers, wherein a first conductivity type impurity is selectively injected into a region of the semiconductor substrate which becomes a current path, and the current injected with the impurity A method of manufacturing a semiconductor device, comprising forming a gate electrode on a path region and then implanting the second conductivity type impurity for the diffusion layer into the semiconductor substrate. 4. The selective implantation of the first conductivity type impurity is performed by forming a mask on the semiconductor substrate and then selectively removing the mask on a region to be the current path to form a groove. The method of manufacturing a semiconductor device according to claim 2, wherein the first conductivity type impurity is implanted from the groove portion. 5. The method of manufacturing a semiconductor device according to claim 4, wherein an offset region is provided on the side wall of the mask in the groove, and the first conductivity type impurity is implanted. 6. The method of manufacturing a semiconductor device according to claim 4, wherein the gate electrode is formed by encapsulating a conductive material in the groove and then removing the mask. 7. The method of manufacturing a semiconductor device according to claim 4, wherein the mask formed on the semiconductor substrate is formed of an insulating film including a nitride film. 8. A semiconductor substrate having two diffusion layers formed thereon,
A method of manufacturing a semiconductor device in which a current path is formed between these two diffusion layers, wherein a first conductivity type impurity is selectively implanted into a region which becomes the diffusion layer in the semiconductor substrate, A method of manufacturing a semiconductor device, wherein a mask is formed on a diffusion layer region in which is implanted, and a second conductivity type impurity is selectively implanted into a region serving as the current path. 9. The selective implantation of the first conductivity type impurity is performed by forming a mask on a region serving as a current path on the semiconductor substrate and implanting the first conductivity type impurity into the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 8, which is performed. 10. The method of manufacturing a semiconductor device according to claim 8, wherein an offset region is provided on the side wall of the mask on the diffusion layer region, and the first conductivity type impurity is implanted. 11. The method of manufacturing a semiconductor device according to claim 8, wherein the mask formed on the diffusion layer region is formed of an insulating film including a nitride film.