JPH0992810A - Solid state image pickup device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the S/N by suppressing fixed pattern noise by white defect and preventing any decrease in signal output. SOLUTION: A tapered surface 43a is formed at the side of a gate insulating film 42 in MIS gate construction of an edge portion in such a manner that the thickness of the edge portion of a gate electrode 43 in MIS gate construction will become gradually smaller. A source/drain region 44 is formed by self alignment relative to the gate electrode 43. The source/drain region 44 has an impurity region 44a having a relatively high concentration and an impurity region 44b having a relatively low concentration as well as an LDD construction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device and a method of manufacturing the same, and more particularly to a MIS (Metal-Insulator-Semi).
conductor) The present invention relates to a solid-state imaging device including an element having a gate structure, and is suitable for use in, for example, a video camera or an electronic still camera.

[0002]

2. Description of the Related Art CCDs and amplification type solid-state image pickup devices are typical examples of conventional solid-state image pickup devices of this type. Here, as a conventional example of an amplification type solid-state imaging device, a MOS type static induction transistor (hereinafter, referred to as “MOSS”).
A device using "IT") as a pixel will be described.

FIG. 9 is a circuit diagram showing this conventional solid-state image pickup device. Although FIG. 9 shows an example in which the pixels have a 2 × 2 matrix configuration, the number of pixels is not limited to this.

As shown in FIG. 9, each pixel 1-1, 1-
2, 2-1 and 2-2 are composed of MOSSIT.

The drain electrodes of the pixels 1-1, 1-2, 2-1 and 2-2 are connected in common to all the pixels, and the power supply voltage 3
It is connected to the.

The gate electrodes of the pixels 1-1 and 1-2 of the first row in the matrix arranged in the horizontal direction are commonly connected to the gate line 4, and the gate electrodes of the pixels 2-1 and 2-2 of the second row are the gates. Commonly connected to line 5. The drive pulse generating circuit 7 is provided in the row selected in the horizontal direction by the vertical scanning circuit 6.
Drive pulses φ _V1 and φ _V2 having a desired drive timing and voltage level generated in 1 are applied to the gate electrodes of the pixels 1-1, 1-2, 2-1 and 2-2 through the gate lines 4 and 5. . Depending on whether the voltage levels of the drive pulses φ _V1 and φ _V2 applied to the gate electrodes of the pixels 1-1, 1-2, 2-1, 2-2 are low level, intermediate level or high level, the pixel MO
SSIT1-1, 1-2, 2-1 and 2-2 have three states of accumulation / readout / reset.

The source electrodes of the pixels 1-1 and 2-1 in the first column in the matrix arranged in the vertical direction are commonly connected to the vertical source line 8, and the source electrodes of the pixels 1-2 and 2-2 in the second column are connected in common. Commonly connected to the vertical source line 9. One of the vertical source lines 8 and 9 is connected to the vertical reset / constant current bias circuit 10. The other one of the vertical source lines 8 and 9 has the optical signal output transfer MOSFET 1 for each column.
1-1, 11-2 and MOSFET 1 for dark signal output transfer
It is connected to one electrode of the optical signal output storage capacitors 13-1 and 13-2 and the dark signal output storage capacitors 14-1 and 14-2 via 2-1 and 12-2, and is read out horizontally. Selection MOSFETs 15-1, 15-
Optical signal output line 1 through 2, 16-1 and 16-2, respectively
7 and the dark signal output line 18. These signal output lines 17 and 18 have parasitic capacitances 19 and 20, respectively.

Further, the optical signal output line 17 and the dark signal output line 18 have horizontal read reset MOSFETs 21-1 for resetting a video signal to be transmitted.
The drain of 21-2 is connected. The sources of the horizontal read reset MOSFETs 21-1 and 21-2 are
The optical signal output storage capacitors 13-1 and 13-2 and the dark signal output storage capacitors 14-1 and 14-2 are connected to the other electrodes and grounded. The gate electrodes of the horizontal read reset MOSFETs 21-1 and 21-2 are commonly connected, and when the drive pulse φ _RSTH is applied to the gate electrodes, the horizontal read reset MOSFET 2 is connected.
1-1 and 21-2 are operated.

The horizontal read selection MOSFET 15
The horizontal selection signal lines 23 and 24 connected to the horizontal scanning circuit 22 are commonly connected to the respective gate electrodes of -1, 15-2, 16-1 and 16-2 for each column. Horizontal reading is controlled by the horizontal drive pulses φ _H1 and φ _H2 sent from 22. The MOSFETs 15-1 and 15-2 are for reading an optical signal that supplies the optical signal output temporarily stored in the optical signal output storage capacitors 13-1 and 13-2 to the optical signal output line 17. MOSFET 16-1, 16-2
Is for reading the dark signal, which supplies the dark signal output once accumulated in the dark signal output accumulating capacitors 14-1 and 14-2 to the dark signal output line 18.

The optical signal output transfer MOSFET 11-
The respective gate electrodes of 1 and 11-2 are commonly connected to the gate line 25, and the dark signal output transfer MOSFET 12-
Gate electrodes 1 and 12-2 are commonly connected to a gate line 26. When drive pulses φ _TS and φ _TD are applied to these gate electrodes, optical signal output transfer MOSFETs 11-1 and 11-2 are applied.
And dark signal output transfer MOSFETs 12-1 and 12-2
Operate alternately in a predetermined order.

In the conventional solid-state image pickup device, the vertical scanning circuit 6, the driving pulse generating circuit 7 and the horizontal scanning circuit 22 constitute a driving circuit. Also, MOSF
ET11-1, 11-2, 12-1, 12-2, 15-
1, 15-2, 16-1, 16-2, 21-1, 21-
2 and capacitors 13-1, 13-2, 14-1, 14
-2 constitutes a read circuit.

Next, the operation of the conventional solid-state image pickup device will be described.

Pixel MOSSIT 1-1, 1-2, 2-
When the gate potentials of 1 and 2 are at a low level, the pixel is in an accumulation state and accumulates holes generated by incident light immediately below the gate electrode. However, the pixel can be kept in a non-conducting state even when a hole corresponding to the saturated exposure amount is accumulated, and a false signal is generated even when a light amount several hundred times the saturated light amount is irradiated. Does not cause blooming phenomenon.

Pixel MOSSIT 1-1, 1-2, 2-
When the gate potentials 1 and 2 are at the intermediate level, the pixel is in the read state. In this case, the channel potential is modulated by the holes accumulated directly under the gate of the pixel, and an amplified current inside the pixel, which is proportional to the amount of incident light, can flow between the drain and the source. .

Pixel MOSSIT 1-1, 1-2, 2-
When the gate potentials of 1 and 2 become high level, the holes accumulated just below the gate electrode of the pixel are discharged toward the substrate. That is, a reset operation is performed.

Pixel MOSSIT 1-1, 1-2, 2-
When 1 and 2-2 are in the storage state, the drive pulses φ _TS and φ _TD are set to a high level in the horizontal blanking period, and the optical signal output transfer MOSFETs 11-1 and 11-2 and the dark signal output transfer MOSFET 12-1 are set. , 12-2 are brought into conduction, so that the optical signal output storage capacitor 13-
1, 13-2 and dark signal output storage capacitor 14-
The electric potentials of 1 and 14-2 are initialized. Before starting the read operation, the drive pulses φ _TS and φ _TD are set to low level, and the optical signal output transfer MOSFETs 11-1 and 11-2 and the dark signal output transfer MOSFETs 12-1 and 12-2 are turned off. .

An intermediate level drive pulse φ _V1 or φ _V2 is applied to the gate electrodes of the pixels 1-1, 1-2 or 2-1, 2-2 in the horizontal row selected by the vertical scanning circuit 6. Then,
The pixels in the selected row are in the read state. At this time, the drive pulse φ _{TS is set} to a high level and the optical signal output transfer MOS is
When the FETs 11-1 and 11-2 are turned on, the source follower operation of the pixel in the selected row starts, and the optical signal charge according to the incident light amount is stored in the optical signal output storage capacitors 13-1 and 13-. Accumulated in 2. After a certain transfer period, the drive pulse φ _{TS is set} to the low level to bring the optical signal output transfer MOSFETs 11-1 and 11-2 into the non-conducting state, thereby completing the source follower operation of the pixel in the selected row. . After that, a high level drive pulse φ _V1 or φ _V2 is applied to the gate electrode of the pixel of the selected row where the optical signal read operation is completed, and the reset operation is performed.

After the reset operation is completed, the intermediate level drive pulse φ _V1 or φ _V2 is applied again to the gate electrodes of the pixels in the selected row. Further, by setting the drive pulse φ _TD to a high level and turning on the dark signal output transfer MOSFETs 12-1 and 12-2, the source follower operation of the pixel in the selected row is started, and the dark signal of the pixel MOSSIT is started. Electric charge is dark signal output storage capacitors 14-1, 14-2
Is accumulated in After a certain transfer period, φ _{TD is set} to a low level, and dark signal output transfer MOSFETs 12-1 and 12-
The dark signal read-out operation is completed by putting 2 into the non-conducting state.

The dark signal output immediately after the reset is the pixel MO.
This is equivalent to the threshold voltage variation of SSIT itself, and the fixed pattern noise (FPN) is generated because the threshold voltage varies from pixel to pixel.

Optical signal output storage capacitors 13-1, 1
3-2 and dark signal output storage capacitors 14-1 and 14
After the accumulation of the optical signal charges and the dark signal charges to -2 is completed, the horizontal scanning circuit 22 is operated to sequentially read the pixel outputs of the selected horizontal row.

That is, first, the horizontal scanning circuit 22 causes the gates of the horizontal read MOSFETs 15-1 and 16-1 to operate.
A high level horizontal drive pulse φ _H1 is applied to the gate electrode to bring the horizontal read MOSFETs 15-1 and 16-1 into a conductive state. As a result, the optical signal output storage capacitor 1
The optical signal output accumulated in 3-1 is input to the optical signal output line 17, the dark signal output accumulated in the dark signal output accumulating capacitor 14-1 is input to the dark signal output line 18, and parasitic capacitances 19 and 20 are respectively provided. And voltage division V _OS ,
It is output to the outside of the device as V _OD .

By subtracting the output V _OD from the output V _OS outside the element (not shown), the fixed pattern noise due to the threshold voltage variation described above can be suppressed and the true optical signal output can be obtained. .

Next, the drive pulse φ _RSTH is _set to a high level, and the horizontal read line reset MOSFETs 21-1 and 2-2.
The above output line 1 can be obtained by putting 1-2 into the conductive state.
The electric potentials of 7 and 18 are initialized.

After that, the horizontal scanning circuit 14 is scanned and the horizontal read MOS is used to read the output of the pixel in the adjacent column.
By making the FETs 15-2 and 16-2 conductive and repeating the above operation, the image output of the column can be obtained.

The pixels 1-1 and 1-2 of the first row described above
The read operation for the pixel is performed on the pixels 2-1 and 2-2 in the second row.
The same applies to.

In the conventional solid-state image pickup device, the pixel MOSSIT 1-1, 1-2, 2-1 and 2-2 and the horizontal readout selection MOSFET 15-.
1, 15-2, 16-1, 16-2, etc. are elements having a MIS gate structure (MOS gate structure in this example),
These elements are configured as shown in FIG.
FIG. 10A is a schematic cross-sectional view of the main parts of these elements,
FIG. 10B is an enlarged view of a part in FIG. 10A and is an explanatory view regarding a white defect caused by the crystal defect dislocation network 35.

The element having the MIS gate structure in the conventional solid-state image pickup device is manufactured as follows. That is, the gate oxide film 32 is formed on the first conductivity type substrate 31 by thermal oxidation. After this, chemical vapor deposition (hereinafter C
VD) is used to form a film of polysilicon, and impurities such as phosphorus are diffused in the polysilicon for the purpose of lowering the resistance.
The gate electrode 33 made of polysilicon is formed by patterning as shown in FIG. The gate electrode 33 has a uniform thickness even at its edge portion and has a rectangular cross-sectional shape. Thereafter, the source / drain region 34 of the second conductivity type (the region which becomes either one of the source region and the drain region is referred to as a “source / drain region”. That is, two regions on both sides in FIG. One of the two source / drain regions 34 serves as a source region and the other serves as a drain region.
Impurities are ion-implanted and thermally diffused by self-alignment using the gate electrode 33 as a mask.

[0028]

The above-mentioned conventional solid-state image pickup device has the first problem that S / N may be deteriorated due to white defects caused by pixel defects or the like.

This point will be described with reference to FIG. In the ion implantation process described above, the source /
The PN junction between the drain region 34 and the substrate 31 becomes amorphous. In the process of recrystallizing the amorphous layer, the recrystallization direction is different between the vertical direction X and the horizontal direction Y of the source / drain region 34, so that a crystal defect having a curvature as shown in FIG. Dislocation network (Mask Edge Defect) 3
5 is formed.

This crystal defect dislocation network 35 is formed in the PN junction region between the source / drain region 34 and the substrate 31 as shown in FIG. 10B, or the depletion layer reaches the crystal defect dislocation network 35. In that case, it becomes a large dark current source. Therefore, in particular, the pixel MOSSIT1-1, 1-
When such a situation occurs in No. 2, 2-1 and No. 2-2, the image becomes a white defect defect.

The fixed pattern noise due to such a white defect cannot be suppressed by the subtraction processing of the optical signal and the dark signal described above, and therefore it is necessary to have a structure structurally unaffected by the crystal defect dislocation network.

As a method of avoiding the influence of the crystal defect dislocation network 35, the heat treatment after the ion implantation is excessively performed to diffuse the impurities deeply and the source / drain regions 3 are formed.
It is known that 4 may be formed deep. However, in this case, the diffusion of impurities in the lateral direction also becomes large, so that the pixel MOSSIT 1-1, 1-2, 2-
The effective gate lengths of 1 and 2 become short, which adversely affects the electrical characteristics.

Further, the stress of the gate electrode 33 (that is, polysilicon in this example) may cause distortion at the position of the end of the gate electrode 33 inside the substrate 31, and this distortion (not shown) also causes dark current. It becomes a generation source. Therefore, in particular, the pixel MOSSIT 1-1, 1-2, 2-1 and 2-
When such a situation occurs in No. 2, as in the case of the crystal defect dislocation network 35, it becomes an image-wise white defect.

Secondly, in the conventional solid-state image pickup device, secondly, the signal output is largely lowered, resulting in S / N.
However, there was a problem that it deteriorated.

That is, in the conventional solid-state image pickup device, as described above, the output storage capacitor 13-
1, 13-2, 14-1, 14-2 and signal output line 1
Although the voltage outputs V _OS and V _OD are obtained by capacitance division with the parasitic capacitances 19 and 20 of 7, 18 (that is, the optical signal output and the dark signal output are read out), the parasitic capacitances 19 of the signal output lines 17 and 18 are 20 is an output storage capacitor 13-1, 1
Since it is relatively larger than 3-2, 14-1 and 14-2, there is a problem that the signal outputs V _OS and V _OD at the element output ends are lowered, resulting in deterioration of S / N. is there.

This point will be described with reference to FIG.

In the conventional solid-state image pickup device, the output storage capacitors 13-1, 13-2, 14-1, 14 are provided.
-2, the signal charges accumulated in the signal output lines 17, 1
The capacitance is divided by the parasitic capacitances 19 and 20 of 8 and discharged to the outside of the element.

Parasitic capacitance 1 of signal output lines 17 and 18
9 and 20 are (1) a component determined by the wiring length, and (2) horizontal readout selection MOSFETs 15-1, 15-2, 16-1, 16- connected to the signal output lines 17 and 18.
A component determined by the overlap amount 36 between the second source / drain region (impurity diffusion layer) 34 and the gate electrode 33,
(3) Horizontal readout selection MOSFETs 15-1, 15-2, 16 connected to the signal output lines 17, 18
-1, 16-2 source / drain regions 34 and substrate 31
Is the sum of the component determined by the area between and, and (4) the component determined by the intersection of the wiring and the wiring.

The components (1) and (4) can be reduced by making the wiring as thin as possible. The component of (3) above is M
This can be reduced by reducing the diffusion area of the OSFETs 15-1, 15-2, 16-1, 16-2.

The component (2) will be described with reference to FIG. As described above, the source / drain regions 34 are formed by ion-implanting and thermally diffusing impurities by self-alignment using the gate electrode 33 as a mask. However, since the impurities also diffuse laterally, the gate electrode 33 is formed.
An overlap region 36 is formed between the source / drain region 34 and the source / drain region 34, and the overlap region 36 forms a parasitic capacitance 37. In the parasitic capacitance 37, the interlayer insulation between the gate electrode 33 and the source / drain region 34 is the gate oxide film 32 having a thickness of several tens nm, and the overlap amount of the overlap region 36 is relatively large. , MOSFETs 15-1, 15-2, 16-1,
The value of the parasitic capacitance 37 of each of 16-2 becomes relatively large. Therefore, the parasitic capacitance 37 is connected to the signal output line 1
Since 7 and 18 are parasitic as many as the number of horizontal pixels,
The value of the parasitic capacitance as a whole becomes considerably large.

Therefore, in the conventional solid-state image pickup device, the parasitic capacitances 19 and 2 of the signal output lines 17 and 18 are used.
0 is output storage capacitors 13-1, 13-2, 14-
1 and 14-2 are relatively large, the signal outputs V _OS and V _OD at the element output end are lowered, and as a result, the S / N is deteriorated.

The present invention has been made in view of the above circumstances, and suppresses fixed pattern noise due to a white defect and suppresses S / S.
It is an object to provide a solid-state imaging device that can improve N and a method for manufacturing the same.

Another object of the present invention is to provide a solid-state imaging device capable of preventing a decrease in signal output and improving S / N, and a method for manufacturing the same.

[0044]

In order to solve the above-mentioned problems, the solid-state image pickup device according to the first aspect of the present invention is provided with a MIS.
In a solid-state imaging device including an element having a gate structure,
A taper surface is formed on the edge portion of the gate electrode in the MIS gate structure so that the thickness of the edge portion of the gate electrode in the MIS gate structure gradually decreases. The tapered surface may be a curved surface or a flat surface.

A solid-state imaging device according to a second aspect of the present invention is the solid-state imaging device according to the first aspect, wherein the element having the MIS gate structure constitutes at least a part of a pixel.

The solid-state image pickup device according to the third aspect of the present invention is the solid-state image pickup device according to the second aspect, wherein the pixel receives in the control region an embedded photodiode for generating and accumulating charges according to incident light. An amplification junction field effect transistor that produces an amplified output according to an electric charge, and a transfer MIS field effect transistor that transfers the electric charge generated and accumulated by the embedded photodiode to the control region of the junction field effect transistor. A reset MIS field effect transistor for discharging the charges transferred to the control region of the amplification junction field effect transistor. The element having the MIS gate structure is at least one of the transfer MIS field effect transistor and the reset MIS field effect transistor.

A solid-state imaging device according to a fourth aspect of the present invention is the solid-state imaging device according to any one of the first to third aspects, in which the element having the MIS gate structure constitutes a part of a read circuit. Is.

A solid-state image pickup device according to a fifth aspect of the present invention is the solid-state image pickup device according to the fourth aspect, wherein the readout circuit temporarily stores an optical signal output from a pixel, and an optical signal output storage capacitor. An optical signal reading MIS field effect transistor for supplying an optical signal output accumulated in the optical signal output accumulating capacitor to an optical signal output line, and an element having the MIS gate structure,
It is characterized in that it is the MIS type field effect transistor for reading an optical signal.

A solid-state image pickup device according to a sixth aspect of the present invention is the solid-state image pickup device according to the fourth or fifth aspect, wherein the readout circuit temporarily stores the dark signal output from the pixel. An element having the MIS gate structure, comprising: a capacitor; and a dark signal reading MIS field effect transistor that supplies a dark signal output accumulated in the optical signal output accumulating capacitor to a dark signal output line. It is a MIS field effect transistor for signal readout.

A solid-state imaging device according to a seventh aspect of the present invention is the solid-state imaging device according to the first to sixth aspects, wherein the element having the MIS gate structure is formed in self-alignment with the gate electrode. It has a source region and a drain region, and the source region and the drain region have an LDD structure.

A method of manufacturing a solid-state image pickup device according to an eighth aspect of the present invention includes a step of forming a gate insulating film on a semiconductor substrate of the first conductivity type, and a step of forming a gate electrode on the gate insulating film. Implanting an impurity into the semiconductor substrate using the gate electrode as a mask to form a second conductivity type source region and a drain region, and implanting the impurity into the semiconductor substrate. Before this, a tapered surface is formed on the edge portion of the gate electrode on the side of the gate insulating film in the MIS gate structure so that the edge portion of the gate electrode is gradually thinned.

[0052]

According to the present invention, the thickness of the edge portion of the gate electrode in the MIS gate structure is gradually reduced,
A taper surface is formed on the edge portion on the side of the gate insulating film in the MIS gate structure, so to speak, the edge portion of the gate electrode has an inverse taper structure.

Therefore, in the element having the MIS gate structure in which the edge portion of the gate electrode has the inverse taper structure,
Impurity is ion-implanted using the gate electrode as a mask
When the drain region is formed, an impurity region having a relatively high concentration and an impurity region having a relatively low concentration are simultaneously formed in the source / drain region in correspondence with the thickness of the edge portion of the gate electrode. The same structure as described above (this structure is referred to as “LDD structure” in this specification). In the case of the LDD structure, the high-concentration impurity region is deeply and laterally diffused by the heat treatment, but the low-concentration impurity region has a low concentration and a shallow diffusion depth. Diffusion can be suppressed, and the effective gate length is determined by the low concentration impurity region. As a result, the heat treatment after the ion implantation is applied excessively as compared with the conventional case, and the crystal defect dislocation network can be deeply diffused so as to be included in the high concentration impurity region. Therefore, the crystal defect dislocation network does not serve as a dark current generation source.

Therefore, when the element having the MIS gate structure in which the edge portion of the gate electrode has the inverse taper structure constitutes at least a part of the pixel as in the second and third aspects, Image-wise, white defects will not occur, fixed pattern noise due to white defects will be suppressed,
From this point, S / N can be improved. Moreover,
Since the effective gate length does not become short, the electrical characteristics are not impaired.

Further, even if strain occurs at the position of the end of the gate electrode inside the substrate due to the stress of the gate electrode, this strain can be included in the high-concentration impurity region like the crystal defect dislocation network. As a result, white defects due to this distortion do not occur.

Further, in the element having the MIS gate structure in which the edge portion of the gate electrode has the inverse taper structure, the overlap region between the gate electrode and the source / drain region is significantly reduced. Therefore, the parasitic capacitance of the element is also reduced.

Therefore, when the element having the MIS gate structure in which the edge portion of the gate electrode has the inverse taper structure constitutes a part of the read circuit as in the fourth to sixth aspects, It is possible to prevent a decrease in signal output, and to improve S / N from this point.

[0058]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a solid-state image pickup device according to an embodiment of the present invention will be described with reference to FIGS.

The solid-state image pickup device according to the present embodiment has a MOSSI as an element having a MIS gate structure as a pixel.
It has T. Further, the solid-state imaging device according to the present embodiment has a MOSFET as an element having a MIS gate structure as a part of the read circuit. These MOSSI
The T and MOSSIT are configured as shown in FIG.

FIG. 1A shows the MOSSIT and the M
FIG. 1B is a schematic cross-sectional view of a main part of the OSFET, and FIG.
It is explanatory drawing regarding the white flaw defect by the crystal defect dislocation network 45 which expanded a part in (a).

As shown in FIG. 1, the MOSSIT and the MOSFET in the solid-state imaging device according to the present embodiment have a gate insulating film (in this embodiment, a gate oxide film formed on a substrate 41 of the first conductivity type). However, other insulating films may be used.) 42, and a gate electrode 43 made of polysilicon or the like formed on the gate insulating film 42,
It has. That is, the MOSSIT and the M
The OSFET has a MIS gate structure.

Then, as shown in FIG.
A tapered surface 43a is formed on the edge portion of the gate electrode 43 on the side of the gate insulating film 42 in the MIS gate structure so that the edge portion 3 of the gate electrode 43 gradually becomes thinner. That is, so to speak, the edge portion of the gate electrode 43 has an inverse taper structure.

Further, in this embodiment, the MOSSIT and the MOSFET are source / drain regions of the second conductivity type (conductivity type opposite to the first conductivity type) formed in self-alignment with the gate electrode 43. It has 44. One of the two source / drain regions 44 on both sides in FIG. 1 is a source region and the other is a drain region. The source / drain regions 44 have a relatively high concentration impurity region 44a and a relatively low concentration impurity region 44.
b and have an LDD structure.

Also in the solid-state image pickup device according to the present embodiment described above, as in the case of the conventional solid-state image pickup device described above, the crystal defect dislocation network 45 is formed as shown in FIG. 1B.

However, in this embodiment, since the edge portion of the gate electrode 43 has an inverse taper structure, in the device shown in FIG. 1, the gate electrode 43 is used as a mask to implant impurities into the source / drain regions 44. When formed, as described above, in the source / drain region 44, the impurity region 44a having a relatively high concentration and the impurity region 44b having a relatively low concentration corresponding to the thickness of the edge portion of the gate electrode 43 are formed.
Are simultaneously formed to form an LDD structure. In the case of the LDD structure, the high-concentration impurity region 44a is deeply and laterally diffused by heat treatment, but the low-concentration impurity region 44a has a concentration of 44.
Since b is low and the diffusion depth is shallow, lateral diffusion can be suppressed even if heat treatment is applied, and the effective gate length is determined by the low-concentration impurity region 44b. By this, the heat treatment after ion implantation is applied excessively compared to the conventional one,
As shown in FIG. 1B, the crystal defect dislocation network 45 can be deeply diffused so as to be included in the high concentration impurity region 44a. Therefore, the crystal defect dislocation network 45 does not serve as a dark current generation source.

Therefore, in this embodiment, M as a pixel is
Since the OSSIT has the configuration shown in FIG. 1, image-wise no white defect is generated, fixed pattern noise due to the white defect is suppressed, and from this point, S / N can be improved. Moreover, since the effective gate length does not become short, the electrical characteristics are not impaired.

Further, even if the stress of the gate electrode 43 causes a strain at the position of the end of the gate electrode 43 inside the substrate, this strain is included in the high-concentration impurity region 44a like the crystal defect dislocation network 35. Therefore, white defects due to this distortion do not occur.

In the device shown in FIG. 1, the gate electrode 4
Since the edge portion 3 has an inverse taper structure, the overlap region between the gate electrode 43 and the source / drain region 44 is greatly reduced as compared with the conventional case. Therefore, the parasitic capacitance 46 of the element is also reduced.

Therefore, in this embodiment, since the MOSFET as a part of the read circuit has the structure shown in FIG. 1, a decrease in signal output is prevented, and from this point, the S / N ratio is reduced.
Can be improved.

Next, the element shown in FIG. 1 (MOSSIT
An example of a method of manufacturing a MOSFET (or MOSFET) will be described with reference to FIGS. 2 is a schematic cross-sectional view showing an example of a manufacturing process of the device shown in FIG. 1, and FIG. 3 is a schematic cross-sectional view showing a manufacturing process of the device shown in FIG. 1 following FIG. 2 and 3, elements corresponding to those in FIG. 1 are designated by the same reference numerals.

First, according to the prior art, the first conductivity type substrate 4
A gate oxide film 42 of several tens of nm is formed on the surface of 1 by thermal oxidation, and then polysilicon 43 is formed by CVD. After that, impurities such as phosphorus are diffused into the polysilicon 43 in order to reduce the resistance of the polysilicon 43 (FIG. 2A).

Next, a photoresist 47 is applied on the polysilicon 43, and a required pattern is transferred and developed using, for example, a reduction type projection exposure apparatus to leave the photoresist 47 patterned into a predetermined shape (see FIG. 2 ( b)).

Then, the polysilicon 43 is dry-etched using the photoresist 47 as a mask (FIG. 2).
(C)). The photoresist 47 is used as a mask.
However, the surface of the polysilicon 47 may be oxidized and patterned, for example. As a dry etching apparatus, for example, reactive ion etching (Reactive Ion
Etching) device. As a reaction gas, F series, C
It is common to use 1-system, Br-system or the like. Further, it is common to add another gas to these gases and perform etching as a mixed gas. It is preferable that a strong anisotropy and a selective ratio with respect to the oxide film are ensured in any gas system.

On the photoresist 47 and the etched polysilicon 43, the side wall protective film 48 which is generated by reaction during the dry etching is attached (FIG. 2C). The side wall protective film 48 is attached to prevent dry etching in the lateral direction and to obtain strong anisotropy, as is generally known.

FIG. 2D shows the end of dry etching up to the interface between the polysilicon 43 and the gate oxide film 42. Normally, over-etching is performed to completely etch the polysilicon 43. In this case, the overetching amount is determined in consideration of the selection ratio with the gate oxide film 42.

Next, in the state of FIG. 2D, the anisotropic dry etching is switched to the isotropic dry etching. Specifically, for example, the gas composition ratio having a strong anisotropy is changed to a gas composition ratio having a strong isotropic property, or the gas species itself is changed to an isotropic gas. Further, isotropic wet etching may be performed instead of isotropic dry etching. Then, as shown in FIG. 2D, since the side wall protective film 48 has a small adhesion amount on the substrate 41 side, the etching progresses in the lateral direction and the above-mentioned inverse taper structure is realized (FIG. 3).
(A)). The polysilicon 43 in this state becomes the gate electrode.

Thereafter, the photoresist 47 is peeled off and the side wall protective film 48 is removed. The side wall protective film 48 is made of SiO.
Since it has a composition of SiO ₂ type or polymer type, it can be easily removed with dilute hydrofluoric acid or hot sulfuric acid.

Next, using the polysilicon 43 as a mask, impurities are ion-implanted and thermally diffused (FIG. 3B). As a result, the source / drain regions 44 having the relatively high-concentration impurity regions 44a and the relatively low-concentration impurity regions 44b, that is, the LDD structure are easily formed (FIG. 3).
(C)).

Finally, using the conventional known technique, the PSG
The device is completed by performing the interlayer insulating film 49 and the multi-layer wiring process (FIG. 3D).

The manufacturing method described above is not shown in FIG.
In the state of (d), the anisotropic etching is switched to the isotropic etching, but the anisotropic etching is continued in the state of FIG. 2 (c) without continuing the anisotropic etching until the state of FIG. 2 (d). It is possible to switch from etching to isotropic etching. Even in this case, since the side wall protective film 48 is not attached to the substrate 41 side in the state shown in FIG. 2C, the etching also progresses in the lateral direction, and the above-described inverse taper structure is realized. (FIG. 3 (a)). Subsequent steps are the same as in the above-described manufacturing method.

FIG. 4 shows a concrete example of the solid-state image pickup device (the solid-state image pickup device described with reference to FIG. 1) according to the embodiment.
This will be described with reference to FIG.

The circuit configuration of the solid-state imaging device according to this example is the same as the circuit configuration of the conventional solid-state imaging device described with reference to FIG. Therefore, the duplicated description is omitted here.

FIG. 4A shows the horizontal read selection MOSFET 15 in FIG. 9 in the solid-state image pickup device according to the present embodiment.
It is a schematic plan view of a horizontal read selection MOSFET corresponding to -1. In addition, FIG. 4B shows A in FIG.
It is a sectional view taken on line -A '.

In FIG. 4, elements corresponding to those in FIG. 1 are designated by the same reference numerals, and their description will be omitted.

In FIG. 4, 51 is connected to one source / drain region 44 through a contact hole 52 to form one source / drain electrode, and FIG.
It is an Al wiring corresponding to the inside optical signal output line 17.
53 is the other source / via the contact hole 54.
The source / drain electrode of the other side connected to the drain region 44, and the optical signal output transfer MOS shown in FIG.
It is an Al wiring that serves as a wiring for connecting to the FET 11-1. Further, 55 is an interlayer insulating film, 56 is a field oxide film, and 57 is a field dope region which is a high concentration region of the same conductivity type as the substrate 41.

In this example, the horizontal read selection MOSFE
In order to minimize the parasitic capacitance due to T, the gate electrode 43
Is a ring, and the source / drain region 44 inside the ring-shaped gate electrode 43 corresponds to the optical signal output line 17
It is connected to the I wiring 51. In addition, the ring-shaped gate electrode 4
The contact portion between the source / drain region 44 inside 3 and the Al wiring 51 is also set to the minimum size to reduce the area.

In this example, M for horizontal read selection in FIG.
The horizontal read selection MOSFETs corresponding to the OSFETs 15-2, 16-1, 16-2 also have a structure similar to that shown in FIG. Although not shown in the drawing, in this example, the pixel MOSSIT1-1, 1-in FIG.
2, 2-1 and 2-2 also have the same structure as that shown in FIG.

Next, a solid-state image pickup device according to another embodiment of the present invention will be described with reference to FIGS.

FIG. 5 is a circuit diagram showing the solid-state image pickup device according to this embodiment. Although FIG. 5 shows an example in which the pixel 60 has a 2 × 2 matrix configuration, the number of pixels is not limited to this.

As shown in FIG. 5, the unit pixel 60 includes an embedded photodiode (hereinafter referred to as “BPD”) 61 for generating and accumulating charges according to incident light, and a charge received in a control region. A junction-type field effect transistor for amplification (hereinafter referred to as “JFET”) 62 that produces a corresponding amplified output, and a charge generated and accumulated in the BPD 61 by the JF
A p-channel MOSFET (hereinafter, referred to as “transfer MOSFET”) 63 as a transfer MIS type field effect transistor for transferring to the control region of the ET 62, and a JFET
And a p-channel MOSFET (hereinafter, referred to as “reset MOSFET”) 64 as a reset MIS field effect transistor that discharges the charges transferred to the control region 62. In addition, transfer MOSFET
The gate electrode of 63 serves as a transfer gate (hereinafter referred to as “TG”) that transfers the charge generated and accumulated in the BPD 61 to the control region of the JFET 62. Further, the drain of the reset MOSFET 64 serves as a reset charge discharging unit for discharging the charges transferred to the control region of the JFET 62.
"D"), and the reset MOSFET 6
The gate electrode 4 serves as a reset gate (hereinafter, referred to as "RSG") as a reset control unit for controlling the reset charge discharging unit.

The source of the JFET 62 of each pixel 60 is a vertical source line 70-1, for each column of the matrix arrangement.
70-2 are commonly connected. JFE of each pixel 60
The drain of T62 and the cathode side of the BPD 61 are commonly connected to all pixels by a wiring or a diffusion layer not shown, and are connected to a power supply voltage 65. In addition, each pixel 60
The anode side of the BPD 61 and the control region of the JFET 62 are connected to the source or the drain of the transfer MOSFET 63, respectively.

The transfer gate (gate electrode) of the transfer MOSFET 63 has gate lines 72-1 and 72 scanned by the vertical scanning circuit 71 for each row of the matrix arrangement.
-2, and when the drive pulses φ _TG1 and φ _TG2 sent from the vertical scanning circuit 71 are applied, the transfer MO is transferred.
The SFET 63 is designed to operate sequentially for each row.

The reset gates (gate electrodes) of the reset MOSFET 64 are gate lines 73-1 and 7-7 connected to the vertical scanning circuit 71 for each row of the matrix arrangement.
When the drive pulses φ _RSG1 and φ _RSG2 (both are the same pulse) which are commonly connected to 3-2 and are sent from the vertical scanning circuit 71 are applied, the reset MOSFETs 64 are operated simultaneously in all rows. .

The reset drain (drain electrode) of the reset MOSFET 64 is line 74-scanned by the vertical scanning circuit 71 for each row of the matrix arrangement.
1, 74-2 are commonly connected to which drive pulses φ _RSD1 and φ _RSD2 sent from the vertical scanning circuit 71 are applied. Drive pulses φ _RSD1 and φ _RSD2 are transfer MOSFETs
It is for controlling the gate potential of the JFET 62 via 63.

The vertical source lines 70-1, 70-2
On the other hand, on the other hand, for each column, the optical signal output transfer MO
SFET 75-1, 75-2 and MO for dark signal output transfer
It is connected to one electrode of the optical signal output storage capacitors 77-1 and 77-2 and the dark signal output storage capacitors 78-1 and 78-2 via the SFETs 76-1 and 76-2, and is read out horizontally. Selection MOSFET 79-
The optical signal output line 81 and the dark signal output line 82 are connected via 1, 79-2, 80-1, and 80-2, respectively. These signal output lines 81 and 82 have parasitic capacitance 8
There are 3,84. Also, these signal output lines 8
Output amplifiers 85 and 86 are connected to one of the terminals 1 and 82.

Further, on the optical signal output line 81 and the dark signal output line 82, horizontal read reset MOSFETs 87-1 for resetting the video signal to be sent,
The drain of 87-2 is connected. The sources of the horizontal read reset MOSFETs 87-1 and 87-2 are
The optical signal output storage capacitors 77-1 and 77-2 and the dark signal output storage capacitors 78-1 and 78-2 are connected to the other electrodes and grounded. The gate electrodes of the horizontal read reset MOSFETs 87-1 and _87-2 are commonly connected, and when the drive pulse φ _RSTH is applied to the gate electrodes, the horizontal read reset MOSFET ₈ is provided.
7-1 and 87-2 are designed to operate.

The horizontal read selection MOSFET 79
The horizontal selection signal lines 89 and 90 connected to the horizontal scanning circuit 88 are commonly connected to the respective gate electrodes of -1, 79-2, 80-1, and 80-2 for each column, and the horizontal scanning circuit Horizontal reading is controlled by the horizontal drive pulses φ _H1 and φ _H2 sent from 22. The MOSFETs 79-1 and 79-2 are for reading an optical signal, which supplies the optical signal output temporarily stored in the optical signal output storage capacitors 77-1 and 77-2 to the optical signal output line 81. MOSFET 80-1, 80-2
Is for reading the dark signal, which supplies the dark signal output once accumulated in the dark signal output accumulating capacitors 78-1 and 78-2 to the dark signal output line 82.

The optical signal output transfer MOSFET 75-
Each of the gate electrodes 1 and 75-2 is commonly connected to the gate line 91, and the dark signal output transfer MOSFET 76-
Each gate electrode of 1 and 76-2 is commonly connected to a gate line 92, and when drive pulses φ _TS and φ _TD are applied to these gate electrodes, optical signal output transfer MOSFETs 75-1 and 75-2.
And dark signal output transfer MOSFETs 76-1, 76-2
Operate alternately in a predetermined order.

The vertical source lines 70-1, 70-2
On the other hand, on the other hand, the drains of the vertical source line reset MOSFETs 93-1 and 93-2 and the bias current source (source follower read current source) 94 for each column.
-1, 94-2, the source of the vertical source line resetting MOSFETs 93-1 and _93-2 is supplied with the power supply voltage V _RSTV , and the bias current source _94-2 is connected.
The power supply voltage V _CS is supplied to 1, 94-2.

The vertical source line reset MOS
A reset pulse φ _RSTV is supplied to the gate electrodes of the FETs 93-1 and 93-2. When the reset pulse φ _RSTV goes high, the vertical source line reset MO is reset.
The SFETs 93-1 and 93-2 become conductive, and the vertical source lines 70-1 and _70-2 can be reset to the voltage V _RSTV .

Next, the operation of the solid-state imaging device according to the present embodiment will be described with reference to the pulse timing chart shown in FIG. Note that, in FIG. 6, only the drive pulse relating to the read operation of the pixels 60 in the first row is shown, and the drive pulses φ _TG2 , φ _RSG2 , φ _RSD2 are omitted.

At time t ₁ , the drive pulse φ _RSG1 is at the low level and the drive pulse φ _RSD1 is at the high level.
The resetting MOSFET 64 of each pixel 60 in the first row becomes conductive, and the gate potential of the _{JFET 62} is initialized to the high level of the drive pulse φ _RSD1 .

At time t ₂ , drive pulses φ _TD , φ
_{Since RSTV} is at high level, dark signal output transfer MOS
The FETs 76-1 and 76-2 and the vertical source line reset MOSFETs 93-1 and 93-2 are turned on, and the potentials of the dark signal output storage capacitors 78-1 and 78-2 are reset to V _RSTV .

At time t ₃ , the drive pulse φ _RSTV is at the low level and the drive pulse φ _TD is at the high level, so that the vertical source line reset MOSFETs 93-1 and 93 are provided.
-2 is non-conducting state and dark signal output transfer MO
The SFETs 76-1 and 76-2 are in the conductive state, and the JFE
T62 performs the source follower operation of the dark signal, and the dark signal output is charged in the dark signal output storage capacitors 78-1 and 78-2.

At time t ₄ , the drive pulse φ _RSTV is at the high level and the drive pulse φ _TD is at the low level, so that the vertical source line reset MOSFETs 93-1 and 93 are provided.
-2 becomes conductive, and a MO for dark signal output transfer
The SFETs 76-1 and 76-2 are turned off, and the potentials of the vertical source lines 70-1 and _70-2 are reset to V _RSTV . Further, at time t ₄ , drive pulse φ _TG1
Is at a low level, the transfer MOSFET 63 of each pixel 60 on the first row becomes conductive, and the charge photoelectrically converted by the BPD 61 of each pixel 60 on the first row becomes the JFET 6
2 is transferred to the gate.

At time t ₅ , the drive pulse φ _RSTV is at the high level and the drive pulse φ _TS is at the high level. Therefore, vertical source line reset MOSFETs 93-1 and 93 are provided.
-2 and optical signal output transfer MOSFETs 75-1 and 75
-2 becomes conductive, and the optical signal output storage capacitor 7
The potentials _7-1 and _77-2 are reset to V _RSTV .

Since the drive pulse φ _RSTV is at the low level and the drive pulse φ _TS is at the high level at time t ₆ , the vertical source line reset MOSFETs 93-1 and 93 are provided.
-2 is in a non-conducting state and an optical signal output transfer MO
SFETs 75-1 and 75-2 are in the conductive state, and JFE
T62 performs the source follower operation of the optical signal, and the optical signal output is charged in the optical signal output storage capacitors 77-1 and 77-2.

At time t ₇ , the drive pulse φ _RSTH becomes high level, and the horizontal read reset MOSFET is
87-1 and 87-2 become conductive, and the potentials of the optical signal output line 81 and the dark signal output line 82 are reset.

At time t ₈ , the horizontal drive pulse φ _H1 becomes high level and the horizontal read selection MOSFET 7
9-1 and 80-1 become conductive, and the optical signal output storage capacitor 77-1 and the dark signal output storage capacitor 7
From 8-1, the optical signal output and the dark signal output of the pixel 60 of the first row and the first column are capacity-divided with the parasitic capacitances 83 and 84, respectively, and output to the optical signal output line 81 and the dark signal output line 82. And output as voltage outputs V _OS and V _OD to the outside of the device via the output amplifiers 85 and 86.

At time t _{9 and} time t ₁₀ , the same operation as at time t _{7 and} time t ₈ is repeated for the optical signal output and the dark signal output of the pixel 60 in the next column of the first row, and the first operation is performed.
The signals of the pixels 60 in each column of the row are sequentially read out of the element.

The readout operation for each pixel 60 in the first row described above is similarly performed for each pixel 60 in the second row.

Next, the structure of the unit pixel of the solid-state imaging device according to the present embodiment will be described with reference to FIGS. 7 and 8.

FIG. 7 is a schematic plan view of the unit pixel 60 in the solid-state image pickup device according to this embodiment. 8 is a schematic sectional view of a predetermined portion in FIG. 7, (a) is a sectional view taken along the line BB ′ in FIG. 7, and (b) is a sectional view taken along the line CC ′ in FIG. 7. is there.

This unit pixel is, as already described, B
PD61, JFET62, transfer MOSFET (p
Channel MOSFET) 63 and reset MOSFE
T (p-channel MOSFET) 64.

In FIGS. 7 and 8, 100a is BP.
It is a first layer aluminum wiring for supplying a power supply voltage 65 (see FIG. 5) to the D61 and the JFET 62. 100b is
This is a first-layer dummy aluminum line for forming the same step structure as the first-layer aluminum wiring 100a. 101 is a transfer M
The transfer MOSFE of each pixel (horizontal pixel) 60 in the same row also serves as the gate electrode (transfer gate) of the OSFET 63.
A polysilicon wiring (corresponding to the gate lines 72-1 and 72-2 in FIG. 5) commonly connecting the gate electrodes of T63. Reference numeral 102 also serves as a gate electrode (reset gate) of the resetting MOSFET 64 and commonly connects the gate electrode of the resetting MOSFET 64 of each pixel 60 in the same row to a polysilicon wiring (gate line 73-1 in FIG. 5,
73-2). 103 is a reset MOS
The second layer aluminum wiring for controlling the gate potential of the JFET 62 via the FET 64 (line 74-1 in FIG. 5,
74-2), and the resetting MOSFET 64
It also serves as one of the source / drain electrodes. 104
Is a first-layer aluminum wiring that also serves as the other source / drain electrode of the reset MOSFET 64 and is connected to the second-layer aluminum wiring 103. Reference numeral 105 is a through hole for connecting the first layer aluminum wiring 104 and the second layer aluminum wiring 103. Reference numeral 106 also serves as the source electrode of the JFET 62, and JF of each pixel (vertical pixel) 60 in the same column.
First-layer aluminum wiring for commonly connecting the source electrodes of the ET62 (vertical source lines 70-1, 70-2 in FIG. 5)
Is equivalent to).

Further, 107 is a p-type substrate and 108 is an n-type well. 109 is an n ⁺ pixel separation region,
It also serves as the drain electrode of the ET 62 and is connected to the first-layer aluminum wiring 100a through the contact hole 110. 111 is a p-type gate region of JFET 62 (JFE
(T62 control region), 112 is an n-type channel region of the JFET 62, and 113 is an n ⁺ region for making contact with the source electrode of the JFET 62 (also serving as the first-layer aluminum wiring 106). P-type gate region 1 of JFET 62
11 also serves as one of the source / drain regions of the transfer MOSFET 63, and also has the reset MOSFET 6
4 also serves as one of the source / drain regions. 114
Is a p-type region forming the other source / drain region of the resetting MOSFET 64. Reference numeral 115 denotes an n-type region between the source and drain of the reset MOSFET 64. 116 is an n ⁺ region continuous with the n ⁺ pixel separation region, 1
Reference numeral 17 is a p-type region, and the BPD 61 is formed by a PN junction formed by these. As can be seen from FIG.
The BPD 61 is a buried photodiode having a vertical overflow structure. Part of the p-type region 117 also serves as the other source / drain region of the transfer MOSFET 63. Reference numeral 118 is a contact hole for connecting the first-layer aluminum wiring 104 and the p-type region 114. Reference numeral 119 denotes the first layer aluminum wiring 106 and the n ⁺ region 11
3 is a contact hole for connecting with 3.

In the solid-state imaging device according to the present embodiment, as shown in FIG. 8, the edge portion of the polysilicon wiring 101 which is the gate electrode of the transfer MOSFET 63 which is an element having the MIS gate structure in the unit pixel 60 is reversed. A reset MOS which is an element having a taper structure and having a MIS gate structure in the unit pixel 60.
The edge portion of the polysilicon wiring 102 which is the gate electrode of the FET 64 has an inverse taper structure. The source / drain regions of the MOSFETs 63 and 64 are self-aligned to have an LDD structure.

In the pixel structure of the solid-state image pickup device according to this embodiment, the p-type diffusion in which ion implantation is performed using the polysilicon 101 and 102 as a mask is a relatively low concentration of ion implantation, so that a crystal defect dislocation network is generated. However, even if a crystal defect dislocation network is generated, it does not become a dark current generation source.

Although not shown in the drawing, a horizontal read selection MOS in the solid-state image pickup device according to the present embodiment.
The FETs 79-1, 79-2, 80-1, 80-2 have a structure similar to that shown in FIG.

Although the respective embodiments of the present invention have been described above, the present invention is not limited to these embodiments. For example, in the present invention, the pixel configuration, the readout circuit, and the like are not limited to the configurations described in the above embodiments, and the present invention can be applied to various solid-state imaging devices.

[0121]

As described above, according to the present invention,
Fixed pattern noise due to white defects can be suppressed, and S / N can be improved.

Further, according to the present invention, it is possible to prevent a decrease in signal output and improve S / N.

[Brief description of drawings]

FIG. 1 is a diagram showing a main part of an element in a solid-state imaging device according to an embodiment of the present invention, FIG. 1 (a) is a schematic cross-sectional view thereof, and FIG. 1 (b) is in FIG. 1 (a). FIG. 6 is an enlarged view of a white defect defect due to a crystal defect dislocation network in which a part of FIG.

FIG. 2 is a schematic cross-sectional view showing an example of a manufacturing process of the element shown in FIG.

FIG. 3 is a schematic cross-sectional view showing the manufacturing process of the device shown in FIG. 1 following FIG. 2;

FIG. 4 is a diagram showing a horizontal readout selection MOSFET in a solid-state imaging device according to an embodiment of the present invention.
4A is a schematic plan view thereof, and FIG. 4B is a sectional view taken along the line AA ′ in FIG.

FIG. 5 is a circuit diagram showing a solid-state imaging device according to another embodiment of the present invention.

6 is a pulse timing chart for explaining a circuit-like operation of the solid-state imaging device shown in FIG.

7 is a schematic plan view of a unit pixel in the solid-state imaging device shown in FIG.

8 is a schematic cross-sectional view of a predetermined portion in FIG.
7A is a sectional view taken along line BB ′ in FIG. 7, and FIG. 8B is FIG.
FIG. 9 is a sectional view taken along the line CC ′ of FIG.

FIG. 9 is a circuit diagram showing a conventional solid-state imaging device.

10 is a diagram showing a main part of an element in the conventional solid-state imaging device shown in FIG. 9, FIG. 10 (a) is a schematic cross-sectional view thereof, and FIG. 10 (b) is a schematic cross-sectional view of FIG. 10 (a). It is explanatory drawing about the white flaw defect by the crystal defect dislocation network which expanded a part.

[Explanation of symbols]

 42 Gate Insulating Film 43 Gate Electrode 43a Tapered Surface 44 Source / Drain Region 44a Relatively High Concentration Impurity Region 44b Relatively Low Concentration Impurity Region 45 Crystal Defect Dislocation Network

Claims (8)

[Claims] 1. A solid-state imaging device including an element having a MIS gate structure, wherein the thickness of an edge portion of a gate electrode in the MIS gate structure is gradually reduced.
A solid-state imaging device, wherein a taper surface is formed on the edge portion on the gate insulating film side in the MIS gate structure. 2. The solid-state image pickup device according to claim 1, wherein the element having the MIS gate structure constitutes at least a part of a pixel. 3. A pixel includes an embedded photodiode for generating and accumulating charges according to incident light, an amplification junction field effect transistor for generating an amplified output according to the charges received in a control region, and the embedded photo. A transfer MIS field effect transistor that transfers the charge generated and accumulated in the diode to the control region of the junction field effect transistor, and a charge transferred to the control region of the amplification junction field effect transistor. An MIS field effect transistor for resetting, wherein the element having the MIS gate structure is
The solid-state imaging device according to claim 2, wherein the solid-state imaging device is at least one of an S-type field effect transistor and the resetting MIS type field effect transistor. 4. The device having the MIS gate structure forms a part of a read circuit.
4. The solid-state imaging device according to any one of 3 to 3. 5. The readout circuit supplies an optical signal output accumulating capacitor for temporarily accumulating an optical signal output from a pixel, and an optical signal output accumulated in the optical signal output accumulating capacitor to an optical signal output line. 5. The solid-state imaging device according to claim 4, further comprising an MIS field effect transistor for reading an optical signal, wherein the element having the MIS gate structure is the MIS field effect transistor for reading an optical signal. 6. The read circuit supplies a dark signal output storage capacitor for temporarily storing a dark signal output from a pixel, and a dark signal output stored in the optical signal output storage capacitor to a dark signal output line. 6. A solid-state imaging device according to claim 4, further comprising a dark signal reading MIS field effect transistor, wherein the element having the MIS gate structure is the dark signal reading MIS field effect transistor. . 7. The device having the MIS gate structure has a source region and a drain region formed in self-alignment with the gate electrode, and the source region and the drain region have an LDD structure. Claim 1
7. The solid-state imaging device according to any one of claims 1 to 6. 8. A step of forming a gate insulating film on a semiconductor substrate of the first conductivity type, a step of forming a gate electrode on the gate insulating film, and implanting impurities into the semiconductor substrate using the gate electrode as a mask. And a step of forming a source region and a drain region of the second conductivity type. A method for manufacturing a solid-state imaging device, comprising forming a taper surface on the gate insulating film side of the MIS gate structure in the edge portion so as to be extremely thin.