JPH0992723A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress fluctuation of skews by detecting the fluctuation of the skew between internal clocks and increasing the load on an internal clock having relatively advanced phase thereby regulating the phase between the distributed internal clocks. SOLUTION: A skew fluctuation observation circuit 14 outputs a detection signal corresponding to an internal clock having relatively an advanced phase among a predetermined number of internal clocks distributed from buffers 22 on the same stage of a clock tree 12 as an active state. A load control circuit 16 increases the load on an internal clock having relatively an advanced phase among a set of four internal clocks on the same stage. A sequence sustaining circuit 18 operates detection circuits 14 and load control circuits 16 sequentially starting from one close to the clock supply of the clock tree 12 and locks that state. According to the circuitry, fluctuation of the skew can be suppressed between internal clocks and erroneous function of the internal circuit can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a clock tree that distributes clocks, and more particularly to a semiconductor device that reduces skew variations among clocks distributed by the clock tree.

[0002]

2. Description of the Related Art The circuit scale of an LSI has been increasing year by year with the miniaturization and high integration of the LSI, and the operation speed has been increased. For this reason, the number of flip-flops or latches that require a clock increases, and the oscillation frequency thereof tends to increase. By the way, as the clock, a so-called clock tree 12 as shown in, for example, FIG. 5 is used in order to improve the driving capability and the operating speed when the number of connected cells increases. That is, the buffer 22 distributes a predetermined number of clocks to the internal circuit.

However, if the clocks are distributed to a predetermined number, even when the circuit is designed, it is assumed that the number of stages of buffers until the respective clocks are distributed and the load applied to each clock are the same. Also, during automatic placement and routing, the skew between clocks varies due to variations in the wiring length of each clock, that is, the arrival time at the end of each clock is shifted in units of a few nanometers. If the clock oscillation frequency is high, the internal circuit may malfunction.

Conventionally, in order to solve this problem, for example, when the internal circuits are automatically arranged and wired, the automatic wiring is performed so that the loads of the respective clocks are the same. The clock wiring is meshed over the entire LSI chip. -Like wiring, thickening the trunk line of the clock and branching from it to the branch line, after automatic placement and wiring, add extra wiring to the part where the clock load is uneven to make each clock load uniform Thus, the malfunction of the internal circuit is prevented by reducing the variation of the skew between the clocks.

However, even if a layout mask pattern is created so as to reduce the skew between the clocks before manufacturing the LSI chip, L
Skew between clocks may increase due to variations in the process of manufacturing the SI chip, and capacitance and resistance that cannot be predicted by simulation before manufacturing. Further, when the mesh-shaped clock wiring or the thick clock trunk line is used, the ratio of the clock wiring to the area of the LSI chip becomes high, and there is a problem that the area cost increases.

[0006]

In view of the problems based on the above-mentioned prior art, the object of the present invention is to distribute a semiconductor device using a clock tree by the clock tree even after the LSI chip is manufactured. It is an object of the present invention to provide a semiconductor device capable of reducing the variation in skew between clocks.

[0007]

To achieve the above object, the present invention distributes an external clock or an internal clock source to a predetermined number of internal clocks, and further repeatedly distributes the internal clock to a predetermined number of internal clocks. Clock tree, a skew variation observing circuit provided in the predetermined internal clock to detect a variation in skew between the internal clocks, and a predetermined internal clock provided in the predetermined internal clock. Of the load variation circuit for increasing the load of the advanced internal clock, and in the skew variation observing circuit, the detection state is sequentially fixed from the one provided for the external clock or the internal clock close to the internal clock source, And a sequence maintaining circuit for fixing the load of the internal clock by the increasing / decreasing circuit. It is to provide a location.

[0008]

According to the semiconductor device of the present invention, the skew of the internal clocks distributed by the clock tree is detected, and the load of the internal clock whose phase is relatively advanced is increased. Is adjusted to reduce the skew variation. Therefore, according to the semiconductor device of the present invention, since the phase of the internal clock is adjusted by actually operating the circuit, it is possible to reduce the skew variation between the internal clocks even after the LSI chip is manufactured. Therefore, the malfunction of the internal circuit can be prevented.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings. FIG. 1 is a configuration circuit diagram of an embodiment of a semiconductor device of the present invention. The semiconductor device 10 of the illustrated example includes a clock tree 12, a skew variation observing circuit 14, a load increasing / decreasing circuit 16, and an order maintaining circuit 18.

Here, the clock tree 12 distributes a clock (hereinafter referred to as an external clock) input from the outside of the LSI chip to a predetermined number of clocks (hereinafter referred to as an internal clock) supplied to an internal circuit. Therefore, it has an IO (input / output) buffer 20 and a plurality of buffers 22. The clock supply source is not limited to the external clock input via the IO buffer, but may be a clock generation source (generator) provided in the LSI chip.

The clock supply source is input via the IO buffer 20 and distributed to the four internal clocks by the four first-stage buffers 22. The four internal clocks in the first stage are further distributed to four internal clocks per set by the four buffers 22 in the next stage, and so on. Similarly, each internal clock is distributed to four by the four buffers 22. As a result, a predetermined number of internal clocks are generated. The number of internal clocks per set and the total number thereof are not particularly limited.

The skew variation observing circuit 14 activates the detection signal corresponding to the internal clock whose phase is relatively advanced among the predetermined number of internal clocks distributed by the buffer 22 at the same stage of the clock tree 12. N, which is provided as, for example, four internal clocks of the same set in the same stage as one unit.
It has an OR gate 24 and a delay buffer 26 and a latch 28 which are respectively provided for the same set of four internal clocks in the same stage.

The same set of four internal clocks at the same stage are input to the NOR gate 24 and each delay buffer 26. The output of each delay buffer 26 is input to the data input terminal D of each latch 28, and the output of the NOR gate 24 is the output of all the latches 28 provided for the same set of four internal clocks in the same stage. It is input to the enable input terminal G. The output terminal Q of each latch 28 outputs a detection signal corresponding to each internal clock.

In the skew variation observing circuit 14, the load increasing / decreasing circuit 16 is arranged in the same stage in accordance with each detection signal output from the latch 28 provided for each of the four internal clocks in the same set in the same stage. Of the four internal clocks of the same set, the load of the internal clock whose phase is relatively advanced is increased, and the N-type MO is provided for each of the four internal clocks of the same set in the same stage.
It has an S-transistor (hereinafter referred to as NMOS) 30 and a capacitive element 32.

Each of the four internal clocks of the same set in the same stage is connected to the drain of each NMOS 30, and the gate of each NMOS 30 has the same set of the same set in the same stage in the skew variation observing circuit 14. Four
The respective detection signals output from the latches 28 provided for the internal clocks of the book are input. One terminal of each capacitance element 32 is connected to each NMOS 3
0 source, the other terminal is grounded.

The sequence maintaining circuit 18 is provided with, for example, the skew variation detecting circuit 14 and the load increasing / decreasing circuit 1 which are provided with the same set of four internal clocks in the same stage as one unit.
6 is for sequentially operating from the side closer to the clock supply source of the clock tree 12 and fixing the state thereof, which is cleared by, for example, a reset signal, and sequentially shifts the high level every clock after the reset is released. It is composed of the shift register 34.

The shift register 34 is used for the clock tree 1
There are as many output signals as the number of stages of the two buffers 22, and each of the output signals has four output signals of the same set in the same stage.
It is commonly input to the NOR gate 24 of the skew variation observation circuit 14 provided for each internal clock of the book. As the clock input to the shift register 34, for example, a clock supply source may be used, or one of the internal clocks at the predetermined stage may be used.

The semiconductor device 10 of the present invention is basically constructed as described above. In the illustrated example, the skew variation observing circuit 14 and the load increasing / decreasing circuit 16 provided in the four internal clocks in the first stage of the clock tree 12 are shown.
However, as shown in the conceptual diagram of FIG.
The skew variation observing circuit 14 and the load increasing / decreasing circuit 16 are similarly applied to the four internal clocks of all the groups of the second and subsequent stages.
Needless to say, may be provided partially or entirely.

The skew variation observing circuit 14 and the load increasing / decreasing circuit 16 are not necessarily the same set of 4 in the same stage.
For example, as shown in the configuration circuit diagram of FIG. 3, only the skew variation observing circuit 14 is provided for the four internal clocks in the first stage, as shown in the configuration circuit diagram of FIG.
Load increase / decrease circuit 1 for 4 internal clocks of 4 sets after the first stage
Only 6 may be provided, and each detection signal output from the latch 28 of the skew variation observing circuit 14 may be commonly input to the gates of the four NMOSs 30 of the load increasing / decreasing circuits 16 of each set. .

Next, the operation of the semiconductor device 10 of the present invention will be described with reference to the timing chart shown in FIG. In the semiconductor device 10 shown in FIG. 1, the same reference numerals are assigned to the respective signals in the timing chart of FIG.

In the semiconductor device 10 of the present invention, first, the reset signal is input and all the output signals of the sequence maintaining circuit 18 are cleared to the low level. That is, the NOR gate 24 of the skew variation observing circuit 14 is brought into an operable state. At this time, if the four internal clocks input to the NOR gate 24 are all at the low level, their outputs are at the high level, and all the latches 28 whose outputs are input to the enable input terminal G are turned on.

After the reset is released, the clock supply source is input to the four buffers 22 in the first stage of the clock tree 12 and distributed to the four internal clocks. At this time, the four internal clocks in the first stage are delayed according to their respective loads, as shown in the timing chart of FIG. 4, for example. The four internal clocks in the first stage are further delayed by the delay buffers 26 and input to the data input terminals D of the latches 28.

When the internal clock with the most advanced phase among the four internal clocks in the first stage rises, the NOR gate 24 of the skew variation observing circuit 14 becomes low level, and this output is input to the enable input terminal G. All 28 are turned off. At this time, the delay buffer 2
Among the four internal clocks delayed by 6, the latch 28 holds the high level for the internal clock whose phase is relatively advanced, and conversely, the latch 28 holds the low level for the internal clock whose phase is delayed. It

Here, the output delay time of the NOR gate 24 and the output delay time of the delay buffer of the skew variation observing circuit 14 are the detection accuracy of the skew variation between the four internal clocks, that is, the detectable skew. Determine the minimum time for the variability of. That is, in order to hold only the high level of the internal clock whose phase is relatively advanced by the fall of the NOR gate 24, the output delay time of the delay buffer is shorter than the output delay time of the NOR gate 24. In a small range, and NOR gate 2
It is necessary to have a value as close as possible to the output delay time of 4.

When the latch 28 holds the high level,
The output signal, that is, the NMOS 30 of the load increasing / decreasing circuit 16 to which the detection signal is input to the gate is turned on. At this time, the capacitive element 32 connected to the source of the NMOS 30
Is electrically connected to the internal clock connected to the drain of the NMOS 30, the internal clock electrically connected to the capacitive element 32 is delayed for a predetermined time by increasing its load by the capacitance of the capacitive element 32. The phase of the internal clock having a relatively slow phase is adjusted.

Here, the capacitive element 32 of the load adjusting circuit 16
The capacitance value of determines the adjustment accuracy of the skew variation between the four internal clocks, that is, the time for delaying the internal clock with a relatively advanced phase. That is, in order to synchronize the phases of the four internal clocks, the capacitance value of the capacitive element 32 is set only for the detection accuracy in the skew variation observing circuit 14, that is, for a time substantially equal to the minimum time of detectable skew variation. It is preferable to have a capacitance value capable of delaying the internal clock whose phase is relatively advanced.

As described above, after the phase of the internal clock whose phase is relatively advanced is adjusted by the rising edges of the four internal clocks at the first stage, the output signal Q0 of the sequence maintaining circuit 18 is, for example, the internal clock. Rises to a high level after a predetermined delay time due to the same rise. At this time,
The output of the NOR gate 24 of the skew variation observing circuit 14 to which the output signal Q0 is input is fixed at a low level, and the adjustment state of the internal clock by the load adjusting circuit 16 is fixed until the reset signal is input next. .

Similarly, the phases of the internal clocks distributed by the buffers 22 at the second and subsequent stages of the clock tree 12 are adjusted. The semiconductor device 10 of the present invention basically operates as described above.

[0029]

As described in detail above, the semiconductor device of the present invention detects variations in skew between internal clocks and increases the load of the internal clocks that have a relatively advanced phase, thereby increasing the internal clock. It is to adjust the phase between them. Therefore, according to the semiconductor device of the present invention, L
By actually operating the SI chip after it is manufactured, it is possible to reduce the variation in the skew between the internal clocks and prevent the malfunction of the internal circuit. For this reason, it is possible to deal with process variations that cannot be known until the LSI chip is manufactured, and capacitance, resistance, cell delay, input rounding, etc., which cannot be predicted by simulation before manufacturing.

[Brief description of drawings]

FIG. 1 is a configuration circuit diagram of an embodiment of a semiconductor device of the present invention.

FIG. 2 is a conceptual diagram of an embodiment of a semiconductor device of the present invention.

FIG. 3 is a configuration circuit diagram of another embodiment of the semiconductor device of the present invention.

FIG. 4 is a timing chart of an example for explaining the operation of the semiconductor device of the present invention.

FIG. 5 is a configuration circuit diagram of an example of a clock tree.

[Explanation of symbols]

 10 semiconductor device 12 clock tree 14 skew variation observing circuit 16 load increasing / decreasing circuit 18 sequence maintaining circuit 20 IO (input / output) buffer 22 buffer 24 NOR gate 26 delay buffer 28 latch 30 N-type MOS transistor (NMOS) 32 capacitive element 34 shift register

Claims (1)

[Claims] 1. A clock tree that distributes an external clock or an internal clock source to a predetermined number of internal clocks, and repeatedly distributes the internal clock to a predetermined number of internal clocks, and a clock tree provided in the predetermined internal clocks. A skew variation observing circuit for detecting variation in skew between clocks, and provided in the predetermined internal clock,
A load increasing / decreasing circuit for increasing the load of the internal clock whose phase is relatively advanced among the internal clocks, and one provided in the external clock or an internal clock close to the internal clock source in the skew variation observing circuit And a sequence maintaining circuit that sequentially fixes the detection states and fixes the load of the internal clock by the load increasing / decreasing circuit.