JPH0992130A - Electric charge generator, and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electric charge generator in which electric charges can be easily generated by a driving voltage of several tens. SOLUTION: A drive line 3 comprising a P-well layer is provided on an n-type semiconductor substrate 1, and an N<+> layer 4 is diffused and formed on the surface of the P-well layer driving line 3. A p-n junction diode formed of the P-well layer driving line 3 and the N<+> layer 4 is set as an electron emitting part, and a backward bias is applied to the diode to cause avalanche breakdown, thereby electrons or charges are emitted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge generator used in an electrostatic image forming device or a display device used in electrostatic printing, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, a charge generation control element utilizing corona discharge has been used as a method for forming a latent image by electrostatic charges on a dielectric recording body by the principle of transferring charges directly onto the dielectric recording body and depositing them. Is disclosed in Japanese Patent Publication No. 2-62862, and such a charge generation control element is
The method of forming high definition using semiconductor fine processing technology,
It is proposed in Japanese Patent Application No. 6-288580, which is the application of the present applicant.

FIG. 22 is a sectional view showing a part of a configuration example of a conventional charge generator for an electrostatic image forming apparatus. In FIG. 22, reference numeral 100 indicates one charge generation control element, and the charge generator is configured by arranging a large number of charge generation control elements 100 one-dimensionally or two-dimensionally. The charge generation control element 100 includes a substrate 101 made of quartz or glass,
A line electrode 102 made of metal, a first insulating film 103,
Finger electrode 104 made of metal and second insulating film 105
And the screen electrode 106, and the finger electrode
Finger holes 107 and screen holes 108 are formed in 104 and screen electrode 106, respectively.

The charge generation control device 100 having the above-described configuration
Are formed by forming a resist pattern on a metal film formed by a method such as a sputtering method or a vacuum evaporation method, and then removing portions not covered by the resist pattern by etching. For the first insulating film 103, a material having a high electrostatic withstand voltage such as a silicon oxide film or a silicon nitride film formed by a method such as a CVD (chemical vapor deposition) method or a sputtering method is used. A resin having high heat resistance such as polyimide is used for the second insulating film 105.

Next, the operation of the thus-configured charge generation control device 100 will be described. In FIG.
By applying an AC voltage between the line electrode 102 and the finger electrode 104 which are arranged with the first insulating film 103 sandwiched between them, electric charges are generated on the side wall of the finger hole 107 and on the first insulating film 103 due to a corona discharge phenomenon. Swarms occur. Negative charges having a large mobility in the charge group are used for latent image formation. The second insulating film 105 is opposed to the finger electrode 104.
When a potential more positive than the potential applied to the finger electrode 104 is applied to the screen electrode 106 formed with the
It is extracted from the screen hole 108 formed in 106. The negative charges extracted from the screen holes 108 are accelerated toward a drum (not shown), which is a dielectric recording body, and are deposited on the drum to form a latent charge image. Conversely, when a negative potential is applied to the screen electrode 106 with respect to the finger electrode 104, extraction of negative charges from the screen hole 108 is blocked, and a latent image is not formed on the drum.

[0006]

However, the conventional charge generator for the electrostatic image forming apparatus has the following problems. That is, when driving the charge generator, an AC voltage of 1 KV or more must be applied between the first insulating films having a thickness of several microns, which causes the greatest problem of increasing the driving circuit and the power supply voltage. To do. When driving the conventional charge generator shown in FIG. 22, a high electric field of several MV / cm is generated inside the first insulating film, and the first insulating film, which is the bottom surface in the finger hole, is also generated. The surface of the film 103 is exposed to the plasma generated by the corona discharge,
There is a problem that the surface layer is scraped as shown by 109. Furthermore, in order to manufacture the conventional charge generator shown in FIG. 22, a large number of film forming steps and a large number of steps such as etching steps of each film are required, and heat, stress, etc. in each film forming step are required. Causes the deterioration of the insulating film, which causes a decrease in yield.

The present invention has been made to solve the above problems of the conventional charge generator for an electrostatic image forming apparatus.
An object of the present invention is to provide a highly reliable charge generator capable of downsizing a drive circuit and a power supply voltage source, and a manufacturing method thereof. To describe the purpose of each claim, claims 1, 2,
An object of each of the inventions 5 to 7 is to provide a charge generator capable of easily generating charges only by applying a driving voltage of several tens of volts. Each of the inventions described in claims 3 and 4 provides a method of manufacturing a charge generator capable of easily manufacturing a charge generator capable of easily generating charges with a driving voltage of several tens of volts. To aim. It is an object of the present invention to provide a charge generator in which charge generation control elements can be easily formed in an array using semiconductor technology. Claims 9 and 10
An object of each of the inventions described is to provide an electrostatic image forming device or a display device that can be easily driven with a driving voltage of several tens of volts.

[0008]

In order to solve the above-mentioned problems, the invention according to claim 1 has the following advantages:
In a charge generator having charge generation control elements having a function of discharging electrons or charges arranged one-dimensionally or two-dimensionally, the charge generation control element is formed on a semiconductor substrate, and the charge generation control element is formed. The electron-emitting portion is formed of a diode having a P-N junction, and a reverse bias is applied to the diode to emit electrons or charges, and the invention according to claim 2 In the charge generator according to Item 1, the N layer of the diode having the P-N junction is formed of a diffusion layer of about several tens of liters formed on the pole surface of the semiconductor substrate.

As described above, the electron emission portion of the charge generation control element is composed of the P-N junction diode, so that several tens of volts are applied.
A reverse electric field causes avalanche breakdown due to a high electric field in the P-type semiconductor region. Hot electrons having high energy generated by this fly out of the very thin N-type layer and generate charges (electrons). Therefore, with the above structure, in order to generate electrons or charges from the conventional charge generation control element, 1 KV is required.
Although the above driving voltage is required, electrons or charges can be easily discharged into the atmosphere or vacuum with an applied voltage of several tens of volts. Further, the insulating film is not scraped due to corona discharge, stable electric charges can be generated, and reliability can be greatly improved.

According to a third aspect of the present invention, in the method of manufacturing a charge generator according to the first or second aspect, the N layer of the diode having the P-N junction is formed by diffusion from polycrystalline silicon. The invention according to claim 4 is the method for manufacturing a charge generator according to claim 1 or 2, wherein the N layer of the diode having the P-N junction is formed by an ion implantation method. This makes it possible to easily manufacture a charge generator that can easily generate charges with a driving voltage of several tens of volts.

According to a fifth aspect of the present invention, there is provided a charge generator in which charge generation control elements having a function of emitting electrons or charges are arranged one-dimensionally or two-dimensionally in the atmosphere or vacuum. The charge generation control element is formed on a semiconductor substrate, and the electron emission portion of the charge generation control element is composed of the semiconductor substrate and an extremely thin metal film formed on the semiconductor substrate. According to a sixth aspect of the invention, in the charge generator according to the fifth aspect, the ultrathin metal film forming the electron emitting portion is formed of platinum or gold.

By forming the electron emitting portion in this way, a Schottky diode is formed, and by applying a reverse bias of several tens of V, breakdown occurs due to a high electric field in the P semiconductor layer. The hot electrons generated by this fly out of the very thin metal film and generate charges (electrons). As a result, electrons or charges can be easily discharged into the atmosphere or vacuum with a driving voltage of about several tens of volts. Further, the Schottky diode has no delay in switching from the forward direction to the reverse direction as compared with the PN junction diode, and is therefore suitable for speeding up. Further, the insulating film is not scraped by corona discharge, stable electric charges can be generated, and reliability can be significantly improved.

According to a seventh aspect of the present invention, there is provided a charge generator comprising one-dimensionally or two-dimensionally arranged charge generation control elements having a function of emitting electrons or charges in the atmosphere or vacuum. The charge generation control element is formed on a semiconductor substrate, and the electron emission portion of the charge generation control element is composed of a bipolar transistor having a PNP or NPN structure. When the electron emitting portion is composed of a bipolar transistor as described above, breakdown occurs by applying a reverse bias of several tens of V between the extremely thin collector layer and base layer. Hot electrons generated by this flow in the direction of the collector and jump out from the surface to generate charges (electrons). Dozens of V
It is possible to easily discharge electrons or charges into the atmosphere or vacuum with the driving voltage of.

The invention according to claim 8 is the invention as claimed in claims 1, 2, and 5.
The charge generator according to any one of claims 1 to 7, further comprising a voltage application line for driving an electron emission portion of the charge generation control element, the voltage application line being arranged in an array direction of the charge generation control element. And is formed in the semiconductor substrate by diagonally intersecting each other. With this configuration,
The charge generation control elements can be easily formed in an array.

The invention according to claim 9 is the invention as claimed in claims 1, 2, and 5.
The electrostatic image forming apparatus is configured by the charge generator according to any one of items 1 to 7 and the dielectric drum arranged to face the charge generator. This makes it possible to realize an electrostatic image forming apparatus that can be easily driven with a driving voltage of several tens of volts. The invention according to claim 10 constitutes a display device with the charge generator according to any one of claims 1, 2, 5 to 7 and a fluorescent plate arranged to face the charge generator. Is. As a result, it is possible to realize a display device that can be easily driven with a drive voltage of several tens of volts.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Next, examples will be described. FIG. 1 is a sectional view showing a single charge generation control element portion of a first embodiment of a charge generator according to the present invention. In FIG. 1, 1 is an N-type semiconductor substrate, 2 is a silicon oxide formed on the surface of the N-type semiconductor substrate 1 excluding an electron emission portion, 3
Is a drive line formed of a P well layer also formed on the N-type semiconductor substrate 1, and 4 is an N ⁺ layer diffused and formed on the surface of the P well layer forming the drive line 3, forming the drive line 3. The P well layer and the N ⁺ layer 4 forming the PN junction diode forming an electron emitting portion are formed. Reference numeral 5 is polycrystalline silicon formed on the surface of the substrate so as to intersect the drive line 3 obliquely, 6 is a polyimide layer formed on the polycrystalline silicon 5, 7 is a screen electrode formed on the polyimide layer 6, 8 is a drive line 3 and polycrystalline silicon 5
It is a screen hole formed corresponding to a portion intersecting with.

[0017] In the thus configured charge generator, a PN junction diode of P-well layer and the N ⁺ layer 4 which constitutes the drive line 3 forms the electron emission portion, the N ⁺ layer 4 By forming a thin film, avalanche breakdown can be easily caused and electrons (charges) can be emitted simply by applying a reverse bias of several tens of volts.

Next, a method of manufacturing the charge generator of the first embodiment shown in FIG. 1 will be described with reference to the manufacturing process charts shown in FIGS. First, as shown in FIG. 2, an N-type semiconductor substrate 11
On the entire surface by using the LP-CVD (low pressure chemical vapor deposition), the formation temperature 780 ° C approximately in SiH ₂ Cl ₂ (dichlorosilane) NH ₃ (ammonia) reaction gas, 1000 Å approximately silicon nitride 12 Form. Next, as shown in FIG.
The resist 13 is coated, and the resist 13 is left on the drive line only by exposure and development. Next, as shown in FIG. 4, the silicon nitride 12 other than the drive line portion is removed by dry or wet etching, and the semiconductor substrate 11 is exposed on the surface.

Next, as shown in FIG. 5, after removing the resist 13, the substrate surface is cleaned (usually CN cleaning), and then an oxidation step is performed at 1000 ° C. for about 2 hours to form a silicon nitride film in the drive line portion. The portion not covered by 12a is oxidized (generally called LOCOS), and silicon oxide 14 is converted to 50%.
Form about 00Å. After that, the silicon nitride film 12a on the drive line is removed by dry or wet etching. As a result, the N-type semiconductor substrate 11 of the drive line portion is exposed on the surface.

Next, as shown in FIG. 6, by performing a thermal oxidation process called pad oxidation at 900 ° C. for about 10 minutes,
A silicon oxide film 15 of about 500 Å is formed on the driving line, and then B (boron) 16 is ion-implanted at an acceleration voltage of 80 to 150 KeV and a dose amount of 5 × 10 ¹² to 1 × 10 ¹³ cm ^-2. Inject under the conditions of. After that, the diffusion process is performed at 1000 ° C ~ 1100
This is carried out at a temperature of ° C for 10 to 20 hours to form a well layer 17 having a P type surface concentration of about 10 ¹⁶ cm ^-2 which will be a driving line.

Next, as shown in FIG. 7, the silicon oxide film 15 formed before the ion implantation is removed by a hydrofluoric acid-based cleaning agent, and then LP-CVD is used to form SiH ₄ at a formation temperature of about 620 ° C. (Silane) Reaction gas allows polycrystalline silicon 18
Form about 2000Å. Next, as shown in Figure 8, 900 °
POCl ₃ (phosphorus oxychloride) is doped at a temperature of about C to make the polycrystalline silicon 18 an N-type conductive layer. afterwards,
By heat treatment at a temperature of about 900 ° C., the N ⁺ layer 19 is diffused and formed in the extreme surface layer (several tens to several hundreds Å) of the semiconductor substrate. Subsequently, the polycrystalline silicon 18 is resist-patterned so as to obliquely intersect the P-type well layer 17 which is a drive line, and a charge generation control element is formed by dry etching. Next, as shown in FIG.
A film having excellent heat resistance such as a film having a thickness of several tens of microns is formed, and then a Ti film to be the screen electrode 21 is formed in a thickness of about 1.0 to 2.0 microns. Subsequently, the screen electrode 21 and the polyimide 20 are formed by dry or wet etching so that the screen hole 22 is formed at the position where the P-type well layer 17 and the upper polycrystalline silicon 18 intersect, and the charge generator is formed. Complete.

In the charge generator thus constructed, when a reverse bias is applied to the pixel selected by the P-type well layer 17 and the upper polycrystalline silicon 18, electrons are emitted from the screen hole 22. . When the charge generator having such a structure is used as a charge generator of a printer, the dielectric drum is located above. Further, by arranging a fluorescent material thin film formed on the dielectric material drum by irradiating charged particles such as electrons to emit blue to red visible light, a display device such as a flat panel display can be provided. can get.

In this manufacturing method, the drive line formed of the P well layer is separated from the adjacent line by LO.
Although the COS oxide film is used, the present invention is not limited to this, and a trench type separation in which a groove is formed in a silicon substrate can also be used. Further, as shown in FIG. 10, by removing the polycrystalline silicon 18 on the emitting portion while leaving the periphery in a guard ring shape, the polycrystalline silicon is eliminated, so that the emission of electrons becomes easier and the emission efficiency is improved. Can be raised.

As described above, in the charge generator manufactured by this manufacturing method, the charge generating portion is formed by the PN diode and the N ⁺ layer is very thin, so that a reverse bias of several tens V is applied. Avalanche breakdown can be easily caused and electrons (charges) can be emitted simply by simply opening. This makes it possible to easily form a charge generator in a semiconductor substrate by using a fine processing technique. Also,
Since there is no first insulating film exposed to corona discharge, there is no film loss or cracks, and durability is greatly improved. Moreover, since the driving voltage may be several tens of volts, a charge generator can be obtained which can remarkably simplify the structure of the generator.

FIG. 11A is a schematic perspective view showing the overall configuration of the charge generator of the first embodiment shown in FIG. 1, and FIG. 11B is a circuit configuration diagram thereof. In FIG. 11A, the screen electrodes and screen holes are not shown. In FIGS. 11A and 11B, reference numeral 31 is a charge generation control element array section in which the charge generation control elements 30 are two-dimensionally arranged. Reference numeral 32 is a scanner in the H direction composed of MOSFETs or bipolar transistors. The H scanner 32 applies a signal for selecting / deselecting to the gate of each switching transistor 34 through a large number of switch selection lines 33. It has become. Reference numeral 35 is a voltage application terminal connected to one end (source) of the switching transistor 34 for electron emission. The other end (drain) of the switching transistor 34 is connected to a drain line 36, and the drain line 36 is formed of a P well layer which constitutes a drive line. Reference numeral 37 is a V-direction scanner, which is N ⁺ via the polycrystalline silicon (selection line) 38 of the charge generation control elements 30 arranged in the row direction.
Connected to layers.

Next, the operation of the charge generator configured as described above will be described. By the V scanner 37, the polycrystalline silicon (selection line) 38 of the i-th charge generation control element 30
When the selection pulse is applied to, the pixels of the charge generation control element 30 arranged in the i-th position are turned on. In this state, when the H scanner 32 applies a selection pulse to the gate of the switching transistor 34 via the j-th switch selection line 33, the voltage application terminal 35 and the j-th drain line 36 are electrically coupled to each other, This drain line
36 has a negative potential and is in a reverse bias state with respect to the N ⁺ layer connected to the pixel in the ON state. As a result, (i,
A breakdown occurs in the charge generation portion of the charge generation control element at address j), and electrons are emitted from the electron emission holes. Thereafter, the H scanner 32 sequentially scans the jth, j + 1 ... th switching transistor 34 to be turned on, and electrons are sequentially emitted from the charge generation control element 30 in the i-th row. The electron emission from the generation control element 30 ends. When the electron emission from the charge generation control element 30 in the i-th row is completed, the operation of the charge generation control element 30 in the i + 1-th row is similarly started.

Next, the second embodiment will be described with reference to FIGS.
This will be described based on the manufacturing process diagram shown in FIG. First, as shown in FIG. 12A, by the same method as in the first embodiment,
Drive lines 44 and L composed of P well layers on the semiconductor substrate 41
An OCOS oxide film 42 and a pad silicon oxide 43 are formed.
Next, as shown in FIG. 12B, P is formed by an ion implantation method.
Impurity implantation of H ₃ (phosphine) 45 at a low accelerating voltage of 20 to 30 KeV and a dose of 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ^-2 ,
An N ⁺ layer 46 is formed on the extreme surface layer of the semiconductor substrate 41. Subsequently, heat treatment is performed by a lamp annealing method to form a diffusion layer in a short time. Then, the pad oxide film 43 formed before the ion implantation is removed by cleaning with hydrofluoric acid, and the N ⁺ layer 46 of the drive line portion is exposed on the surface. Next, as shown in FIG. 12C, a metal film, for example, an Al film 47 of about 0.1 micron is formed on the entire surface of the substrate by a sputtering method or a vapor deposition method. Subsequently, the P well layer drive line 44 is crossed diagonally,
⁺ Contacts a part of the layer 46 and contacts Al on the charge generation part
The film 47 is patterned by resist so as to be removed, and a charge generating portion is formed by dry etching.

In this embodiment, the Al film 47 forms a line diagonally intersecting the P-well layer drive line 44. However, the intersecting line is not limited to Al, but may be polycrystalline silicon, copper, molybdenum. Materials such as tungsten, titanium, etc. can also be used.

Next, the third embodiment is shown in FIGS. 13 (A) and 13 (B).
This will be described based on the manufacturing process diagram shown in FIG. First, as shown in FIG. 13A, by the same method as in the first embodiment,
The drive line 53 and the L formed of the P well layer on the semiconductor substrate 51.
An OCOS oxide film 52 is formed. Next, as shown in FIG. 13B, a very thin metal film 54 of several tens to several hundreds of liters, for example, a platinum film is formed on the entire surface of the substrate by a sputtering method. Subsequently, the metal film 54 is patterned so as to cross the P well layer drive line 53 obliquely, and a charge generation portion is formed by dry etching.

In this embodiment, a very thin metal film made of platinum is shown, but not limited to platinum, any material having a large work function difference with a semiconductor can be used. Materials such as aluminum, silver, copper, molybdenum, tungsten, and titanium can be used, and also silicide-based materials can be used. The structure of the charge generation portion shown in FIG. 13B is a Schottky diode, and by applying a reverse bias, breakdown is caused by a high electric field similarly to a PN diode, and hot electrons are very thin. The metal film is ejected by tunneling emission to generate charges (electrons).

Next, a fourth embodiment will be described with reference to the manufacturing process drawings shown in FIGS. First, as shown in FIG. 14, in order to form a buried N layer (BL), a P-type semiconductor substrate is formed.
An oxide film 62 of about 1.0 μm is formed on the entire surface of 61, and then the oxide film 62 in the BL layer portion is removed by wet or dry etching with a resist pattern 63. Next, as shown in FIG. 15, after removing the resist pattern, Sb ₂ O ₃ (antimony oxide) is diffused at a temperature of about 1200 ° C. for about 2 to 3 hours to form a BL layer 64. Next, as shown in FIG. 16, after the oxide film 62 is entirely removed, an N-type emitter layer 65 is formed by an epitaxial growth method. Epitaxial conditions include SiH ₄ (silane) at a temperature of about 1000 ° C.
An epitaxial layer of about 10 microns is formed by the reaction of PH ₃ (phosphine).

Next, as shown in FIG. 17, after forming the oxide film 66 for forming isolation, the oxide film 66 is selectively removed by wet or dry etching with a resist pattern. After that, add BN (boron nitride) 1000 °
The diffusion is performed at a temperature of about C to form a P-type isolation 67. Next, as shown in FIG. 18, the oxide film 68 formed again after the step shown in FIG. 17 is selectively removed by wet or dry etching with a resist pattern to form a base region. Then, B (boron) 69 is set to an acceleration voltage of 40 to 10
Ion implantation is performed at 0 KeV and a dose amount of 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ^-2 , and the base layer 70 is diffused at a temperature of about 1000 ° C.
To form Next, as shown in Fig. 19, deposit POCl ₃ (phosphorus oxychloride) at 1000 ° C for about 15 minutes, and
Very thin N by diffusing for about 30 minutes at a temperature of about 00 ° C
^{A +} type collector layer 71 is formed.

Next, as shown in FIG. 20, a metal film 72 of about 1.0 micron, such as an Al film, is formed on the entire surface of the substrate by a sputtering method or a vapor deposition method. Subsequently, it intersects diagonally with the bipolar structure serving as a drive line, contacts a part of the N ⁺ type collector layer 71, and performs resist patterning and dry etching so as to remove the metal 72 on the charge generation portion. Form a generator. Next, as shown in FIG. 21, a film having excellent heat resistance such as polyimide 73 is formed on the entire surface for several tens of microns, and then a Ti film to be the screen electrode 74 is formed for about 1.0 to 2.0 microns. Subsequently, the screen electrode 74 and the polyimide 73 are formed by dry or wet etching so that the screen hole 75 is formed at the position where the bipolar structure and the upper collector layer 71 intersect, and the charge generator is completed. Although the very thin collector layer 71 is formed by doping POCl ₃ in this embodiment, the present invention is not limited to this, and diffusion of N ⁺ from polycrystalline silicon or ion implantation by a low acceleration voltage is not necessary. It can also be formed by a method.

In the charge generator thus constructed, when a forward voltage is applied between the emitter layer 65 and the base layer 70, electrons are injected from the emitter layer 65 into the region of the base layer 70, and the electrons are injected. Most of it reaches the base-collector junction and is absorbed by the collector layer 71 due to the electric field due to the reverse voltage to generate a collector current. However, when a reverse bias is applied between the collector layer 71 and the base layer 70, the collector layer 71 is extremely damaged. Because it is thin
The hot electrons generated by the avalanche breakdown are amplified and emitted from the surface to the outside, and charges are generated, and electrons are emitted from the screen hole 75. When the charge generator having such a structure is used as a charge generator of a printer, the dielectric drum is located above.

In the charge generator having the structure in which the silicon surface containing impurities is exposed to the atmosphere in the first to fourth embodiments, several tens of liters of SiO ₂ and SiO ₂ are formed on the surface.
By adopting the structure in which the N, Si ₃ ON ₄ film is additionally formed, a surface protecting effect and a current stabilizing effect can be obtained.

In each of the above-mentioned embodiments, the embodiments of the charge generator according to the present invention have been described with the application to the electrostatic image forming device in mind, but of course the application of the charge generator according to the present invention is In addition to the electrostatic image forming apparatus, various applications are possible. Examples of other applications include display devices such as flat panel displays. In each of the above embodiments, in consideration of the application to the electrostatic image forming apparatus,
Although it has been described that the dielectric drum is arranged opposite to the charge generator, when the charge generator according to the present invention is applied to a flat panel display, an electronic device such as an electron is placed at the position where the dielectric drum is arranged. By irradiating the charged particles, a fluorescent plate on which a fluorescent material thin film that emits visible light of blue to red is formed is arranged. When the fluorescent plate is arranged in this way, light emission is emitted in the direction opposite to the direction of the charge generator. The atmosphere between the fluorescent plate and the charge generator is a gas atmosphere of helium, neon, argon or the like having an atmospheric pressure lower than atmospheric pressure, or a vacuum state. In the flat panel display configured as described above, the fluorescent particles are irradiated with the charged particles that are sequentially emitted from the charge generator, and visible light is generated from the fluorescent plate in the direction opposite to the direction of the charge generator. A display is formed by using a charge generator in which charge generation control elements are arranged two-dimensionally. As described above, the charge generator according to the present invention can be applied to many devices other than the electrostatic image forming device.

[0037]

As described above on the basis of the embodiments, according to the first and second aspects of the present invention, the electron emitting portion is formed by the PN junction diode formed on the semiconductor substrate. Only by applying a bias of several tens of V, electrons can be emitted, the insulating film is not reduced by the conventional corona discharge, and it is possible to realize a highly reliable charge generator having excellent durability. Moreover, the configuration of the generator for generating the drive voltage is significantly simplified. Claim 3
According to the inventions described in (4) and (4), it is possible to easily generate charges with a driving voltage of several tens of V, and it is possible to easily manufacture the charge generator. Further, according to the fifth and sixth aspects of the invention, since the electron emitting portion is constituted by the semiconductor substrate and the ultrathin metal film formed on the semiconductor substrate, it is only necessary to apply a reverse bias of several tens of volts. Electrons can be emitted, and a highly reliable charge generator can be realized. Further claim 7
According to the described invention, since the electron emission portion is constituted by the PNP or NPN structure bipolar transistor formed on the semiconductor substrate, it is only necessary to apply a reverse bias of several tens of V by forming a very thin collector layer. Therefore, electrons can be emitted, and a highly reliable charge generator can be realized. According to the invention of claim 8, the charge generation control elements can be easily formed in an array. Further, according to the invention of claim 9 or 10, it is possible to realize an electrostatic image forming device or a display device which can be easily driven by a driving voltage of several tens of volts.

[Brief description of drawings]

FIG. 1 is a sectional view showing a single charge generation control element portion of a first embodiment of a charge generator according to the present invention.

FIG. 2 is a diagram showing a manufacturing process for explaining the manufacturing method of the first embodiment shown in FIG.

FIG. 3 is a view showing a manufacturing process following the manufacturing process shown in FIG. 2;

FIG. 4 is a view showing a manufacturing process following the manufacturing process shown in FIG. 3;

FIG. 5 is a view showing a manufacturing process subsequent to the manufacturing process shown in FIG. 4;

FIG. 6 is a view showing a manufacturing process subsequent to the manufacturing process shown in FIG. 5;

FIG. 7 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 6;

FIG. 8 is a view showing a manufacturing process subsequent to the manufacturing process shown in FIG. 7;

9 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 8. FIG.

FIG. 10 is a sectional view showing a part of a modification of the first embodiment with a part thereof omitted.

FIG. 11 is a schematic perspective view and a circuit configuration diagram showing an overall configuration of the first embodiment.

FIG. 12 is a diagram showing a manufacturing process for explaining the second embodiment.

FIG. 13 is a diagram showing a manufacturing process for explaining the third embodiment.

FIG. 14 is a diagram showing a manufacturing process for explaining the fourth embodiment.

15 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 14.

16 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 15.

FIG. 17 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 16.

18 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 17.

FIG. 19 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 18.

20 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 19.

FIG. 21 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 20.

FIG. 22 is a diagram showing a configuration example of a conventional charge generator.

[Explanation of symbols]

1 N-type semiconductor substrate 2 Silicon oxide 3 P well layer drive line 4 N ⁺ layer 5 Polycrystalline silicon 6 Polyimide layer 7 Screen electrode 8 Screen hole 11 N-type semiconductor substrate 12 Silicon nitride 13 Resist 14 LOCOS silicon oxide 15 Pad silicon oxide 16 Boron 17 P well layer (driving line) 18 Polycrystalline silicon 19 N ⁺ layer 20 Polyimide 21 Screen electrode 22 Screen hole 30 Charge generation control element 31 Array section 32 H direction scanner 33 Switch selection line 34 Switch transistor 35 Voltage application terminal 36 Drain Line 37 V direction scanner 38 Polycrystalline silicon selection line 41 N-type semiconductor substrate 42 LOCOS oxide film 43 Pad silicon oxide 44 Drive line (P well layer) 45 PH ₃ (phosphine) 46 N ⁺ layer 47 Al film 51 N-type semiconductor substrate 52 LOCOS oxide film 53 Drive line (P well layer) 54 Gold Metallic film 61 P-type semiconductor substrate 62 Oxide film 63 Resist pattern 64 BL layer 65 N-type emitter layer 66 Oxide film 67 P-type isolation 68 Oxide film 69 Boron 70 Base layer 71 N ⁺ type collector layer 72 Metal film 73 Polyimide 74 Screen Electrode 75 screen hole

Claims (10)

[Claims] 1. A charge generator, which is configured by arranging charge generation control elements having a function of emitting electrons or charges in a one-dimensional or two-dimensional array in the atmosphere or vacuum, wherein the charge generation control elements are semiconductors. The electron emission part of the charge generation control element is formed on a substrate and is constituted by a diode having a P-N junction, and a reverse bias is applied to the diode to emit electrons or charges. Characteristic charge generator. 2. An N of a diode having the P-N junction.
The charge generator according to claim 1, wherein the layer is composed of a diffusion layer of about several tens of liters formed on the extreme surface of the semiconductor substrate. 3. The method of manufacturing a charge generator according to claim 1, wherein the N of the diode having the P—N junction is used.
A method of manufacturing a charge generator, wherein the layer is formed by diffusion from polycrystalline silicon. 4. The method of manufacturing a charge generator according to claim 1, wherein the N of the diode having the P—N junction is used.
A method of manufacturing a charge generator, wherein the layer is formed by an ion implantation method. 5. A charge generator comprising a one-dimensional or two-dimensional array of charge generation control elements having a function of releasing electrons or charges into the atmosphere or vacuum, wherein the charge generation control elements are semiconductors. A charge generator, which is formed on a substrate, and in which the electron emission portion of the charge generation control element is composed of the semiconductor substrate and an extremely thin metal film formed on the semiconductor substrate. 6. The charge generator according to claim 5, wherein the ultrathin metal film forming the electron emitting portion is made of platinum or gold. 7. A charge generator comprising a charge generation control element having a function of emitting electrons or charges in a one-dimensional or two-dimensional array in the atmosphere or in a vacuum, wherein the charge generation control element is a semiconductor. A charge generator formed on a substrate, wherein the electron emission portion of the charge generation control element is composed of a bipolar transistor having a PNP or NPN structure. 8. A voltage application line for driving an electron emission portion of the charge generation control element is provided, and the voltage application line intersects obliquely with an arrangement direction of the charge generation control element in a semiconductor substrate. The electric charge generator according to claim 1, wherein the electric charge generator is formed. 9. A static discharge device, comprising: the charge generator according to claim 1, 2, 5 or 7, and a dielectric drum arranged to face the charge generator. Electrographic device. 10. A display device comprising the charge generator according to claim 1, 2, or 5 and a fluorescent plate arranged to face the charge generator.