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JPH097967A - Fabrication method of semiconductor device - Google Patents

Fabrication method of semiconductor device

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Publication number
JPH097967A
JPH097967A JP14728595A JP14728595A JPH097967A JP H097967 A JPH097967 A JP H097967A JP 14728595 A JP14728595 A JP 14728595A JP 14728595 A JP14728595 A JP 14728595A JP H097967 A JPH097967 A JP H097967A
Authority
JP
Japan
Prior art keywords
oxide film
boron
locos
locos oxide
oxidation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14728595A
Other languages
Japanese (ja)
Inventor
Hidekuni Nishimura
英訓 西村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP14728595A priority Critical patent/JPH097967A/en
Publication of JPH097967A publication Critical patent/JPH097967A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE: To fabricate a semiconductor device including a channel stopper and a high resistance element under a LOCOS oxide film formed through ion implantation of boron. CONSTITUTION: LOCOS oxidization is effected with two-step oxidization of wet oxidization and dry oxidization after there is applied twice boron doping at low energy and high energy to achieve channel stopper formation of a boron diffusion layer and the boron doping at high energy. Thereafter, a LOCOS oxide film 39 is formed with two-step oxidization of wet oxidization and dry oxidization to form a high resistance element 1 under the LOCOS oxide film 39 by making use of a boron diffusion layer 43. Hereby, deterioration of withstand voltage of the channel stopper part in contact with a high concentration N<+> diffusion layer is reduced, and a boron concentration diffusion layer also securely processing a channel stopper effect can be accurately formed. Further, the high resistance element 1 can be formed under the LOCOS oxide film 39 with reduced variations of the resistance.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、さらに詳しくは、ボロンのイオン注入により、L
OCOS酸化膜下のチャネルストッパやLOCOS酸化
膜下の拡散層による高抵抗素子を形成する工程を含む半
導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.
The present invention relates to a method of manufacturing a semiconductor device including a step of forming a high resistance element by a channel stopper under an OCOS oxide film and a diffusion layer under a LOCOS oxide film.

【0002】[0002]

【従来の技術】LSI等の半導体装置の高集積化、高性
能化に伴い、LOCOS法とボロンのイオン注入による
効果的な素子分離法や、LOCOS法で形成される厚い
酸化膜のフィールド領域に、ボロンの拡散層による高抵
抗素子を形成する等の高集積化対応がなされてきた。
2. Description of the Related Art With higher integration and higher performance of semiconductor devices such as LSI, an effective element isolation method by ion implantation of LOCOS method and boron and a field region of a thick oxide film formed by the LOCOS method are formed. High integration has been achieved by forming a high resistance element using a boron diffusion layer.

【0003】LOCOS法とボロンのイオン注入で、L
OCOS酸化膜下にチャネルストッパを形成する従来の
素子分離法につき、図5を参照して説明する。まず、図
5(a)に示すように、半導体基板11の表面に酸化膜
31を熱酸化により形成し、その上にプラズマCVDよ
りSiN膜32を堆積し、フォトリソグラフィ法により
半導体集積回路のフィールド領域となる部分のSiN3
2をパターニングし、その後ボロンのイオン注入をし
て、ボロン注入領域33を形成する。次に図5(b)に
示す様に、不活性ガスの熱処理により注入イオンを活性
化した後、SiN膜32を酸化防止膜として酸化のマス
クに使用し、熱酸化によりLOCOS酸化膜34を半導
体基板11に形成する。この様にして、フィールド領域
のLOCOS酸化膜34下のボロン拡散層35によるチ
ャネルストッパが形成される。
By the LOCOS method and boron ion implantation, L
A conventional element isolation method for forming a channel stopper under the OCOS oxide film will be described with reference to FIG. First, as shown in FIG. 5A, an oxide film 31 is formed on the surface of a semiconductor substrate 11 by thermal oxidation, and a SiN film 32 is deposited thereon by plasma CVD, and a field of a semiconductor integrated circuit is formed by photolithography. Area SiN3
2 is patterned, and then boron ions are implanted to form a boron implantation region 33. Next, as shown in FIG. 5B, after the implanted ions are activated by heat treatment with an inert gas, the SiN film 32 is used as an oxidation mask for an oxidation mask, and the LOCOS oxide film 34 is formed into a semiconductor by thermal oxidation. It is formed on the substrate 11. In this way, a channel stopper is formed by the boron diffusion layer 35 below the LOCOS oxide film 34 in the field region.

【0004】また、半導体集積回路のフィールド領域の
LOCOS酸化膜下に、ボロンの拡散層を用いた高抵抗
素子を形成して、半導体集積回路の高集積化を図ること
が行われてきた。この製造方法を図6を参照して説明す
る。。まず図6(a)に示したように、P型半導体基板
11にN型不純物を拡散し、Nウェル12を形成したP
型半導体基板11上に、熱酸化膜31を形成し、更にこ
の上にプラズマCVD法によりSiN膜32を形成す
る。次に、フォトリソグラフィによりSiN膜32をパ
ターンニングしてフィールド領域となる部分のSiN膜
32を除去する。
Further, a high resistance element using a diffusion layer of boron has been formed under the LOCOS oxide film in the field region of the semiconductor integrated circuit to achieve high integration of the semiconductor integrated circuit. This manufacturing method will be described with reference to FIG. . First, as shown in FIG. 6A, an N-type impurity is diffused into the P-type semiconductor substrate 11 to form an N well 12.
A thermal oxide film 31 is formed on the mold semiconductor substrate 11, and a SiN film 32 is further formed thereon by a plasma CVD method. Next, the SiN film 32 is patterned by photolithography to remove the SiN film 32 in the portion to be the field region.

【0005】さらにその後、図6(b)に示すように、
フォトレジスト36を塗布し、LOCOS酸化下のボロ
ン拡散層に高抵抗素子を形成するためのボロンイオン注
入用マスクによる、フォトレジスト36のパターニング
する。次に、所望の高抵抗を形成すべく、ボロンのイオ
ン打ち込みをして、ボロン注入領域37を形成する。次
に、図6(c)に示すように、フォトレジスト36を剥
離後、イオン注入したボロンの活性化の熱処理を行い、
その後SiN膜32を酸化防止膜として酸化のマスクに
使用し、ウェット酸化法にて酸化し、LOCOS酸化膜
34を形成する。このようにして、LOCOS酸化膜3
4の下に、ボロン拡散層38による高抵抗素子1が形成
される。
After that, as shown in FIG. 6 (b),
A photoresist 36 is applied, and the photoresist 36 is patterned using a boron ion implantation mask for forming a high resistance element in the boron diffusion layer under LOCOS oxidation. Next, in order to form a desired high resistance, boron is ion-implanted to form a boron implantation region 37. Next, as shown in FIG. 6C, after removing the photoresist 36, a heat treatment for activating the ion-implanted boron is performed.
After that, the SiN film 32 is used as an antioxidation film as an oxidation mask and is oxidized by a wet oxidation method to form a LOCOS oxide film 34. In this way, the LOCOS oxide film 3
Underneath 4, the high resistance element 1 is formed by the boron diffusion layer 38.

【0006】しかし、上記の様なボロンのイオン注入に
よるLOCOS酸化膜下のチャネルストッパ形成におけ
る問題は、ボロンのイオン打ち込みドーズ量が多いと、
チャネルストッパの効果は上がるが、高濃度N+ 拡散層
と接する部分(図示せず)での耐圧が低下する。一方、
ボロンのイオン打ち込みドーズ量が少ないと、LOCO
S酸化時にボロンが酸化膜中に多く取り込まれ、更にま
た、ボロンの偏拆係数が小さいことにより、LOCOS
酸化膜下の界面でボロン濃度の低下が起き、チャネルス
トッパの効果が低下する。更に、MOSトランジスタの
半導体集積回路においては、LOCOS領域の周囲に生
じるバーズビーク下のボロン濃度の低下はゲート電極の
チャネル幅変動要因となり、MOS特性を劣化させる。
However, the problem in forming the channel stopper under the LOCOS oxide film by the above boron ion implantation is that the boron ion implantation dose is large.
Although the effect of the channel stopper is enhanced, the breakdown voltage at the portion (not shown) in contact with the high concentration N + diffusion layer is reduced. on the other hand,
If the dose of boron ion implantation is small, the LOCO
A large amount of boron is taken into the oxide film during S oxidation, and further, the deviation coefficient of boron is small, which results in LOCOS.
The boron concentration decreases at the interface under the oxide film, and the effect of the channel stopper decreases. Further, in the semiconductor integrated circuit of the MOS transistor, the decrease in the boron concentration under the bird's beak that occurs around the LOCOS region causes the channel width variation of the gate electrode and deteriorates the MOS characteristics.

【0007】また、上記の様なボロンのイオン注入によ
るフィールド領域のLOCOS酸化膜下の高抵抗素子の
形成においては、拡散層の実質的なボロン濃度変動によ
る抵抗値のバラツキが大きな問題である。この抵抗値の
バラツキは、LOCOS工程およびLOCOS工程以前
熱処理工程においての、シリコンのドーパントとなる不
純物の拡散により実質的なボロン濃度の変動によるか、
又はボロンの偏拆係数の関係で、LOCOS工程時にボ
ロンの酸化膜への取り込まれ度合いの変動等によってお
こされる。この様なことで、高抵抗素子の抵抗値のバラ
ツキを起こし、半導体装置の製造歩留を低下させてい
る。
Further, in the formation of the high resistance element under the LOCOS oxide film in the field region by the boron ion implantation as described above, the variation of the resistance value due to the substantial variation of the boron concentration of the diffusion layer is a serious problem. Is this variation in the resistance value due to a substantial variation in the boron concentration due to the diffusion of impurities serving as a dopant of silicon in the LOCOS step and the heat treatment step before the LOCOS step?
Alternatively, due to the deviation coefficient of boron, it is caused by a variation in the degree of incorporation of boron into the oxide film during the LOCOS process. As a result, the resistance value of the high resistance element varies, and the manufacturing yield of the semiconductor device is reduced.

【0008】[0008]

【発明が解決しようとする課題】本発明は、上記のごと
くイオン注入後にLOCOS酸化をして、LOCOS酸
化膜下のボロン拡散層によりチャネルストッパを形成す
る場合に、高濃度N+ 拡散層と隣接する箇所での耐圧低
下を押さえ、しかもチャネルストッパの効果を確実にす
るための精度よいボロン濃度制御を可能とする半導体装
置の製造方法を提供することを目的とする。また本発明
は、上記のごとくイオン注入後にLOCOS酸化をし
て、LOCOS酸化膜下にボロン拡散層による高抵抗素
子を形成する場合に、LOCOS酸化膜下のボロン拡散
層のボロン濃度バラツキを押さえたことで高抵抗素子の
抵抗値バラツキ押さえることを可能にする半導体装置の
製造方法を提供することを目的とする。
SUMMARY OF THE INVENTION According to the present invention, when the LOCOS oxidation is performed after the ion implantation as described above and the channel stopper is formed by the boron diffusion layer under the LOCOS oxide film, it is adjacent to the high concentration N + diffusion layer. An object of the present invention is to provide a method for manufacturing a semiconductor device, which suppresses the breakdown voltage reduction at a desired position and enables accurate boron concentration control for ensuring the effect of a channel stopper. Further, according to the present invention, when the LOCOS oxidation is performed after the ion implantation as described above to form a high resistance element by the boron diffusion layer under the LOCOS oxide film, variation in boron concentration in the boron diffusion layer under the LOCOS oxide film is suppressed. Therefore, it is an object of the present invention to provide a method for manufacturing a semiconductor device that can suppress variations in resistance value of a high resistance element.

【0009】[0009]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、上記の課題を解決するために提案するもので
あり、半導体基板上に酸化防止膜を形成し、前記半導体
基板に形成する半導体集積回路のフィールド領域になる
前記酸化防止膜をフォトリソグラフィ法により開口し、
前記酸化防止膜をマスクに熱酸化してLOCOS酸化膜
を形成し、LOCOS酸化膜下にチャネルストッパを形
成する半導体装置の製造方法であって、前記チャネルス
トッパとなるボロンをイオン注入する際に、前記半導体
基板表面に低エネルギーで打ち込むイオン注入と、LO
COS酸化膜厚の略半分の値に相当する半導体基板表面
からの深さに高エネルギーで打ち込むイオン注入を施し
た後、前記酸化防止膜をマスクとして熱酸化し、前記L
OCOS酸化膜を形成することを特徴とする。また、本
発明の半導体装置の製造方法は、上記の半導体装置の製
造方法であって、LOCOS酸化工程を水蒸気と酸素ガ
スによるウェット酸化工程と酸素ガスのみによるドライ
酸化工程をこの順序で施して、前記LOCOS酸化膜を
形成することを特徴とするものである。
A method for manufacturing a semiconductor device according to the present invention is proposed to solve the above-mentioned problems, and an antioxidation film is formed on a semiconductor substrate and formed on the semiconductor substrate. The oxidation prevention film, which becomes the field region of the semiconductor integrated circuit, is opened by photolithography,
A method of manufacturing a semiconductor device, wherein a LOCOS oxide film is formed by thermal oxidation using the anti-oxidation film as a mask, and a channel stopper is formed under the LOCOS oxide film. Ion implantation for implanting into the surface of the semiconductor substrate with low energy, and LO
Ion implantation is performed with high energy to a depth from the surface of the semiconductor substrate corresponding to a value approximately half the thickness of the COS oxide film, and then thermal oxidation is performed using the antioxidant film as a mask.
It is characterized in that an OCOS oxide film is formed. A method for manufacturing a semiconductor device of the present invention is the above-described method for manufacturing a semiconductor device, in which a LOCOS oxidation step is performed in this order by a wet oxidation step using water vapor and oxygen gas, and a dry oxidation step using only oxygen gas, The LOCOS oxide film is formed.

【0010】更にまた、本発明の半導体装置の製造方法
は、半導体基板に形成される半導体集積回路でフィール
ド領域のLOCOS酸化膜下に拡散層による高抵抗素子
を形成する半導体装置の製造方法であって、形成される
前記LOCOS酸化膜厚の略半分の値に相当する半導体
基板表面からの深さに高エネルギーで打ち込むボロンの
イオン注入をした後、前記酸化防止膜をマスクとして熱
酸化によりLOCOS酸化膜を形成することで、LOC
OS酸化膜下に拡散層による高抵抗を形成することを特
徴とするものである。また、本発明の半導体装置の製造
方法は、上記のLOCOS酸化膜下に拡散層による高抵
抗素子を形成する半導体装置の製造方法であって、LO
COS酸化工程を水蒸気と酸素ガスによるウェット酸化
工程と酸素ガスのみによるドライ酸化工程をこの順序で
施して、前記LOCOS酸化膜を形成することを特徴と
するものである。
Furthermore, the method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device in which a high resistance element is formed by a diffusion layer under a LOCOS oxide film in a field region in a semiconductor integrated circuit formed on a semiconductor substrate. Then, after ion implantation of boron with high energy is implanted into the depth from the surface of the semiconductor substrate corresponding to approximately half the thickness of the LOCOS oxide film to be formed, LOCOS oxidation is performed by thermal oxidation using the antioxidant film as a mask. By forming a film, LOC
It is characterized in that a high resistance is formed by the diffusion layer under the OS oxide film. A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which a high resistance element is formed of a diffusion layer below the LOCOS oxide film.
The LOCOS oxide film is formed by performing a COS oxidation process in the order of a wet oxidation process using water vapor and oxygen gas and a dry oxidation process using only oxygen gas.

【0011】[0011]

【作用】本発明の半導体装置の製造方法によれば、LO
COS酸化時の酸化膜にボロンが食われる状態を極力押
さえることで、LOCOS酸化膜下のボロン拡散層によ
るチャネルストッパや高抵抗素子を安定して精度よく形
成することができる。一般に、ボロンを含むシリコン半
導体基板を酸化すると、ボロンの偏拆係数の関係で酸化
膜中により多くのボロンが偏拆する。そこで、ボロンの
酸化膜に取り込まれる量を少なくすべく、LOCOS酸
化膜がシリコン基板表面から内部に形成される厚み(L
OCOS酸化膜厚の約4割の厚み)以上の深さに高エネ
ルギーでボロンのイオン注入を施した後、前記酸化防止
膜をマスクとして熱酸化し、前記LOCOS酸化膜を形
成ことで、ボロンのLOCOS酸化膜に食われる量を極
力押さえられる。
According to the method of manufacturing a semiconductor device of the present invention, the LO
By suppressing the state where boron is eaten into the oxide film during COS oxidation as much as possible, it is possible to stably and accurately form the channel stopper and the high resistance element by the boron diffusion layer under the LOCOS oxide film. In general, when a silicon semiconductor substrate containing boron is oxidized, more boron is deviated in the oxide film due to the deviation coefficient of boron. Therefore, in order to reduce the amount of boron taken into the oxide film, the thickness (L
Boron is ion-implanted with high energy to a depth of at least 40% of the OCOS oxide film thickness) and then thermally oxidized using the antioxidant film as a mask to form the LOCOS oxide film. The amount eaten by the LOCOS oxide film can be suppressed as much as possible.

【0012】更に、ボロンの偏拆係数は酸化条件の違い
により、次式のようになることが知られている。ウエッ
ト酸化時の偏拆係数m(Si中の不純物濃度とSiO2
中の不純物濃度の比)は、 m=104.0EXP(−0.66eV/kT) ドライ酸化時の偏拆係数mは、 m=13.4EXP(−0.33eV/kT) 今、1000℃でLOCOS酸化をする時には、ウエッ
ト酸化時およびドライ酸化時の偏拆係数mは、それぞれ
m=0.255、m=0.663となる。したがって、
ドライ酸化の方がボロンの酸化膜への取り込まれ度合い
が少なくてすむ。通常、厚いLOCOS酸化膜の形成
は、作業性の関係で酸化速度の大きいウエット酸化にて
行うが、上記のことを考慮して、LOCOS酸化膜厚の
略半分の値に相当する半導体基板表面からの深さに高エ
ネルギーで打ち込むボロンイオン注入をした後、LOC
OS酸化工程を水蒸気と酸素ガスによるウェット酸化工
程と酸素ガスのみによるドライ酸化工程をこの順序で施
して、前記LOCOS酸化膜を形成すれば、LOCOS
酸化膜下のボロン拡散層による高抵抗素子が、バラツキ
の少ない抵抗値で安定にでき、しかもの作業性よく形成
することができる。
Further, it is known that the deviation coefficient of boron is given by the following equation, depending on the difference in oxidation conditions. Deviation coefficient m during wet oxidation (impurity concentration in Si and SiO 2
The ratio of the impurity concentration in) is m = 104.0 EXP (-0.66 eV / kT) The deviation coefficient m during dry oxidation is m = 13.4 EXP (-0.33 eV / kT) When performing LOCOS oxidation, the deviation coefficients m during wet oxidation and during dry oxidation are m = 0.255 and m = 0.663, respectively. Therefore,
Dry oxidation requires less incorporation of boron into the oxide film. Normally, a thick LOCOS oxide film is formed by wet oxidation, which has a high oxidation rate due to workability. However, in consideration of the above, from the surface of the semiconductor substrate corresponding to about half the value of the LOCOS oxide film thickness. After implanting boron ions with high energy to the depth of
If the OS oxidation process is performed by a wet oxidation process using water vapor and oxygen gas and a dry oxidation process using only oxygen gas in this order to form the LOCOS oxide film, the LOCOS film is formed.
A high resistance element formed of a boron diffusion layer below the oxide film can be stably formed with a resistance value having little variation, and can be formed with good workability.

【0013】[0013]

【実施例】以下、本発明の具体的実施例につき、添付図
面を参照して説明する。なお従来技術の説明で参照した
図5、6中の構成部分と同様の構成部分には、同一の参
照符号を付すものとする。
Embodiments of the present invention will be described below with reference to the accompanying drawings. It should be noted that the same components as those in FIGS. 5 and 6 referred to in the description of the prior art are designated by the same reference numerals.

【0014】実施例1 本実施例は、半導体集積回路の製造方法における、LO
COS法とボロンのイオン注入による素子分離法に本発
明を適用した例であり、これを図1(a)〜(c)を参
照にして説明する。まず、図1(a)に示すように、P
型半導体基板11の表面に、厚さ約30nmの酸化膜3
1を熱酸化により形成し、その上にプラズマCVD法よ
り厚さ約200nmのSiN膜32を堆積し、更にその
上に、フォトレジスト37を1.5μmの厚さで塗布す
る。次に、半導体集積回路のフィールド領域となる部分
のSiN膜32を除去すべく、まずフォトレジスト37
をリソグラフィ法によりパターニングし、その後このフ
ォトレジスト37をマスクとしSiN膜32をRIE法
によりエッチングする。
Example 1 This example is an LO method in a method for manufacturing a semiconductor integrated circuit.
This is an example in which the present invention is applied to the element isolation method by the COS method and boron ion implantation, which will be described with reference to FIGS. First, as shown in FIG.
The oxide film 3 having a thickness of about 30 nm is formed on the surface of the semiconductor substrate 11.
1 is formed by thermal oxidation, a SiN film 32 having a thickness of about 200 nm is deposited thereon by a plasma CVD method, and a photoresist 37 is applied thereon with a thickness of 1.5 μm. Next, in order to remove the SiN film 32 in the field region of the semiconductor integrated circuit, first the photoresist 37 is removed.
Is patterned by the lithography method, and then the SiN film 32 is etched by the RIE method using the photoresist 37 as a mask.

【0015】次に、前記フォトレジスト37とSiN膜
32をマスクとし、P型半導体基板11上の酸化膜31
を通して、P型半導体基板11に、一例としてドーズ量
約2E13/cm2 、エネルギー約20KeVでボロン
をイオン注入して、P型半導体基板11表面のより浅い
部分(約60nm)に低エネルギーのボロン注入領域3
3を形成する。その後、図1(b)に示す様に、高エネ
ルギーによるボロンのイオン注入を行い、高エネルギー
によるボロン注入領域38を形成する。この注入時のボ
ロンイオンのエネルギーは、この後に形成するLOCO
S酸化膜厚より決め、例えばLOCOS酸化膜厚を約6
00nmとする時は、P型半導体基板11の表面よりL
OCOS酸化膜厚の約半分である深さ300nm程度に
ボロンイオンが打ち込まれるようなエネルギーとし、こ
のエネルギー値は、酸化膜31を考慮すると約100K
eVとなる。なお、この時のボロンイオンのドーズ量は
チャネルストッパ効果とN+ 高濃度不純物拡散領域(図
示せず)と接する箇所での耐圧低下を生じないことを考
慮し、約2E13/cm2 程度とする。
Next, using the photoresist 37 and the SiN film 32 as a mask, the oxide film 31 on the P-type semiconductor substrate 11 is used.
Through boron ion implantation into the P-type semiconductor substrate 11 at a dose amount of about 2E13 / cm 2 and energy of about 20 KeV, and low-energy boron implantation to a shallower portion (about 60 nm) of the surface of the P-type semiconductor substrate 11. Area 3
3 is formed. After that, as shown in FIG. 1B, high-energy boron ion implantation is performed to form a high-energy boron implantation region 38. The energy of boron ions at the time of implantation is LOCO formed later.
Determined from the S oxide film thickness, for example, the LOCOS oxide film thickness is about 6
When the thickness is set to 00 nm, L is less than the surface of the P-type semiconductor substrate 11.
The energy is set such that boron ions are implanted at a depth of about 300 nm, which is about half the thickness of the OCOS oxide film. This energy value is about 100 K when the oxide film 31 is taken into consideration.
eV. At this time, the dose amount of boron ions is set to about 2E13 / cm 2 in consideration of the channel stopper effect and the fact that the breakdown voltage does not decrease at the portion in contact with the N + high-concentration impurity diffusion region (not shown). .

【0016】次に、フォトレジスト37を除去し、前記
低エネルギーのボロン注入領域33や高エネルギーによ
るボロン注入領域38のボロンの活性化をすべく、約1
000℃で10分間の熱処理をする。その後SiN膜3
2を酸化防止のマスクとし、一例として水素ガスと酸素
ガスを1:1.1の比で混合したガスを、酸化炉中で燃
焼させて作る水蒸気と酸素の雰囲気中で酸化を行うウェ
ット酸化法により、約950℃で160分間酸化し、さ
らにその後、酸素ガスのみによるドライ酸化を約950
℃で30分間おこない、図1(c)に示すように、約6
00nmのLOCOS酸化膜39を形成する。この様に
してLOCOS酸化を行うと、低エネルギーと高エネル
ギーによって注入されたボロン注入領域33、38のボ
ロンは一部酸化膜に取り込まれながら、深さ方向と平面
方向に拡散してゆき、LOCOS酸化膜39下にボロン
拡散層40が形成される。
Next, the photoresist 37 is removed, and about 1 is used to activate the boron in the low energy boron implantation region 33 and the high energy boron implantation region 38.
Heat treatment is performed at 000 ° C. for 10 minutes. Then SiN film 3
Wet oxidation method in which 2 is used as an anti-oxidation mask and, as an example, a gas in which hydrogen gas and oxygen gas are mixed at a ratio of 1: 1.1 is burned in an oxidizing furnace to oxidize in an atmosphere of steam and oxygen. Oxidize for about 160 minutes at about 950 ° C, and then dry oxidize only with oxygen gas for about 950
1 hour at 30 ° C for about 6 minutes as shown in Fig. 1 (c).
A LOCOS oxide film 39 of 00 nm is formed. When the LOCOS oxidation is performed in this way, the boron in the boron-implanted regions 33 and 38, which has been implanted by the low energy and the high energy, is partially taken into the oxide film and diffuses in the depth direction and the plane direction. A boron diffusion layer 40 is formed under the oxide film 39.

【0017】この時、P型半導体基板11の表面に打ち
込まれた前者の低エネルギーのボロン注入領域33のボ
ロンは、LOCOS酸化膜39のバーズビーク部41の
下にも効果的に拡散してチャネルストッパの機能を確実
に持たせることができる。また、後者の高エネルギーに
よるボロン注入領域38のボロンは、LOCOS酸化時
の酸化膜への取り込まれが少なく、またウェット酸化と
ドライ酸化の2段階酸化によりボロンの偏拆係数の関係
で決まるLOCOSの界面での濃度低下が軽減され、チ
ャネルストッパ効果と耐圧の面で決める所望のボロン濃
度が精度よく得られる。この上述したボロンイオンの二
度打ち込みと2段階のLOCOS酸化をした時、LOC
OS酸化膜39とP型半導体基板11のボロン濃度分布
を従来法と対比して示したのが図2(a)、(b)であ
る。ここで、図2(a)は本実施例1の場合で、図2
(b)は従来例の場合である。この図2より明らかなよ
うに、本実施例1の場合はLOCOS酸化膜へのボロン
取り込まれ量が少なく、またLOCOSの界面における
ボロン濃度低下が少なく所望のボロン濃度が得やすくな
っている。
At this time, the former boron in the low-energy boron-implanted region 33, which has been implanted into the surface of the P-type semiconductor substrate 11, is also effectively diffused under the bird's beak portion 41 of the LOCOS oxide film 39 to be a channel stopper. The function of can be surely provided. In the latter case, boron in the boron-implanted region 38 due to high energy is hardly taken into the oxide film at the time of LOCOS oxidation, and the LOCOS of the LOCOS determined by the relationship between the deviation coefficient of boron is determined by the two-step oxidation of wet oxidation and dry oxidation. The decrease in the concentration at the interface is reduced, and the desired boron concentration determined in terms of the channel stopper effect and the breakdown voltage can be accurately obtained. When the above-mentioned double implantation of boron ions and two-stage LOCOS oxidation are performed, the LOC
FIGS. 2A and 2B show the boron concentration distributions of the OS oxide film 39 and the P-type semiconductor substrate 11 in comparison with the conventional method. Here, FIG. 2A shows the case of the first embodiment, and FIG.
(B) is the case of the conventional example. As is clear from FIG. 2, in the case of the first embodiment, the amount of boron taken into the LOCOS oxide film is small, and the boron concentration at the interface of LOCOS is not lowered so that the desired boron concentration can be easily obtained.

【0018】実施例2 本実施例は、半導体集積回路の製造方法における、フィ
ールド領域のLOCOS酸化膜下に高抵抗素子を形成す
る場合に本発明を適用した例であり、図3(a)〜
(c)および図4を参照して説明する。本実施例は、ま
ず図3(a)に示したように、通常方法にてP型半導体
基板11にN型不純物を拡散し、Nウェル12を形成し
たP型半導体基板11上に、膜厚30nmの熱酸化膜3
1を形成し、更にこの上にプラズマCVD法によりSi
N膜32を膜厚約200nm形成する。次に、フォトリ
ソグラフィによりSiN膜13をパターニングしてフィ
ールド領域となる部分のSiN膜32を除去する。
Embodiment 2 This embodiment is an example in which the present invention is applied to the case where a high resistance element is formed under the LOCOS oxide film in the field region in the method of manufacturing a semiconductor integrated circuit, and FIG.
This will be described with reference to (c) and FIG. In this embodiment, first, as shown in FIG. 3A, the N-type impurity is diffused in the P-type semiconductor substrate 11 by a normal method, and the film thickness is formed on the P-type semiconductor substrate 11 in which the N well 12 is formed. 30 nm thermal oxide film 3
1 is formed, and Si is further formed thereon by plasma CVD.
The N film 32 is formed to a film thickness of about 200 nm. Next, the SiN film 13 is patterned by photolithography to remove the SiN film 32 in the portion to be the field region.

【0019】さらにその後、図3(b)に示すように、
フォトレジスト36を膜厚約1.5μmほど塗布し、L
OCOS酸化膜下のボロン拡散層に高抵抗素子を形成す
るためのボロンイオン注入用のフォトマスクにて、フォ
トレジスト36をパターニングする。次に、所望の高抵
抗を形成すべく、フォトレジスト36のパター形状とL
OCOS酸化およびその後の熱処理とを考慮して決める
ボロンのドーズ量、例えば6E13/cm2 で、エネル
ギーとしては、この後に形成するLOCOS酸化膜の膜
厚、例えば600nmの約半分程度のボロンイオン注入
の投影飛程を与えるエネルギー約100KeVで、ボロ
ンをフォトレジスト36をマスクとしてP型半導体基板
11に打ち込み、ボロン注入領域42を形成する。
After that, as shown in FIG. 3 (b),
Photoresist 36 is applied to a film thickness of about 1.5 μm, and L
The photoresist 36 is patterned using a photomask for boron ion implantation for forming a high resistance element in the boron diffusion layer under the OCOS oxide film. Next, in order to form a desired high resistance, the pattern shape of the photoresist 36 and L
The boron dose determined in consideration of OCOS oxidation and the subsequent heat treatment, for example, 6E13 / cm 2 , and the energy is about half the film thickness of the LOCOS oxide film to be formed thereafter, for example, about 600 nm. Boron is implanted into the P-type semiconductor substrate 11 using the photoresist 36 as a mask at an energy of about 100 KeV that gives a projection range to form a boron implantation region 42.

【0020】次に、フォトレジスト36を剥離後、イオ
ン注入したボロンの活性化のため、約1000℃で10
分間の熱処理を行う。その後引き続いて、SiN膜32
を酸化防止のマスクとし、一例として水素ガスと酸素ガ
スを1:1.1の比で混合したガスを、酸化炉中で燃焼
させて作る水蒸気と酸素の雰囲気中で酸化を行うウェッ
ト酸化法により、約950℃で160分間酸化し、さら
にその後、酸素ガスのみによるドライ酸化を約950℃
で30分間おこない、図3(c)に示すように、約60
0nmのLOCOS酸化膜39を形成する。上述したよ
うなボロンのイオン注入法とLOCOS酸化法とによ
り、LOCOS酸化膜39下のボロン拡散層43による
高抵抗素子1を形成することで、LOCOS酸化膜への
ボロンの取り込まれ量を軽減し、またボロンの偏拆係数
に起因するLOCOSの界面でのボロン濃度の落ち込み
も軽減でき、バラツキの少ない、所望の抵抗値もつ高抵
抗素子1が安定して形成でき、しかも、LOCOS酸化
をウェット酸化とドライ酸化の二段階酸化とすることで
の作業性への影響はほとんど無い。
Next, after the photoresist 36 is stripped off, at a temperature of about 1000.degree.
Heat treatment for 1 minute. Then, subsequently, the SiN film 32 is formed.
Is used as an anti-oxidation mask, and as an example, a gas in which hydrogen gas and oxygen gas are mixed at a ratio of 1: 1.1 is burned in an oxidizing furnace to perform oxidation in an atmosphere of steam and oxygen. , Oxidize at about 950 ° C for 160 minutes, and then dry oxidize only with oxygen gas at about 950 ° C
For 30 minutes, and as shown in Fig. 3 (c), about 60
A LOCOS oxide film 39 of 0 nm is formed. By forming the high resistance element 1 by the boron diffusion layer 43 under the LOCOS oxide film 39 by the above-described boron ion implantation method and LOCOS oxidation method, the amount of boron taken into the LOCOS oxide film is reduced. Further, it is possible to reduce the drop in boron concentration at the LOCOS interface due to the deviation coefficient of boron, to stably form the high resistance element 1 having a desired resistance value with little variation, and to perform wet oxidation of LOCOS oxidation. There is almost no effect on workability due to the two-stage oxidation of dry oxidation.

【0021】上述のLOCOS酸化膜下の高抵抗素子1
を形成した後は、従来の方法によって、P型半導体基板
11のNウェル31の領域には、PチャンネルMOSト
ランジスタ2を、P型半導体基板11には、Nチャンネ
ルMOSトランジスタ(図示せず)等を形成し、コンタ
クト窓開けや電極形成等を行い、図4に示すような半導
体集積回路を作製する。以上、本発明の2例の実施例で
説明した製造方法は、これら実施例に何ら限定されるも
のではない。例えば、LOCOS酸化時のウェット酸化
は蒸留水の加熱による水蒸気を使用してもよく、高エネ
ルギーのボロン打ち込み用マスクとしてCVDのSiO
2 膜等を利用してもよい。その他、本発明の技術的思想
の範囲内で、ボロンのイオン注入やLOCOS酸化の製
造条件は適宜変更が可能である。
High resistance element 1 under the LOCOS oxide film described above.
After the formation, the P-channel MOS transistor 2 is formed in the region of the N-well 31 of the P-type semiconductor substrate 11 and the N-channel MOS transistor (not shown) is formed in the P-type semiconductor substrate 11 by the conventional method. Then, a contact window is opened, electrodes are formed, and a semiconductor integrated circuit as shown in FIG. 4 is manufactured. As described above, the manufacturing method described in the two examples of the present invention is not limited to these examples. For example, wet oxidation at the time of LOCOS oxidation may use steam by heating distilled water, and CVD SiO is used as a mask for high-energy boron implantation.
Two membranes may be used. In addition, the manufacturing conditions of boron ion implantation and LOCOS oxidation can be appropriately changed within the scope of the technical idea of the present invention.

【0022】[0022]

【発明の効果】以上の説明から明らかなように、本発明
の半導体装置の製造方法によるLOCOS酸化膜下のチ
ャネルストッパ形成は、低エネルギーと高いエネルギー
によるボロンのイオン注入を行った後に、ウェット酸化
とドライ酸化の2段階酸化法をとることにより、高濃度
+ 拡散層と隣接する箇所での耐圧低下を押さえ、しか
もバードビーク部も含めたLOCOS酸化膜下のチャネ
ルストッパ機能を確実に持たせた精度よいボロン濃度制
御を可能にする。また、本発明の半導体装置の製造方法
によるLOCOS酸化膜下のボロン拡散層による高抵抗
素子の形成は、高いエネルギーによるボロンのイオン注
入を行った後に、ウェット酸化とドライ酸化の2段階酸
化法をとることにより、バラツキの少ない所望の抵抗値
もったLOCOS酸化膜下の高抵抗素子が安定して形成
でき、半導体装置の製造歩留りを改善できる。
As is apparent from the above description, the channel stopper formation under the LOCOS oxide film according to the method of manufacturing a semiconductor device of the present invention is performed by wet oxidation after boron ion implantation with low energy and high energy. By adopting the two-step oxidation method of dry oxidation, the decrease in breakdown voltage at a portion adjacent to the high-concentration N + diffusion layer was suppressed, and a channel stopper function under the LOCOS oxide film including the bird's beak portion was surely provided. Enables accurate boron concentration control. Further, according to the method for manufacturing a semiconductor device of the present invention, a high resistance element is formed by a boron diffusion layer under a LOCOS oxide film by performing a two-step oxidation method of wet oxidation and dry oxidation after ion implantation of boron with high energy. By doing so, a high resistance element under the LOCOS oxide film having a desired resistance value with less variation can be stably formed, and the manufacturing yield of semiconductor devices can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明を適応した実施例1の工程を、その工程
順に説明する概略断面図であり、(a)は低エネルギー
のボロンイオン注入によるボロン注入領域を形成した状
態、(b)は高エネルギーのボロンイオン注入によるボ
ロン注入領域を形成した状態、(c)はLOCOS酸化
してボロン拡散層を形成した状態である。
1A and 1B are schematic cross-sectional views for explaining the steps of Example 1 to which the present invention is applied, in the order of the steps, where FIG. 1A is a state in which a boron implantation region is formed by low energy boron ion implantation, and FIG. A state in which a boron-implanted region is formed by high-energy boron ion implantation, and (c) is a state in which a LOCOS oxidation is performed to form a boron diffusion layer.

【図2】LOCOS酸化をした時、LOCOS酸化膜と
P型半導体基板のボロン濃度分布を示したもので、
(a)は本発明の場合で、(b)は従来の場合である。
FIG. 2 shows a boron concentration distribution of a LOCOS oxide film and a P-type semiconductor substrate when LOCOS oxidation is performed.
(A) is the case of the present invention, and (b) is the conventional case.

【図3】本発明を適応した実施例2の工程を、その工程
順に説明する概略断面図であり、(a)は酸化防止膜の
SiN膜をパターニングした状態、(b)は高エネルギ
ーのボロンイオン注入によるボロン注入領域を形成した
状態、(c)はLOCOS酸化してボロン拡散層を形成
した状態である。
3A and 3B are schematic cross-sectional views illustrating the steps of Example 2 to which the present invention is applied, in the order of the steps, where FIG. 3A is a state in which a SiN film as an antioxidant film is patterned, and FIG. 3B is high energy boron. A state where a boron implantation region is formed by ion implantation is shown, and (c) is a state where a LOCOS oxidation is performed to form a boron diffusion layer.

【図4】本発明を適応した実施例2のLOCOS酸化膜
下の高抵抗素子を有する半導体集積回路の概略断面図で
ある。
FIG. 4 is a schematic cross-sectional view of a semiconductor integrated circuit having a high resistance element under a LOCOS oxide film according to a second embodiment of the present invention.

【図5】従来のLOCOS酸化膜下のチャネルストッパ
形成工程を、その工程順に説明する概略断面図であり、
(a)は低エネルギーのボロンイオン注入によるボロン
注入領域を形成した状態、(b)はLOCOS酸化して
ボロン拡散層を形成した状態である。
5A to 5C are schematic cross-sectional views illustrating a conventional step of forming a channel stopper under a LOCOS oxide film, in order of the steps.
(A) is a state in which a boron implantation region is formed by low-energy boron ion implantation, and (b) is a state in which a boron diffusion layer is formed by LOCOS oxidation.

【図6】従来のLOCOS酸化膜下の高抵抗素子形成工
程を、その工程順に説明する概略断面図であり、(a)
は酸化防止膜のSiN膜をパターンニングした状態、
(b)は低エネルギーのボロンイオン注入によるボロン
注入領域を形成した状態、(c)はLOCOS酸化して
ボロン拡散層による高抵抗素子を形成した状態である。
6A to 6C are schematic cross-sectional views illustrating a conventional high resistance element formation process under a LOCOS oxide film in the order of the process,
Is a state in which the SiN film of the antioxidant film is patterned,
(B) shows a state in which a boron-implanted region is formed by low-energy boron ion implantation, and (c) shows a state in which a high-resistance element is formed by LOCOS oxidation and a boron diffusion layer.

【符号の説明】[Explanation of symbols]

1 LOCOS酸化膜下の高抵抗素子 2 MOSトランジスタ 11 P型半導体基板 12 Nウェル 31 酸化膜 32 SiN膜 39 LOCOS酸化膜 40 チャネルストッパ 43 高抵抗素子 1 High-resistance element under LOCOS oxide film 2 MOS transistor 11 P-type semiconductor substrate 12 N well 31 Oxide film 32 SiN film 39 LOCOS oxide film 40 Channel stopper 43 High-resistance element

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に酸化防止膜を形成し、前
記半導体基板に形成する半導体集積回路のフィールド領
域になる前記酸化防止膜をフォトリソグラフィ法により
開口し、前記フィールド領域にチャネルストッパとする
ボロンをイオン注入した後、前記酸化防止膜をマスクに
熱酸化してLOCOS酸化膜を形成し、LOCOS酸化
膜下にチャネルストッパを形成する半導体装置の製造方
法において、 前記チャネルストッパとなるボロンをイオン注入する際
に、前記半導体基板表面に低エネルギーで打ち込むイオ
ン注入と、LOCOS酸化膜厚の略半分の値に相当する
半導体基板表面からの深さに高エネルギーで打ち込むイ
オン注入を施した後、前記酸化防止膜をマスクとして熱
酸化し前記LOCOS酸化膜を形成することを特徴とす
る半導体装置の製造方法。
1. An anti-oxidation film is formed on a semiconductor substrate, and the anti-oxidation film to be a field region of a semiconductor integrated circuit formed on the semiconductor substrate is opened by photolithography to serve as a channel stopper in the field region. In a method of manufacturing a semiconductor device, in which boron is ion-implanted, thermal oxidation is performed using the anti-oxidation film as a mask to form a LOCOS oxide film, and a channel stopper is formed under the LOCOS oxide film. At the time of implantation, ion implantation is performed with low energy on the surface of the semiconductor substrate, and ion implantation is performed with high energy at a depth from the surface of the semiconductor substrate corresponding to approximately half the LOCOS oxide film thickness. The LOCOS oxide film is formed by thermal oxidation using an antioxidant film as a mask. Method of manufacturing a body apparatus.
【請求項2】 請求項1に記載した半導体装置の製造方
法において、 LOCOS酸化工程を水蒸気と酸素ガスによるウェット
酸化工程と酸素ガスのみによるドライ酸化工程をこの順
序で施して、前記LOCOS酸化膜を形成することを特
徴とする半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the LOCOS oxidation step is performed by a wet oxidation step using water vapor and oxygen gas and a dry oxidation step using only oxygen gas in this order to form the LOCOS oxide film. A method of manufacturing a semiconductor device, which comprises forming the semiconductor device.
【請求項3】 半導体基板に形成される半導体集積回路
でフィールド領域のLOCOS酸化膜下に拡散層による
高抵抗素子を形成する半導体装置の製造方法において、 形成される前記LOCOS酸化膜厚の略半分の値に相当
する半導体基板表面からの深さに高エネルギーで打ち込
むボロンのイオン注入を施した後、前記酸化防止膜をマ
スクとして熱酸化によりLOCOS酸化膜を形成するこ
とで、前記LOCOS酸化膜下に拡散層による高抵抗素
子を形成する半導体装置の製造方法。
3. A method of manufacturing a semiconductor device in which a high resistance element is formed of a diffusion layer under a LOCOS oxide film in a field region in a semiconductor integrated circuit formed on a semiconductor substrate, wherein the LOCOS oxide film thickness is about half the thickness of the LOCOS oxide film. After implanting boron ions with a high energy into the depth from the surface of the semiconductor substrate corresponding to the value of, the LOCOS oxide film is formed by thermal oxidation using the antioxidant film as a mask. A method of manufacturing a semiconductor device in which a high resistance element is formed by a diffusion layer.
【請求項4】 請求項3に記載した半導体装置の製造方
法において、 LOCOS酸化工程を水蒸気と酸素ガスによるウェット
酸化工程と酸素ガスのみによるドライ酸化工程をこの順
序で施して、前記LOCOS酸化膜を形成することを特
徴とする半導体装置の製造方法。
4. The method of manufacturing a semiconductor device according to claim 3, wherein the LOCOS oxidation step is performed by a wet oxidation step using water vapor and oxygen gas and a dry oxidation step using only oxygen gas in this order to form the LOCOS oxide film. A method of manufacturing a semiconductor device, which comprises forming the semiconductor device.
JP14728595A 1995-06-14 1995-06-14 Fabrication method of semiconductor device Pending JPH097967A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14728595A JPH097967A (en) 1995-06-14 1995-06-14 Fabrication method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14728595A JPH097967A (en) 1995-06-14 1995-06-14 Fabrication method of semiconductor device

Publications (1)

Publication Number Publication Date
JPH097967A true JPH097967A (en) 1997-01-10

Family

ID=15426752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14728595A Pending JPH097967A (en) 1995-06-14 1995-06-14 Fabrication method of semiconductor device

Country Status (1)

Country Link
JP (1) JPH097967A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5829290A (en) * 1996-02-14 1998-11-03 Crown Cork & Seal Technologies Corporation Reshaping of containers
US5832766A (en) * 1996-07-15 1998-11-10 Crown Cork & Seal Technologies Corporation Systems and methods for making decorative shaped metal cans
US5960659A (en) * 1995-10-02 1999-10-05 Crown Cork & Seal Company, Inc. Systems and methods for making decorative shaped metal cans
CN111769047A (en) * 2020-09-03 2020-10-13 江苏应能微电子有限公司 A kind of high voltage metal oxide semiconductor terminal region manufacturing method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5960659A (en) * 1995-10-02 1999-10-05 Crown Cork & Seal Company, Inc. Systems and methods for making decorative shaped metal cans
US5829290A (en) * 1996-02-14 1998-11-03 Crown Cork & Seal Technologies Corporation Reshaping of containers
US5832766A (en) * 1996-07-15 1998-11-10 Crown Cork & Seal Technologies Corporation Systems and methods for making decorative shaped metal cans
US5970767A (en) * 1996-07-15 1999-10-26 Crown Cork & Seal Technologies Corporation Systems and methods for making decorative shaped metal cans
CN111769047A (en) * 2020-09-03 2020-10-13 江苏应能微电子有限公司 A kind of high voltage metal oxide semiconductor terminal region manufacturing method

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