JPH0969074A - Integrated circuit for serial communication - Google Patents

Abstract

The present invention relates to an integrated circuit for serial communication that transmits and receives signals between a plurality of printed circuit board units, has a small circuit scale, high signal transmission efficiency, and MPU processing efficiency. The purpose is to realize a high-performance integrated circuit for serial communication. In a serial communication integrated circuit for transmitting and receiving a plurality of signals between a master printed board unit and a plurality of slave printed board units, a multi-bit parallel signal from a control circuit of the master printed board unit is converted into a serial signal. To the slave printed circuit board unit and the serial signal received from the control circuit of the slave printed circuit board unit to a parallel signal of multiple bits to control the master printed circuit board unit. Serial to send to the circuit /
And a parallel conversion circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial communication integrated circuit for transmitting and receiving a plurality of signals between a plurality of printed board units.

Due to the sophistication and large scale of communication devices and information processing devices, it has become necessary to transmit and receive a large amount of signals between a plurality of printed board units. For example, 1
When one master printed board unit monitors a plurality of slave printed board units, the monitored items of each slave printed board unit may be, for example, 100 to 200 items. It is necessary to send and receive monitoring data in proportion to the number of plate units.

A master for performing such a circuit for transmitting and receiving various data between the printed board units with a circuit having a small structure, improving the data transmission efficiency, and monitoring and controlling the entire system. There is a demand for a circuit that can reduce the load on the control circuit (Micro Processor Unit, hereinafter referred to as MPU) of the printed board unit.

[0004]

2. Description of the Related Art FIG. 12 is a diagram for explaining a conventional example. Reference numeral 10 in the figure denotes a master printed board unit, and 21 to 2
n is a slave printed board unit.

In the configuration shown in the figure, the MPU 10A of the master print board unit 10 transmits data (SendData, hereinafter referred to as SD signal) for driving the lamps / relays of the slave print board units 21 to 2n, and at the same time, the slave print board. Data (Scan, hereinafter referred to as SCN signal) from the units 21 to 2n is collected to control and monitor the entire system.

In transmitting and receiving such a signal, the master printed board unit 10 and the slave printed board unit 21
2n is a control interface (indicated as INF in the figure) 10
a, 20a and the signal line S, and data is transmitted and received as parallel data between them.

FIG. 13 shows an operation sequence diagram of a conventional example. When the MPU 10A of the master printed board unit 10 issues a data write request, the control interface 1
0a through slave printed board unit 2i (21
Data is transmitted to the control interface 20a of any one of 2n to 2n), and the lamp / relay is driven according to this data.

On the other hand, the alarm information of the slave printed board unit 2i is written in a read register (not shown). When reading this alarm information from the MPU 10A, a data read request is issued from the MPU 10A of the master printed board unit 10 and transmitted to the control interface 20a of the slave printed board unit 2i through the control interface 10a. Then, in the slave printed board unit 2i, the data in the read register is read out, and the control interface 10a of the master printed board unit 10 is passed through the control interface 20a.
And is captured by the MPU 10A.

At this time, the MPU 10A is in a waiting state from issuing the data read request until receiving the response data, and it is impossible to perform other processing during this waiting time. The load is high.

[0010]

In the above-mentioned conventional example, when the SD signal and the SCN signal are transmitted and received, the parallel signal is transmitted and received.
In the case of a book, since the number of slave printed board units 21 to 2n is n, 8 × n signal lines S are required.

However, the slave printed board unit 21
The number n of 2n is increasing due to the increase in the scale of the system, and the number of signal lines S is also increasing. In order to solve such a problem, the parallel / serial conversion circuit and the serial / parallel conversion circuit are composed of discrete parts, and the master printed board unit 10 and the slave printed board units 21 to 2n are transmitted / received by serial data. Can be done, but if it is composed of discrete parts,
As the number of parts increases, the mounting space on the printed board is limited.

For example, using discrete components,
When the parallel / serial conversion circuit and the serial / parallel conversion circuit are configured, the following problems occur. -Due to the restrictions on the number of parts, it is difficult to communicate between one-to-many slave printed board units.

The number of transmission bits per slave printed circuit board unit cannot be increased. -Abnormality of the signal line and disconnection of the printed board unit cannot be detected.・ Slave printed circuit board unit 2i whose information you want to read
Information cannot be read immediately. There is a long wait time between sending a request and returning a response.

Since the interface section 10a is provided for the slave printed board unit, there is a restriction on the number of connectors to be connected to the interface section 10a.

According to the present invention, when a plurality of signals are transmitted and received between the master printed circuit board unit and the plurality of slave printed circuit board units, the circuit scale is small, the signal transmission efficiency is high, and the MPU processing efficiency is high. , An attempt is made to realize an integrated circuit for serial communication.

[0016]

FIG. 1 is a diagram for explaining an embodiment of the present invention. Reference numeral 10 in the figure denotes a master printed circuit board unit equipped with an MPU 10A for controlling and monitoring the entire system, and 100 denotes transmission and reception of a plurality of signals between the master printed circuit board unit 10 and a plurality of slave printed circuit board units (not shown). Serial communication integrated circuit (hereinafter referred to as serial communication LSI).

In the present invention, a parallel / serial signal conversion unit 120 that converts a parallel asynchronous signal of a plurality of bits from the MPU 10A of the master printed board unit into a serial synchronous serial signal and sends it to the slave printed board unit, A serial / parallel conversion circuit 220 for converting a serial synchronous signal from the slave printed board unit into an asynchronous parallel signal, a parallel / serial conversion circuit 120, and a serial / parallel conversion circuit 22.
Timing generator 1 for generating 0 operation timing signal
01 is provided, and the parallel asynchronous signal from the MPU 10A is converted into a synchronous serial signal to perform communication between the master printed board unit 10 and the slave printed board unit. (Claim 1) A random access memory 110 for transmission, which stores the latest write signal sent from the master printed board unit 10 to the slave printed board unit, and a random reception memory, which stores the latest state of the slave printed board unit. An access memory 210 and an address random access memory 310 for accumulating position information designating a position of a slave printed board unit for reading and writing from the master printed board unit are provided to write and read data.

Here, the master printed board unit 10 is used.
The asynchronous signal from the MPU 10A is written in the transmission random access memory 110 and the address random access memory 310, and the parallel / serial conversion circuit 12
0 to 320, the serial signal is converted into a serial signal and transmitted to the slave printed board unit, and the serial signal received from the slave printed board unit is converted into a parallel signal by the serial / parallel conversion circuit 220 and stored in the receiving random access memory 210. By writing, a small-sized serial communication LSI can be realized. (Claims 2, 3,
4) The data length from the parallel / serial conversion circuits 120 and 320 and the data length received by the serial / parallel conversion circuit 220 are set in 8-bit units by the data length setting unit 400. With such a data structure, it is possible to suppress the influence when a data error occurs. (Claim 5) According to the timing signal from the timing control circuit,
By transmitting the address signal and the write signal from the master printed board unit 10 and receiving the read signal from the slave printed board unit at the same time, the transmission efficiency of the write signal and the read signal can be improved. (Claim 6) The parity check unit 230 checks the parity of the signal received in 8-bit units, and when a parity error occurs, the data invalid processing unit 410 invalidates the read data. Similarly, the frame check unit 2
When it is detected that the slave printed board unit is missing at 40, the data read processing unit 410 invalidates the read data. (Claims 7 and 8) A serial communication LSI 101 for a master printed board unit and a serial communication LSI 102 for a slave printed board unit are mounted on the serial communication LSI 100, and one of them is selected and used. . (Claim 9)

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram for explaining an embodiment of the present invention. The master printed circuit board unit 10 in the figure is a random access memory (hereinafter referred to as RAM) 11 for transmitting an asynchronous parallel SD signal from the MPU 10A.
The slave print board unit that writes 0 to the SD signal and the address signal that specifies the row to which the SD signal is to be written is written to the address RAM 310 and sent to the slave print board unit. When the slave printed board unit receives the address signal and the address matches the address of its own slave printed board unit, SD
Capture signals. At the same time, the S received in the previous frame
The serial SCN signal corresponding to the D signal is taken into the receiving RAM 210 through the serial / parallel conversion circuit 220.

The timing generation unit 101 generates an operation timing signal, and the parallel / serial conversion circuits 120, 3
20, and the operation timing of the serial / parallel conversion circuit 220 is controlled.

FIG. 2 is a diagram for explaining the system configuration of the embodiment of the present invention. The figure shows an example in which the master printed board unit 10 and the slave printed board units 21 to 2n are connected using the serial communication integrated circuit of the present invention, and the master LSI is a serial communication LSI 101 (Card to Card).
Interface-Master (shown as LSI in the figure), and a slave LSI as a serial communication LSI 102.

With this configuration, the master printed board unit 1
The SD signal and the address signal designating the address for writing the SD signal from the MPU 10A of 0 are converted from parallel signals to serial signals by the serial communication LSI 101 and transmitted in parallel to the slave printed board units 21 to 2n. Each slave printed board unit 21 to 2n checks the received address signal, and when it matches the address of its own slave printed board unit 2i, takes in the SD signal.

Then, the slave printed circuit board unit 2i which has taken in the SD signal receives the SCN for the SD signal.
The signal is converted into a serial signal by the serial communication LSI 102 and transmitted to the master printed board unit 10.

As described above, the master printed board unit 10 and the slave printed board unit 21 are converted by converting the SD signal and the SCN signal into serial signals and transmitting / receiving them.
It is possible to reduce the number of signal lines between ~ 2n,
Further, it is possible to reduce the number of connectors mounted on the master printed board unit 10.

FIG. 3 shows another embodiment (1) of the present invention.
It is a figure explaining. The figure shows a configuration in which a data length setting unit 400 is added to the configuration of the embodiment described in FIG. From MPU 10A to slave printed board unit 2i
RAM1 for transmission when transmitting SD signal to
Data is written in 10 and the address RAM 310 in units of 8 bits. Then, in response to a control signal from the data length setting unit 400, the transmission RAM 110 and the address RA
The data written on M310 is transmitted on the signal line as an 8-bit unit serial signal.

FIG. 4 shows another embodiment (1) of the present invention.
It is a figure explaining transmission / reception of the data of. The figure shows that the slave printed board unit 2i receives the SD signal transmitted from the master printed board unit 10, and the write register 20A
In the following, an example is described in which the signal written to the master print board unit 10 is read, the signal written in the read register 20B is read, and the signal is sent to the master printed board unit 10 as the SCN signal.

Here, an example in which the write register 20A and the read register 20B are each composed of 8 bits × 16 columns of 128 bits is shown. Here, the SD signal is the signal of the 12th to 14th columns according to an instruction from the MPU 10A. An example of transmitting and updating the contents of the write register 20A and designating and transmitting only the first column as the SCN signal is shown.

In this way, the 8-bit unit SD signal, S
By transmitting / receiving the CN signal, the transmitted / received data are only the SD signal for the changed column and the SCN signal for the designated column, and the amount of transmitted / received data can be reduced.

Further, when a data error occurs on the signal line, the data is discarded in 8-bit units, so that the range affected by the error can be limited. In addition, a timing control circuit (not shown) controls the SD signal S and S in 8-bit units.
The efficiency of data transmission / reception can be improved by transmitting / receiving CN signals at the same time.

FIG. 5 shows another embodiment (2) of the present invention.
It is a figure explaining. The figure is based on the configuration of the embodiment described in FIG. 1, and includes a parity generation unit 130, 330, a parity check unit 230, and a data invalidation processing unit 4 that invalidates the data read when a parity error is detected.
10 is provided.

FIG. 6 shows another embodiment (3) of the present invention.
It is a figure explaining. In the figure, the configuration of the embodiment described in FIG. 1 is provided with a frame check unit 240 and a data invalidation processing unit 410 that invalidates the read data when a frame error is detected.

FIG. 7 is a diagram for explaining an embodiment of a serial communication LSI. The drawing incorporates all the components described in FIGS. 1 to 6, and converts parallel data from the MPU 10A (not shown) into serial data and transmits the serial data to the slave printed board unit. The functions of the data length setting unit 400, the data invalidation processing unit 410, and the timing control circuit (not shown) described in the embodiments (2) and (3) are included in the LSI control register 420.

Further, a transmission RAM access register (register in the figure is designated as REG) 111, a reception RAM access register 211, and an address RAM access register 311 are provided, and the MPU 1 is provided through these registers.
Data is written / read from 0A to the transmission RAM 110, the reception RAM 210, and the address RAM 310.

FIG. 8 shows a time chart of the embodiment of the present invention. The serial communication LSI 1 shown in FIG.
00 will be described. CCLK: Slave serial communication LSI 10
It is a basic timing signal to 1.

CMFCK: A timing signal for clarifying transmitted / received data, which is one frame with 12 clocks of CCLK. One frame of transmitted / received data is included in each one frame.

CCSEL; a signal for designating an address for transmitting an SD signal. The upper 4 bits designate the number (eg, ID) of the slave printed board unit, and the lower 4 bits designate the designated slave printed board unit 2
The column number of the write register 20A of i is designated. Next 1
The bit is a parity bit, and the next 3 bits are the bits for detecting the removal of the printed board unit, and are "H" when the printed board unit is removed.
If the bits are continuously "H", it is determined that the printed board unit is missing.

DDATA: SD signal, which is 8-bit data to be written. Are serial communication LSIs of slave printed board units 21 to 2n
100 (Card and Card Interface-Slave in the figure, CCI
(Denoted as S).

RE; slave printed board unit 2
This is a read enable signal for fetching the data of the designated column of the read register 20B of i into the slave printed board unit 2i.

RD: Indicates data taken into the slave printed board unit 2i by the read enable signal RE. WE: This is a register latch signal for the slave printed board unit 2i to take in the data transmitted from the master printed board unit 10.

WD: data to be written in the write register 20A. The serial communication LSI 10 of the master printed board unit 10 uses the data of the read register 20B fetched in step 1 as serial data with the next frame signal CMFCK.
0 (indicated as Card and Card Interface-Master, CCIM in the figure).

FIG. 9 is a diagram for explaining the multiplexing process of data transmission / reception of the present invention. The figure is in the time chart of FIG.
The operation for simultaneously transmitting and receiving data will be described. (A) shows data exchange between the serial communication LSI 101 on the master side and the serial communication LSI 102 on the slave side.

From the serial communication LSI 101 of the master printed board unit 10 to the slave printed board unit 2
When a read request for i is issued, a response to the request is returned, but the read request and the response are not performed sequentially, but the read request is issued and at the same time, the response to the previous read request is received. I am trying.

(B) shows the exchange of data as a bit string. For example, when the response 1 to the request 1 is returned, the next request 2 is issued. In this way, the request i and the response i-1 are transmitted and received at the same time, which improves the efficiency of data transmission and reception.

FIG. 10 shows an operation sequence diagram of the present invention. The figure shows the transmission and reception of data between the master printed board unit 10 and the slave printed board unit 2i as a sequence.

When a write request is issued from the MPU 10A of the master printed board unit 10 in (A), the data is transmitted to the serial communication LSI 102 of the slave printed board unit 2i through the serial communication LSI 101, and the data is written in the write register 20A. Drive the lamp / relay.

On the other hand, alarm information is written in the read register 20B of the slave printed board unit 2i, and the serial communication LSI 101 of the master printed board unit 10 is passed through the serial communication LSI 102.
Is written in the read RAM 210 and is read by a read request from the MPU 10A. The waiting time at this time is extremely short as compared with the conventional example of (B).

(B) is a reprint of the operation sequence diagram of the conventional example described in FIG. 13 for comparison. FIG.
The figure which shows the structure of the LSI for serial communication by this invention is shown. The serial communication LSI 100A of the present invention is
It has functions as a master and a slave, and one of them is selected and used. 101 in the figure is a serial communication LSI used in the master printed circuit board unit 10.
101, a transmission RAM 110 and a reception RAM 12
0, an address RAM 130, parallel / serial conversion circuits 120 and 320, and a serial / parallel conversion circuit 220.

On the other hand, the serial communication LSI 102 used in the slave printed board unit 2i has a serial / parallel conversion circuit 510 for converting the received serial data into parallel data, and write data for latching the data for writing in the read register 20A. Latch circuit 5
20, a read data latch circuit 620 for taking in the data of the read register 20B, and a parallel / serial conversion circuit 610 for converting the read parallel data into serial data.

Serial communication LSI 100 having such a configuration
Due to A, both the master printed board unit 10 and the slave printed board unit 2i can be used, and various management in manufacturing the printed board unit becomes easy.

[0050]

By using the serial communication LSI of the present invention to transmit / receive data between the master printed board unit and the slave printed board unit using serial data, the circuit scale and cost can be reduced.

Further, by providing the parity check unit and the frame check unit, it is possible to detect errors in data transmission / reception, frame errors, and missing mounting of the printed circuit board unit, and read when an error occurs. Data is invalid.

Further, by setting the unit of data transmission / reception to be an 8-bit unit, only the necessary data is transmitted / received, and the write request and its response are performed within the same frame signal, thereby improving the efficiency of data transmission / reception. Can be improved.

By providing a random access memory in the serial communication LSI, the access from the MPU is independent of the speed of serial communication between the master printed board unit and the slave printed board unit.
It is possible to perform processing according to the processing speed of and to eliminate the waiting time for reading from the MPU.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an embodiment of the present invention.

FIG. 2 is a diagram illustrating a system configuration of an embodiment of the present invention.

FIG. 3 is a diagram for explaining another embodiment (1) of the present invention.

FIG. 4 is a diagram illustrating data transmission / reception according to another embodiment (1) of the present invention.

FIG. 5 is a diagram for explaining another embodiment (2) of the present invention.

FIG. 6 is a diagram for explaining another embodiment (3) of the present invention.

FIG. 7 is a diagram illustrating an embodiment of a serial communication LSI.

FIG. 8 is a time chart of the embodiment of the present invention.

FIG. 9 is a diagram for explaining multiplexing processing of data transmission / reception of the present invention.

FIG. 10 is an operation sequence diagram of the present invention.

FIG. 11 is a diagram illustrating a configuration of a serial communication LSI of the present invention.

FIG. 12 is a diagram illustrating a conventional example.

FIG. 13 is an operation sequence diagram of a conventional example.

[Explanation of symbols]

10 Master Printed Circuit Board Unit 10A MPU 10a, 20a Control Interface 100, 101, 102, 100A Serial Communication L
SI 101 Timing generation unit 102 Address decoding unit 103 Input / output data buffer unit 110 Transmission RAM 111 Transmission RAM access REG 120, 320, 610 P / S conversion circuit 130, 330 Parity generation unit 210 Reception RAM 211 Reception RAM access REG 220, 510 S / P conversion circuit 230 Parity check unit 240 Frame check unit 310 Address RAM 311 Address RAM access REG 400 Data length setting unit 410 Data invalidation processing unit 420 LSI control register 520 Write data latch circuit 620 Read data latch Circuits 21 to 2n Slave printed circuit board unit 20A Write register 20B Read register S Signal line

Claims (9)

[Claims] 1. A serial communication integrated circuit for transmitting and receiving a plurality of signals between a master printed board unit and a plurality of slave printed board units, wherein a parallel signal of a plurality of bits from a control circuit of the master printed board unit, A parallel / serial conversion circuit for converting into a serial signal and transmitting to the slave printed board unit, and a serial signal received from the slave printed board unit is converted into a parallel signal of a plurality of bits, and the master printed board unit Serial / parallel conversion circuit for transmitting to the control circuit, and a timing generation unit for generating an operation timing signal of the parallel / serial conversion circuit and the serial / parallel conversion circuit. circuit. 2. In a serial communication integrated circuit for transmitting and receiving a plurality of signals between a plurality of printed board units, the latest write data sent from the control circuit of the master printed board unit to the slave printed board unit. 2. The serial communication integrated circuit according to claim 1, further comprising a random access memory for transmission for storing the data. 3. A serial communication integrated circuit for transmitting and receiving a plurality of signals between a plurality of printed board units, wherein a random access memory for reception in which the latest read data of the slave printed board unit is stored in the master printed board unit. The integrated circuit for serial communication according to claim 1, further comprising: 4. In a serial communication integrated circuit for transmitting and receiving a plurality of signals between a plurality of printed board units, position information for designating a position of the slave printed board unit for reading and writing from the master printed board unit is stored. The serial communication integrated circuit according to claim 1, further comprising an address random access memory. 5. In a serial communication integrated circuit for transmitting and receiving a plurality of signals between a plurality of printed board units, a data length transmitted from the master printed board unit to the slave printed board unit, and a slave printed board unit. 2. The integrated circuit for serial communication according to claim 1, wherein the master printed board unit is provided with a data length setting section for setting a data length for receiving and processing in units of 8 bits. 6. In a serial communication integrated circuit for transmitting and receiving a plurality of signals between a plurality of printed board units, the data transmitted from the master printed board unit to the slave printed board unit is converted into a serial signal in units of 8 bits. Timing for operating the parallel / serial conversion circuit and the serial / parallel conversion circuit for converting 8-bit unit data transmitted from the slave printed circuit board unit and received by the master printed circuit board unit into parallel signals with the same timing frame signal The integrated circuit for serial communication according to claim 5, further comprising a control circuit. 7. In a serial communication integrated circuit for transmitting and receiving a plurality of signals between a plurality of printed board units, a parity generation unit for generating a parity of data to be transmitted to the slave printed board unit and a parity of received data are provided. 5. The serial communication according to claim 2, wherein a parity check unit for checking and a data invalidation processing unit for invalidating read data when the parity check unit detects an error in received data are provided. Integrated circuit. 8. In a serial communication integrated circuit for transmitting and receiving a plurality of signals between a plurality of printed board units, a frame check unit for checking the normality of the frame signal, and the frame check unit is a slave printed board unit. 4. A data invalidation processing unit for invalidating the read data when the omission is detected.
4. The integrated circuit for serial communication according to item 4. 9. A serial communication integrated circuit for transmitting and receiving a plurality of signals between a plurality of printed board units, comprising: a serial communication integrated circuit for a master printed board unit and a serial communication integrated circuit for a slave printed board unit. An integrated circuit for serial communication, wherein the integrated circuit for serial communication is implemented by switching between a master and a slave.