JPH0964732A - Synchronization clock generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress fluctuation in a phase between output clocks of plural PLL circuits connected in cascade when a reference clock is switched. SOLUTION: The circuit is provided with a phase locked loop circuit 3 synchronizing an output clock with an input clock and decreasing a loop gain in response to a request of a hold-over state, a clock selection circuit 1 applying selectively plural reference clocks to the phase locked loop circuit 3, and an input interrupt detection circuit 2 detecting interruption of the selection clock of the clock selection circuit 1, providing an instruction to the clock selection circuit 1 to select other clock, requesting a hold-over state to the phase locked loop circuit 3 and requesting release of the hold-over state after selection of the clock is switched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous clock generation circuit used in optical communication devices and the like.

[0002]

2. Description of the Related Art A synchronous clock generation circuit used in a synchronous timing control system of an optical communication device which requires high reliability has several reference clocks, and even if one clock is cut off, another Select a clock and keep supplying clock to the device. FIG. 3 shows a configuration example of a conventional synchronous clock generation circuit.

In FIG. 3, there are two reference clocks A and B, and when the A clock is in a disconnected state, the input disconnection detection circuit (IND) 1 detects it and the selection circuit (SEL) 2 is detected. Give an instruction to select the B clock.

The B clock selected by the selection circuit 2 is input to the first PLL circuit (PLL1) 3. This P
The LL circuit 3 generates a clock synchronized with the B clock,
It becomes the first reference clock OUT1 of the output destination.
This first reference clock OUT1 is the second PL
The second reference clock OUT2 is input to the L circuit (PLL2) 4 and is synchronized with OUT1.

However, in the conventional synchronous clock generating circuit as described above, since the first PLL circuit locks to a new clock when the reference clock is switched,
A sudden phase change appears in the output clock. The second PLL circuit 4 cannot follow this abrupt phase fluctuation, and the phase difference between the output clocks OUT1 and OUT2 fluctuates, resulting in a device error.

FIG. 4 shows how the phase changes. As is clear from this figure, at the moment when the A clock is switched to the B clock and the B clock is locked, the output clock O
A sudden phase change appears between UT1 and OUT2.

[0007]

As described above, in the conventional synchronous clock generation circuit, abrupt phase fluctuation appears in the output of the PLL circuit at the time of switching the reference clocks, and the output clocks of the plurality of cascaded PLL circuits are different from each other. There was a problem that the phase of fluctuated.

The present invention has been made to solve the above problems, and a synchronous clock generation circuit capable of suppressing the phase fluctuation between output clocks of a plurality of cascaded PLL circuits even when a reference clock is switched. The purpose is to provide.

[0009]

To achieve the above object, a synchronous clock generation circuit according to the present invention is a phase locked loop which synchronizes an output clock with an input clock and lowers a loop gain in response to a holdover state request. Circuit, a clock selection circuit that selectively supplies a plurality of reference clocks to the phase-locked loop circuit, and an instruction to detect a disconnection of the selection clock of the clock selection circuit and select another clock to the clock selection circuit In addition, the phase-locked loop circuit is configured to include an input disconnection detection circuit that requests a holdover state and requests release of the holdover state after switching the clock selection.

The phase locked loop circuit includes a phase comparison circuit for comparing the phases of an input clock and a feedback clock, an analog filter circuit for averaging the comparison output of this circuit, and an averaged output of this circuit as a digital value. An analog / digital conversion circuit for conversion, a digital filter circuit for reducing a loop gain in accordance with a holdover state requirement for a digital output of this circuit, a digital / analog conversion circuit for converting a digital output of this circuit into an analog signal, and this circuit A clock generator for generating a clock having a frequency corresponding to the analog output of 1 and a frequency dividing counter for dividing the output clock of the clock generator into the frequency of the input reference clock to use as the feedback clock are provided.

The input break detection circuit requests the release of the holdover state in the process in which the phase locked loop circuit locks to the clock after switching. In the synchronous clock generation circuit with the above configuration, the next-stage phase-locked loop circuit outputs the output of the preceding-stage phase-locked loop circuit by requesting the hold-over state to the preceding-stage phase-locked loop circuit at the time of switching the reference clock to reduce the loop gain. The change is made to follow so that abrupt changes in phase difference do not appear between output clocks.

The phase locked loop circuit converts the output of the analog filter circuit into a digital signal, reduces the gain by digital processing, and returns it to the analog signal again, thereby enabling accurate control.

Further, by requesting a holdover state in the process in which the phase locked loop circuit locks to the clock after switching, the loop gain is made so small that it cannot be locked, and further fluctuation of the phase difference is suppressed. .

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings. In FIG. 1, the same parts as those in FIG. 3 are designated by the same reference numerals, and different parts will be mainly described here.

FIG. 1 shows the configuration of a synchronous clock generation circuit according to the present invention. The reference clock A or B selected by the selection circuit 2 is input to the phase comparison circuit (PC) 31 of the first PLL circuit 3. And the phase is compared with the feedback clock, and the comparison result is the analog filter circuit (AF
(IL) 32 and averaged. The signal averaged here is an A / D (analog / digital) conversion circuit (A
/ D) 33 and is converted into a digital value. The signal converted into the digital value is input to the digital filter circuit (DFIL) 34. This digital filter circuit 34 is made of a CPU and has a hold function, which will be described later.
It has a function to adjust loop gain or loop time constant.

The output of the digital filter circuit 34 is D / A.
The voltage control signal is input to the (digital / analog) conversion circuit (D / A) 35, and a voltage control signal to the voltage controlled oscillator (VCXO) 36 at the subsequent stage is generated. The oscillator 36 controls the frequency of the output clock according to the level of the voltage control signal, and the clock generated here is output as the first reference clock OUT1 and is input to the frequency division counter (COUNTER) 37. It is divided into a clock having the same frequency as the input reference clock, and is input to the phase comparison circuit 31 as a feedback clock.

On the other hand, when the input interruption detection circuit 1 detects the interruption of the reference clock, it gives an instruction for selecting another clock to the selection circuit 2 and, at the same time, requests the digital filter circuit 34 for a holdover state. The "holdover state" means that the clock that has been input up to that point continues to be output and the information of the signals whose phases are compared in that state is ignored.

In the above configuration, the processing operation when the reference clock A is cut off will be described below with reference to FIG. First, the A clock is selected, and when the A clock is cut off, the input cutoff detection circuit 1 requests the digital filter circuit 8 for a holdover state. Upon receiving this request, the digital filter circuit 8 simultaneously reduces the loop gain. This brings the PLL circuit into the holdover state. In this state, changing the loop characteristics does not affect the output clock OUT1.

After that, the input disconnection detection circuit 1 requests the digital filter circuit 34 to release the holdover state when detecting that the B clock has been completely switched. As a result, the first PLL circuit 3 is locked to the B clock selected by the selection circuit 1.

At this time, the loop gain is reduced by the digital filter circuit 34. Therefore, the second
The PLL circuit 4 becomes capable of following the change in the output of the first PLL circuit 3, and no sudden change in the phase difference appears between the output clocks OUT1 and OUT2.

Therefore, in the synchronous clock generating circuit having the above-mentioned configuration, the output clocks OUT1 and OUT of the PLL circuits 3 and 4 cascaded even when the reference clock is switched
The fluctuation of the phase between the two can be suppressed.

The present invention is not limited to the above embodiment. For example, as shown by the dotted line in FIG.
By locking the timing for returning the loop gain of the PLL circuit 3 to the B clock, the loop gain can be made so small that it cannot be locked, so that further fluctuation of the phase difference can be suppressed. Needless to say, various modifications can be made in the same manner without departing from the scope of the present invention.

[0023]

As described above, according to the present invention, it is possible to provide a synchronous clock generation circuit capable of suppressing the fluctuation of the phase between the output clocks of a plurality of cascaded PLL circuits even when the reference clock is switched. You can

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a configuration of an embodiment of a synchronous clock generation circuit according to the present invention.

FIG. 2 is a timing waveform chart for explaining the operation of the above embodiment.

FIG. 3 is a block circuit diagram showing a configuration of a conventional synchronous clock generation circuit.

FIG. 4 is a diagram showing a conventional circuit for switching a reference clock when switching a reference clock
It is a timing waveform diagram which shows the sudden phase fluctuation which appears in the L circuit output.

[Explanation of symbols]

1 ... Selection circuit, 2 ... Input disconnection detection circuit, 3 ... First PLL
Circuit, 31 ... Phase comparison circuit, 32 ... Analog filter circuit, 33 ... A / D conversion circuit, 34 ... Digital filter circuit, 35 ... D / A conversion circuit, 36 ... Voltage controlled oscillator, 3
7 ... Frequency division counter, 4 ... Second PLL circuit.

Claims (3)

[Claims] 1. An output clock is synchronized with an input clock,
A phase locked loop circuit that lowers the loop gain in response to a holdover state request, a clock selection circuit that selectively supplies a plurality of reference clocks to the phase locked loop circuit, and a disconnection of the selected clock of the clock selection circuit And an instruction to select another clock to the clock selection circuit, request the phase-locked loop circuit for a holdover state, and request the release of the holdover state after switching the clock selection. Synchronous clock generation circuit. 2. The phase-locked loop circuit comprises: a phase comparison circuit for comparing the phases of an input clock and a feedback clock; an analog filter circuit for averaging the comparison output of this circuit; and a digital averaging output of this circuit. An analog / digital conversion circuit that converts the value to a value, a digital filter circuit that reduces the loop gain according to the holdover state requirement for the digital output of this circuit, and a digital / analog conversion circuit that converts the digital output of this circuit to an analog signal A clock generator for generating a clock having a frequency corresponding to the analog output of this circuit, and a frequency division counter for dividing the output clock of the clock generator to the frequency of the input reference clock to use as the feedback clock are provided. The synchronous clock generation circuit according to claim 1, wherein . 3. The synchronous clock generation circuit according to claim 1, wherein the input break detection circuit requests release of a holdover state in the process in which the phase locked loop circuit locks to the clock after switching. .