JPH0964040A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Object] To provide a technique capable of flattening a wiring formed in an insulating film when a semiconductor device having a multilayer wiring structure is manufactured. [Structure] The lower layer wiring 14 and the upper layer wiring 18 constituting the multilayer wiring structure are respectively formed in the grooves 13 and 17 formed in the lower layer insulating film 11 and the upper layer insulating film 15, respectively.
The surface is flattened and embedded so that the surface has a height corresponding to the surfaces of the grooves 13 and 17. Thus, when manufacturing a semiconductor device having a multilayer wiring structure, it is possible to flatten the wiring formed in the insulating film and prevent wiring defects such as short circuit defects and disconnection defects due to the wiring shape. Can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a technique effective when applied to a semiconductor device having a multilayer wiring structure in which a lower layer wiring is electrically connected to an upper layer wiring through an interlayer insulating film. It is a thing.

[0002]

2. Description of the Related Art In recent semiconductor devices represented by LSI, the integration density of circuit elements formed on a semiconductor substrate has been increasing more and more as the degree of integration is improved. Along with this, the area occupied by each circuit element on the semiconductor substrate tends to be further reduced, and on the other hand, the area occupied by the wiring connecting each circuit element is increasing in inverse proportion to this.

For this reason, a multi-layer wiring structure has been adopted in which the wiring is three-dimensionally formed in the thickness direction of the semiconductor substrate. According to this multi-layer wiring structure, wiring that has been laid in a horizontal plane on the semiconductor substrate can be separately laid vertically in the lower layer wiring and the upper layer wiring through the interlayer insulating film. The degree of freedom can be given to the arrangement of the circuit elements.

To form such a multilayer wiring structure,
Since it is necessary to route the wiring separately for the lower layer wiring and the upper layer wiring, after first forming the lower layer insulating film on the semiconductor substrate and forming a contact hole at this desired position, first, the lower layer insulation including this contact hole is formed. A lower layer wiring is formed on the surface of the film so as to be electrically connected to a desired region formed on the semiconductor substrate. Next, an upper insulating film is formed so as to cover the lower insulating film and the lower wiring, a contact hole is formed at this desired position, and the lower wiring is electrically connected to the surface of the upper insulating film including the contact hole. An upper layer wiring is formed on the substrate.

[0005] For example, "Latest LS" issued by Industrial Research Institute Co., Ltd.
I Process Technology ", issued January 20, 1991, P36
3 to P371 describe a technique relating to such a multilayer wiring structure.

[0006]

In order to form the above-mentioned multilayer wiring structure, after forming the upper layer insulating film so as to cover the lower layer wiring formed so as to extend to the surface of the lower layer insulating film, Since the upper layer wiring is formed so as to extend to the surface of the upper layer insulating film, a step is formed in the upper layer insulating film. For this reason, the shape of the upper-layer wiring formed to extend to the surface of the upper-layer insulating film is reflected in the step difference and lacks flatness. There is a problem that wiring failure easily occurs.

For example, when the degree of the step difference in the upper layer insulating film becomes large, the thickness of that portion partially becomes thin, so that pinholes are formed. Therefore, when the upper layer wiring is formed, this upper layer wiring is It becomes short-circuited with the lower layer wiring through the pinhole. Alternatively, if the degree of flatness of the upper layer wiring becomes small, the disconnection will partially occur. The short circuit failure and the disconnection failure are more likely to occur as the number of layers of the multilayer wiring increases.

An object of the present invention is to provide a technique capable of flattening a wiring formed in an insulating film when manufacturing a semiconductor device having a multilayer wiring structure.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows.

(1) A semiconductor device according to the present invention is a semiconductor device having a multilayer wiring structure in which a lower layer wiring drawn from a desired region formed on a semiconductor substrate is electrically connected to an upper layer wiring through an interlayer insulating film. The lower-layer wiring and the upper-layer wiring are flattened and embedded in the grooves formed in the lower-layer insulating film and the upper-layer insulating film, respectively, so that the surface of each wiring has a height corresponding to the surface of each groove.

(2) The method of manufacturing a semiconductor device according to the present invention comprises:
Forming a groove having a contact hole in the lower insulating film of the semiconductor substrate on which the lower insulating film is formed;
The step of forming a conductive material to be a lower layer wiring on the surface of the lower insulating film including the groove, and the unnecessary portion is removed by etching the conductive material so that the surface of the groove matches the surface of the groove. A step of forming a lower layer wiring that is flattened and buried so as to have a height; a step of forming an upper layer insulating film so as to cover the lower layer insulating film and the lower layer wiring; and a contact hole in a part of the upper layer insulating film. A step of forming a groove having, a step of forming a conductive material to be an upper wiring on the surface of an upper insulating film including the groove, and a step of removing unnecessary portions by etching the conductive material And a step of forming a buried upper layer wiring so that the surface has a height corresponding to the surface of the groove.

[0013]

According to the above-described means (1), in the semiconductor device of the present invention, the lower layer wiring and the upper layer wiring constituting the multilayer wiring structure are provided in the respective grooves formed in the lower layer insulating film and the upper layer insulating film, respectively. Since each wiring surface is flattened and buried so as to have a height corresponding to the surface of each groove, when manufacturing a semiconductor device having a multilayer wiring structure, the wiring formed on the insulating film should be flattened. Is possible.

According to the above-described means (2), in the method of manufacturing a semiconductor device of the present invention, a groove having a contact hole is partially formed in the lower insulating film of the semiconductor substrate on which the lower insulating film is formed. A step, a step of forming a conductive material to be a lower layer wiring on the surface of the lower insulating film including the groove, and an unnecessary portion is removed by etching the conductive material so that the surface in the groove is the surface of the groove. A step of forming a lower layer wiring which is flattened and buried so as to have a height corresponding to the step, a step of forming an upper layer insulating film so as to cover the lower layer insulating film and the lower layer wiring, and a part of the upper layer insulating film. By forming a groove having a contact hole, forming a conductive material to be an upper wiring on the surface of the upper insulating film including the groove, and etching the conductive material to remove unnecessary portions, In the case of manufacturing a semiconductor device having a multi-layer wiring structure, the insulating layer is formed in the groove so that the surface of the groove is flattened so that the surface has a height corresponding to the surface of the groove. It is possible to flatten the wiring formed on the film.

The present invention will now be described in detail with reference to the drawings along with embodiments.

In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

[0017]

【Example】

(Embodiment 1) FIG. 1 is a cross-sectional view showing a semiconductor device according to Embodiment 1 of the present invention, showing an example in which a bipolar transistor is formed on a semiconductor substrate and an electrode layer is drawn out from this emitter region by a multilayer wiring structure. ing. The semiconductor device according to the present embodiment has a plurality of N-type regions 2A that are insulated and separated from each other on a semiconductor substrate 1 made of, for example, a P-type silicon single crystal substrate.
2B, 2C ... Are formed, and an NPN type bipolar transistor (hereinafter, simply referred to as transistor) Q is formed in one N type region 2B. Also, other N
Arbitrary circuit elements are formed in the mold regions 2A and 2C.

3 is an N + type buried layer, 4 is an N type collector region, 5 is a P type base region, 6 is an N + type emitter region, 7
Is an N + type collector contact region, 8 is a collector electrode layer, 9 is a base electrode layer, 10 is an emitter electrode layer, and 11 is a lower insulating film made of an oxide film (SiO ₂ ). Here, the emitter electrode layer 10 has the following multilayer wiring structure as shown in an enlarged view in FIG.

A groove 13 having a contact hole 12 in a part thereof is formed in the lower insulating film 11, and an Al alloy whose surface is flattened so that the surface of the groove 13 coincides with the surface of the groove 13. A lower layer wiring 14 made of, for example, is buried. Further, an upper layer insulating film 15 made of an oxide film or the like is formed so as to cover the lower layer insulating film 11 and the lower layer wiring 14, and a groove 17 having a contact hole 16 is partially formed in the upper layer insulating film 15. There is. As a position where the contact hole 16 is formed, an arbitrary position on the lower layer wiring 14 is selected.

In the groove 17, an upper wiring 18 made of an Al alloy or the like, which is flattened so that its surface is flush with the surface of the groove 17, is embedded. As a result, the lower layer wiring 14 and the upper layer wiring 18 are electrically connected through the contact hole 16. The upper layer wiring 18 extends to the side end position of the semiconductor substrate 1 as shown in the figure, and is electrically connected to, for example, a pad electrode. A final insulating film 19 made of an oxide film or the like covers the entire semiconductor substrate 1 to protect the semiconductor device from the external atmosphere.

With the above structure, the lower wiring 14
Thus, the emitter electrode layer 10 formed in a multilayer wiring structure including the upper wiring 18 and the upper wiring 18 is obtained.

Next, a method of manufacturing the semiconductor device of this embodiment will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 4, each region constituting the transistor Q is formed inside, and the lower insulating film 11 made of an oxide film or the like and having a thickness of about 1 to 2 μm is formed on the surface.
A semiconductor substrate 1 formed of, for example, a P-type silicon single crystal substrate is prepared. At this point, collector electrode layer 8 and base electrode layer 9 are assumed to be formed in N + collector contact region 7 and P-type base region 5, respectively.

Next, as shown in FIG. 5, the lower insulating film 11 is formed.
Forming a resist 20 on a desired portion of the
A dry etching process is performed using 0 as a mask to form a groove 13 in which the lower layer wiring is to be buried as described later. The width and the depth of the groove 13 are determined by the current density required for the operation of the semiconductor device. For example, the width is about 2 to 3 μm.
m, and the depth is about 0.5 to 1.0 μm.

Subsequently, as shown in FIG. 6, the lower insulating film 1
A resist 20 is formed on desired portions of the groove 1 and the groove 13, and dry etching is performed using the resist 20 as a mask to form a contact hole 12 in the lower insulating film 11. The position of this contact hole 12 is selected arbitrarily on the N + emitter region 6.

Next, as shown in FIG. 7, C is formed on the surface of the lower insulating film 11 including the groove 13 and the contact hole 12.
VD (Chemical Vapor Deposit)
Ion) method or PVD (Physical Va)
Por Deposition) method, etc.
The conductive material 21 to be the lower layer wiring such as an alloy has a thickness of about 1 to 2
It is formed to a thickness of μm.

Then, as shown in FIG. 8, a dry etching process is performed to remove unnecessary portions of the conductive material 21.
This is because the conductive material 21 is entirely dry-etched and gradually removed, and the dry-etching process is stopped when the surface of the lower insulating film 11 is visible. As a result, the surface of the lower insulating film 11 has a groove 13 inside the groove 13.
The lower layer wiring 14 which is flattened and buried so as to have a height corresponding to the surface of is formed.

Next, as shown in FIG. 9, a CVD method and a PV method are used.
A thickness of about 1 to 2 μm made of an oxide film or the like so as to cover the surfaces of the lower insulating film 11 and the lower wiring 14 by D or the like.
The upper insulating film 15 is formed.

Then, as shown in FIG. 10, a dry etching process similar to that shown in FIGS. 5 and 6 is performed to form a groove 17 in which the lower layer wiring having the contact hole 16 is buried in the upper layer insulating film 15. The width and depth of this groove 17 are
Similar to the case of the groove 13, it is determined by the current density required for the operation of the semiconductor device, and is formed to have a width of about 2 to 3 μm and a depth of about 0.5 to 1.0 μm, for example, similar to the groove 13. To be done.

Next, as shown in FIG. 11, on the surface of the upper insulating film 15 including the groove 17 and the contact hole 16,
A conductive material 21 to be an upper layer wiring such as an Al alloy is formed to have a thickness of about 1 to 2 μm by the CVD method or the PVD method.

Subsequently, as shown in FIG. 12, a dry etching process similar to that of FIG. 8 is performed to remove unnecessary portions of the conductive material 21. As in FIG. 8, the conductive material 21 is entirely dry-etched and gradually removed, and the dry-etching process is stopped when the surface of the upper insulating film 15 is visible. Thereby, the upper insulating film 1
In the groove 17 of No. 5, a lower layer wiring 18 is formed which is flattened and buried so that the surface has a height matching the surface of the groove 17.

Next, a final insulating film 19 made of an oxide film and having a thickness of about 1 to 2 μm is formed so as to cover the surfaces of the upper insulating film 15 and the upper wiring 18 by the CVD method or the PVD method. Thus, the semiconductor device of FIG. 1 is manufactured.

According to this embodiment, the following effects can be obtained.

The lower layer wiring 14 and the upper layer wiring 18 constituting the multi-layer wiring structure are provided in the respective grooves 13 and 17 formed in the lower layer insulating film 11 and the upper layer insulating film 15, respectively.
Since the surface 8 is flattened and buried so as to have a height corresponding to the surfaces of the grooves 13 and 17, when the semiconductor device having the multilayer wiring structure is manufactured, the wiring formed on the insulating film is flattened. It becomes possible to do.

Therefore, when forming a multilayer wiring structure,
It is possible to prevent a wiring defect such as a short circuit defect or a disconnection defect due to the wiring shape from occurring.

(Embodiment 2) FIG. 3 is a sectional view showing a semiconductor device according to Embodiment 2 of the present invention. In the semiconductor device of Embodiment 1, between the lower layer wiring 14 and the upper layer wiring 18,
The intermediate layer wiring 23 is formed through the intermediate layer insulating film 22,
It shows an example in which a multilayer wiring structure of three layers is formed.

Also in the semiconductor device of this embodiment, the inside of the groove 25 having the contact hole 24 formed in the intermediate insulating film 22 is flattened so that the surface has a height corresponding to the surface of the groove 25. Since the intermediate layer wiring 23 made of Al alloy or the like is buried, the same effect as that of the first embodiment can be obtained. The semiconductor device of the second embodiment can be manufactured according to the manufacturing method of the first embodiment.

As described above, the invention made by the present inventor is:
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

For example, in the above-mentioned embodiment, an example of manufacturing a semiconductor device having a two-layer or three-layer multi-layer wiring structure has been described, but the same can be applied to the case of forming a multi-layer wiring structure of four or more layers. ..

Further, in the above-mentioned embodiment, an example in which the multilayer structure is formed by targeting the emitter electrode layer has been described, but the present invention is not limited to this, and a desired region of the semiconductor substrate can be targeted.

Further, the dimensions such as thickness and width of each insulating film and wiring constituting the multilayer wiring structure are merely examples, and these values can be changed according to the purpose and application.

Furthermore, in the above-described embodiment, an example in which a bipolar transistor is formed as an active element on a semiconductor substrate has been described, but the present invention is not limited to this, and a MOS transistor may be formed.

In the above description, the case where the invention made by the present inventor is mainly applied to the technology of the semiconductor device which is the field of application which is the background of the invention has been described, but the invention is not limited thereto. The present invention can be applied to the condition of forming a multi-layer wiring structure in which at least one wiring is divided into a plurality of wirings in the thickness direction of the semiconductor substrate and is routed.

[0044]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

The lower-layer wiring and the upper-layer wiring constituting the multi-layer wiring structure are flattened so that the surface of each wiring is in the groove formed in the lower-layer insulating film and the upper-layer insulating film, respectively, so that the height of the wiring surface is the same as the surface of each groove. Since it is embedded in the semiconductor device, the wiring formed in the insulating film can be flattened when manufacturing a semiconductor device having a multilayer wiring structure.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing an enlarged main part of FIG.

FIG. 3 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing a step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing another process of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view showing another process of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a cross-sectional view showing another process of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 11 is a cross-sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 12 is a cross-sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[Explanation of symbols]

1 ... Semiconductor substrate, 2, 2A, 2B, 2C ... N type region, 3
... N + type buried layer, 4 ... N type collector region, 5 ... P type base region, 6 ... N + type emitter region, 7 ... N + type collector contact region, 8 ... Collector electrode layer, 9 ... Base electrode layer, 10 ... Emitter electrode layer, 11 ... Lower insulating film, 12,
16, 24 ... Contact holes, 13, 17, 25 ...
Grooves, 14 ... Lower layer wiring, 15 ... Upper layer insulating film, 18 ... Upper layer wiring, 19 ... Final insulating film, 20 ... Resist, 21 ... Conductive material, 22 ... Intermediate layer insulating film, 23 ... Intermediate layer wiring.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H05K 3/46

Claims (5)

[Claims] 1. A semiconductor device having a multi-layer wiring structure in which a lower layer wiring drawn from a desired region formed on a semiconductor substrate is electrically connected to an upper layer wiring through an interlayer insulating film, wherein the lower layer wiring and the upper layer wiring are A semiconductor device in which each wiring surface is flattened and embedded in each groove formed in each of the lower insulating film and the upper insulating film so that each wiring surface has a height corresponding to the surface of each groove. 2. The semiconductor device according to claim 1, wherein a contact hole is partially formed in each groove of each insulating film in which the lower layer wiring and the upper layer wiring are buried. 3. The semiconductor device according to claim 2, wherein the lower layer wiring and the upper layer wiring buried in each groove are electrically connected through the contact hole. 4. A step of forming a groove having a contact hole in a part of the lower insulating film of a semiconductor substrate on which a lower insulating film is formed, and a conductive material which becomes a lower wiring on a surface of the lower insulating film including the groove. And a step of forming a lower layer wiring in which the surface is flattened and buried in the groove so as to have a height corresponding to the surface of the groove by etching the conductive material to remove unnecessary portions. A step of forming an upper insulating film so as to cover the lower insulating film and the lower wiring, forming a groove having a contact hole in a part of the upper insulating film, and forming an upper insulating film including the groove. A step of forming a conductive material to be an upper layer wiring on the surface and etching the conductive material to remove unnecessary portions are flattened in the groove so that the surface has a height corresponding to the surface of the groove. hand And a step of forming a buried upper layer wiring. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the lower layer wiring is formed so as to be electrically connected to a desired region previously formed on the semiconductor substrate.