JPH096320A - Image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deviation of each image data in the vertical direction before and after the terminal section (border line) of the frame memory determined by the horizontal virtual screen width. SOLUTION: After setting each register externally, a start address (display start address) is loaded on an address counter 1 from a display start address register 3 to cause addressing by a count-up operation and transfer the image data at the designated address on the frame memory 2 to an LCD screen for display. After that, in the case where the count value of the address counter 1 exceeds the address value before the terminal section of the layer of the frame memory 2 in the course of the display line, the starting address (the setting value of the re-start address register 8) on the frame memory 2 of the present line having been latched to the re-start address latch 11 by the output of a comparator 13 is loaded on the address counter 1 to make a count-up operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a raster scan type image display device.

[0002]

2. Description of the Related Art As such an image display device, image data (image information such as characters and patterns) in a frame memory of a parallel data input / output system is sequentially read out and is read by a CRT.
There is a graphic display device for displaying on a screen such as (cathode ray tube) or LCD (liquid crystal device).

Such an image display device is equipped with, for example, an LCD controller (display control means) as shown in FIG. 8 and performs the following operation. First, an external CPU (central processing unit) (not shown) stores the frame memory 2 in the display start address register 3 of the LCD controller.
The upper display start address (start address) is written in a horizontal display screen width register (not shown) for the number of characters displayed horizontally on the LCD screen (horizontal display screen width), and the horizontal virtual screen width register 4 is written in the horizontal direction in the frame memory 2. Set the number of characters (horizontal virtual screen width) respectively.

The address set in the display start address register 3 (or a value obtained by performing some kind of operation on the value) before entering the frame display period (the non-display period after the last display of the last line) Is loaded into the address counter 1 via the switch 6 and the line start address latch 7, and the address counter 1 counts up as the image data (display data) is transferred from the frame memory 2 to the LCD screen.

After the transfer of the image data for one line, the horizontal virtual screen width register 4 is set at the first address of the next line (second line), that is, the first address of the previous line. An address obtained by adding a value (or a value obtained by performing some kind of operation on the value) by the adder 5 is the switch 6 and the line start address latch 7
Is loaded into the address counter 1 via, and the same operation as described above is repeated thereafter.

If the horizontal virtual screen width of the frame memory 2 is "16" as shown in FIG. 2 and the addresses of the image data displayed on the LCD screen are arranged as shown in FIG. 3, the display start address register "3" is set to 3
“8” is set in the horizontal display screen width register, and “16” is set in the horizontal virtual screen width register 4.

By the way, when the image data displayed on the LCD screen is scrolled in the horizontal direction (horizontal direction),
The start address is incremented (or decremented) at an appropriate time, but if the start address is incremented from the display of FIG. 3, there is a problem that the following problems occur.

That is, when the image data before and after the end portion (boundary line) of the layer on the frame memory determined by the horizontal virtual screen width is displayed on the LCD screen, the address counter 1 counts up during the display period. On the right side of the end portion, image data after the start address (see FIG. 2) of the next line on the frame memory is displayed.
As shown in FIG. 9, the image data on the right side is shifted upward by one line (1 character in the case of character display) from the image data on the left side of the end portion.

Therefore, as disclosed in Japanese Laid-Open Patent Publication No. 3-51895, there is proposed a frame memory (image memory) in which a horizontal address counter and a vertical address counter are separately fixed. According to this, even if the start address is set at a position that crosses the boundary line of the frame memory, the vertical address counter does not increment in the middle of the horizontal line, so that it is possible to perform display without a step.

However, although such a hardware configuration is preferable on the assumption of a specific screen size or frame memory size, it is a general-purpose CRT controller or LCD controller applicable to various screen sizes or frame memory sizes. It becomes poor in nature. Therefore, in general, when scrolling in the horizontal direction, it is necessary to take measures as shown in (1) to (3) below.

(1) The screen is developed so that the boundary line is not displayed on the screen. (2) The image data on the right side of the boundary line is previously shifted upward by one line (one character in the case of character display). (3) A horizontal address counter and a vertical address counter are provided separately at the expense of hardware versatility.

[0012]

However, when attempting to expand the screen by making extensive use of horizontal scrolling, the scroll amount is limited by the frame memory size in (1). If you rewrite a lot of software, the load on the software will increase and the performance will decrease. In other words, the display is visually difficult to call a smooth scroll. In (2), the degree of freedom is improved compared to (1), but the burden of software increases and performance declines. Although (3) may be based on the assumption of a specific screen size or frame memory size, it is poor in versatility.

The present invention has been made in view of the above points, and even when image data before and after the boundary line of the frame memory determined by the horizontal virtual screen width is displayed on the screen, a step is generated at the boundary line. It is an object of the present invention to smoothly perform horizontal scroll display without causing a problem and to cope with a certain screen size and frame memory size.

[0014]

In order to achieve the above object, the present invention provides a raster scan type image display device, wherein when a display address exceeds a maximum value of a line being displayed during a display period, The display control means is provided for making the display address jump to the minimum value of the displayed line. In this case, the display control means may be provided with means for calculating the minimum value of each line.

In the image display device according to the present invention, when the display address exceeds the maximum value of the line being displayed (the maximum value of the horizontal virtual screen width) during the display period, the display control means
Since the display address is jumped to the minimum value of the displayed line, even if the image data before and after the border line of the frame memory determined by the horizontal virtual screen width is displayed on the screen, there is a step at the border line. Since it does not occur, the horizontal scroll display can be smoothly performed, and it can be applied to all screen sizes and frame memory sizes.

Furthermore, if the display control means can calculate the minimum value of each line, the load on the external (CPU) side when performing vertical scroll display or the like is reduced, and the processing of the entire image display apparatus is reduced. Increases efficiency.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of an LCD controller (display control means) of an image display device according to an embodiment of the present invention, and the portions corresponding to those in FIG.

This LCD controller has an address counter 1 for counting up by a clock signal (not shown) and outputting each display address to the frame memory 2, and a frame memory 2 for storing image data to be displayed on an LCD screen (not shown). A display start address register 3 for setting a start address (display start address), and a horizontal virtual screen width register 4 for setting a horizontal virtual screen width of the frame memory 2.

Further, the adder 5 which adds the value set in the horizontal virtual screen width register 4 to the output value of the line start address latch 7 (start address of the previous line) and outputs the start address of the next line And a switch 6 for switching and outputting to either the value set in the display start address register 3 or the output value of the adder 5, and the output value (line start address) of the switch 6 is latched and output. A line start address latch 7 is provided.

Further, the value set in the horizontal virtual screen width register 4 is added to the output value of the restart address register 8 for setting the restart address and the restart address latch 11, and the frame memory 2 for the next line is added. An adder 9 that outputs the top address above; a switch 10 that switches and outputs either the value set in the restart address register 8 or the output value of the adder 9;
A restart address latch 11 that latches and outputs the output value (restart address) of the switch 10 is provided.

Further, a switch 12 for switching and outputting to either the output value of the line start address latch 7 or the output value of the restart address latch 11;
The output value of the address counter 1 and the output value of the adder 9 are compared with each other, and when they match each other, the comparator 13 which sets the output signal to a low level (outputs a load pulse), and the input horizontal synchronizing signal, It is provided with a negative logic OR gate 14 which sets the load signal to the address counter 1 to "0" when any of the output signals of the comparator 13 is "0".

Next, the operation of the LCD controller of the image display device thus configured will be described. First, an external CPU (central processing unit) (not shown) stores a display start address (start address) in the frame memory 2 in the display start address register 3 of the LCD controller.
, The start address (restart address) on the frame memory 2 of the line having the start address in the restart address register 8, the horizontal display screen width of the LCD screen in the horizontal display screen width register (not shown), and the horizontal virtual screen width. The horizontal virtual screen width of the frame memory 2 is set in the register 4, respectively.

For example, when the horizontal virtual screen width of the frame memory 2 is set to "16" as shown in FIG. 2 and the address of the image data displayed on the LCD screen for scroll display is arranged as shown in FIG. The display start address register 3 is "12", the restart address register 8 is "0", and the horizontal display screen width register is "8".
And "16" are set in the horizontal virtual screen width register 4, respectively.

Then, "12" set in the display start address register 3 before the start of the frame display period (the non-display period after the last display of the last line) is the switch 6, the line start address latch 7, and Switch 12
Is loaded into the address counter 1 via, and the address counter 1 counts up with the transfer of the image data from the frame memory 2 to the LCD screen.

That is, the address counter 1 outputs the loaded display address "12" and then counts up by a clock signal (not shown) to obtain its count value (each display address "13", "14" ... hereafter). The image data of the respective addresses among the image data written in the frame memory 2 are sequentially output and are sequentially output.
Display it on the D screen.

The frame memory 2 in which the count value (output value) of the address counter 1 is determined by the horizontal virtual screen width
When it exceeds the end portion (boundary line) of the upper layer, the count value becomes "16". The output value of the adder 9 is the value “0” set in the restart address register 8 and the value “16” set in the horizontal virtual screen width register 4.
Therefore, the inputs of the comparator 13 coincide with each other, and a load pulse (low level signal) is output from the input.

At this time, the restart address latch 11
Latches the first restart address “0” input from the restart address register 8 via the switch 10, and the load pulse output from the comparator 13 causes the address counter 1 to be transferred to the address counter 1 via the switch 12. Load "0". Therefore, on the LCD screen, as shown in FIG. 4, the image data at the address "15" is followed by the address "0".
Image data of is displayed.

After that, when the address counter 1 performs a count-up operation to transfer the image data for one line to the LCD screen, the first address of the next line (second line), that is, the line start address latch 7 is set. First address "12" of the previous line that is latched
The value set in the horizontal virtual screen width register 4 is "1.
The address "28" obtained by adding "6" by the adder 5 is loaded into the address counter 1 through the switch 6, the line start address latch 7 and the switch 12, and the image data of the next line is displayed. To start.

Further, when the display of the image data of the next line is started, the restart address latch 11 inputs the start address "" on the frame memory 2 of the next line input from the adder 9 through the switch 10. 16 ", that is, the horizontal virtual screen width register 4 at the first restart address" 0 "
The address "16" obtained by adding the value "16" set to is latched. Thereafter, by repeating the same operation as described above, the image data of the address arrangement shown in FIG. 4 is displayed on the LCD screen. FIG. 5 is a timing chart showing an operation example of this LCD controller.

As described above, according to the LCD controller of this embodiment, when the display address exceeds the maximum value (for example, "15") of the line being displayed during the display period, the display address is displayed. The image data before and after the boundary line of the frame memory 2 determined by the horizontal virtual screen width is displayed on the LCD because the jump is made to the minimum value of the line (for example, "0").
Even when it is displayed on the screen, a step does not occur at the boundary line, horizontal scroll display can be smoothly performed, and it can be applied to all screen sizes and frame memory sizes.

According to this LCD controller,
By changing the start address set in the display start address register 3 to the address of another line and the restart address set in the restart address register 8 to the start address of the line, the vertical direction is changed. You can also scroll the display of.

FIG. 6 is a block diagram showing a configuration example of an LCD controller of an image display apparatus according to another embodiment of the present invention, and the portions corresponding to those in FIG. 1 are designated by the same reference numerals.

Similar to the above-described embodiment, this LCD controller should display on an LCD screen (not shown) and an address counter 1 that counts up by a clock signal (not shown) and outputs each display address to the frame memory 2. Frame memory 2 for storing image data
And a display start address register 3 for setting a start address (display start address), and a frame memory 2
Horizontal virtual screen width register 4 to set the horizontal virtual screen width of
And

Further, the adder 5 which adds the value set in the horizontal virtual screen width register 4 to the output value of the line start address latch 7 (start address of the previous line) and outputs the start address of the next line And a switch 6 for switching and outputting to either the value set in the display start address register 3 or the output value of the adder 5, and the output value (line start address) of the switch 6 is latched and output. A line start address latch 7 is provided.

Further, the subtracter 21 for subtracting the value set in the horizontal virtual screen width register 4 from the output value of the address counter 1 to output the minimum value of the display address during the display period, and the line start address latch 7 2 and the subtracter 21 output value, and an origin address register 22 for setting the address of the origin of the frame memory 2.

Furthermore, a value obtained by adding an integer multiple of the value set in the horizontal virtual screen width register 4 to the value set in the origin address register 22 and the output value of the address counter 1 are compared, and both match. Sometimes, the output signal of the comparator 23 that sets the output signal to a low level (outputs a load pulse) and the load to the address counter 1 when either the input horizontal synchronizing signal or the output signal of the comparator 23 is "0" And a negative logic OR gate 14 for setting the signal to "0".

Next, the operation of the LCD controller of the image display device thus configured will be described. First, the external CPU stores the origin address of the frame memory 2 in the origin address register 22 of the LCD controller, the display start address (start address) in the frame memory 2 in the display start address register 3, and the horizontal display screen width register (not shown). The horizontal display screen width of the LCD screen,
The horizontal virtual screen width of the frame memory 2 is set in the horizontal virtual screen width register 4, respectively.

For example, when the horizontal virtual screen width of the frame memory 2 is "16" as shown in FIG. 2 and the addresses of the image data displayed on the LCD screen are in the array shown in FIG. 4, the origin address register 22 is set to “0”, the horizontal display screen width register is set to “8”, the horizontal virtual screen width register 4 is set to “16”, and the display start address register 3 is set to “12”.

Then, "12" set in the display start address register 3 before the start of the frame display period (non-display period after the last display of the last line) is the switch 6, the line start address latch 7, and Switch 12
Is loaded into the address counter 1 via, and the address counter 1 counts up with the transfer of the image data from the frame memory 2 to the LCD screen.

That is, the address counter 1 outputs the loaded display address "12" and then counts up by a clock signal (not shown) to obtain its count value (each display address "13""14" ... The image data of the respective addresses among the image data written in the frame memory 2 are sequentially output and are sequentially output.
Display it on the D screen.

When the count value of the address counter 1 exceeds the end portion (boundary line) of the layer on the frame memory 2 determined by the horizontal virtual screen width, the count value becomes "1".
6 ”. In addition, this value is the origin address register 22.
"0" and the horizontal virtual screen width register 4 set in
An integer multiple of the value "16" set in (16, 32, 4
8, ...) And the inputs of the comparator 23 match, and a load pulse (low level signal) is output from there.

At this time, the subtracter 21 calculates the horizontal virtual screen width register 4 from the count value "16" of the address counter 1.
The value "0" obtained by subtracting the setting value "16" of
The switch 1 is operated by the load pulse output from the comparator 23.
The address counter 1 is loaded with “0” via 2.
That is, the restart address (minimum value) of the same line as the start address is calculated. Therefore,
As shown in FIG. 4, the image data of the address "0" is displayed next to the image data of the address "15" on the LCD screen.

After that, when the address counter 1 performs a count-up operation to transfer the image data for one line to the LCD screen, the first address of the next line (second line), that is, the line start address latch 7 is set. First address "12" of the previous line that is latched
The value set in the horizontal virtual screen width register 4 is "1.
The address "28" obtained by adding "6" by the adder 5 is loaded into the address counter 1 through the switch 6, the line start address latch 7 and the switch 12, and the image data of the next line is displayed. To start.

Thereafter, by repeating the same operation as described above, the image data of the address arrangement shown in FIG. 4 is displayed on the LCD screen. FIG. 7 is a timing chart showing an operation example of this LCD controller. Here, in order to perform the scroll display in the vertical direction, the CPU sets the start address set in the display start address register 3 to the address of another line (here, "4 in FIG. 4").
4 ”), the following operation is performed.

That is, "4" set in the display start address register 3 before entering the frame display period.
4 ”is loaded into the address counter 1 through the switch 6, the line start address latch 7, and the switch 12, and after the address counter 1 outputs“ 44 ”,
The count value is incremented by a clock signal (not shown) and the count value (each subsequent display address “45” “46” ...
...) is sequentially output, and the image data of each address among the image data written in the frame memory 2 is sequentially output and displayed on the LCD screen.

When the count value of the address counter 1 exceeds the end portion (boundary line) of the layer on the frame memory 2 determined by the horizontal virtual screen width, the count value becomes "4".
8 ”. In addition, this value is the origin address register 22.
"0" and the horizontal virtual screen width register 4 set in
An integer multiple of the value "16" set in (16, 32, 4
8, ...) And the inputs of the comparator 23 match, and a load pulse (low level signal) is output from there.

At this time, the subtractor 21 calculates the horizontal virtual screen width register 4 from the count value "48" of the address counter 1.
The value "32" obtained by subtracting the set value "16" of the above is output, and "32" is loaded into the address counter 1 via the switch 12 by the load pulse output from the comparator 23. That is, the restart address of the same line as the start address after the setting change is calculated. Therefore, the address "4" is displayed on the LCD screen as shown in FIG.
The image data of the address "32" is displayed next to the image data of "7". After that, the same operation as described above is repeated.

As described above, according to the LCD controller of this embodiment, when the display address exceeds the maximum value of the line being displayed during the display period, the display address is displayed as in the above-described embodiments. Since the line is jumped to the minimum value of the line, even when the image data before and after the boundary line of the frame memory 2 determined by the horizontal virtual screen width is displayed on the LCD screen, a step does not occur at the boundary line. The horizontal scroll display can be smoothly performed, and it can be applied to any screen size and frame memory size.

According to this LCD controller,
By changing the start address set in the display start address register 3 to the address of another line, vertical scroll display can be performed. In other words, when performing vertical scroll display,
Since it is only necessary to change the setting of the start address, the load on the external side is reduced, and the processing efficiency of the entire image display device is improved.

Although the embodiment in which the present invention is applied to the LCD controller of the image display device has been described above, the present invention is not limited to this and can be applied to other controllers such as a CRT controller.

[0051]

As described above, according to the present invention, even when the image data before and after the boundary line of the horizontal virtual screen width of the frame memory is displayed on the screen, there is no step at the boundary line. , The horizontal scroll display can be performed smoothly. For example, when it is desired to repeatedly display horizontally written messages without gaps, or to virtually enlarge the size of the horizontal virtual screen width (the portions that are not displayed in the frame memory are sequentially rewritten), they can be displayed without any discomfort. Further, the present invention can be applied to all screen sizes and frame memory sizes.

[Brief description of drawings]

FIG. 1 is an image display device L according to an embodiment of the present invention.
It is a block diagram which shows the structural example of a CD controller.

FIG. 2 is an explanatory diagram showing an example of an address array of image data on the frame memory shown in FIG.

FIG. 3 is an explanatory diagram showing an example of an address array of a part of image data on a frame memory displayed on the LCD screen by the LCD controller.

FIG. 4 is an explanatory diagram showing another example of the address arrangement of a part of the image data on the frame memory displayed on the LCD screen by the LCD controller.

FIG. 5 is a timing chart showing an operation example of the LCD controller.

FIG. 6 is a block diagram showing a configuration example of an LCD controller of an image display device according to another embodiment of the present invention.

7 is a timing chart showing an operation example of the LCD controller shown in FIG.

FIG. 8 is a block diagram showing a configuration example of an LCD controller of a conventional image display device.

FIG. 9 is a diagram showing an LC of the LCD controller shown in FIG.
It is explanatory drawing which shows an example of the address arrangement | sequence of some image data on the frame memory displayed on D screen.

[Explanation of symbols]

 1: Address counter 2: Frame memory 3: Display start address register 4: Horizontal virtual screen width register 5, 9: Adder 6, 10, 12: Switching device 7: Line start address latch 8: Restart address register 11: Re Start address latch 13, 23: Comparator 14: Negative logic OR gate 21: Subtractor 22: Origin address register

Claims (2)

[Claims] 1. A display for jumping to the minimum value of the line that has been displayed when the display address exceeds the maximum value of the line being displayed during the display period in a raster scan type image display device. An image display device comprising a control means. 2. The image display device, wherein the display control means has means for calculating a minimum value of each line.