JPH0955726A - Integrated circuit and transmitter/receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of external terminal pins of the integrated circuit composed of a PLL and a demodulating circuit which demodulates received data. SOLUTION: A lock detecting circuit 85 which detects the PLL 31 being locked and a frame detecting circuit 84 which detects the frame signal of the received data are provided. A switching circuit 90 is provided which is supplied with the lock detection signal LKD of the lock detecting circuit 85 and the frame detection signal FRMD of the frame detecting circuit 84. The switching circuit 90 is controlled with an external control signal MDPL to selectively lead out the lock detection signal LKD and frame detection signal FRMD.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit and a transceiver using the same.

[0002]

2. Description of the Related Art For example, a frequency band for 89 channels is assigned to a small power cordless telephone in Japan, and the relationship between the channel number CHNO and the transmission frequencies of the master unit and the slave unit is as follows. This is as shown in FIG. At this time, the frequency intervals between the channels are all constant at 12.5 kHz.

A transmission signal having such a frequency is generally P
Although it can be formed by LL, when the transmission channel is set in the master unit or the slave unit, the microcomputer forms the data of the division ratio corresponding to the channel number CHNO, and this data is changed by the PLL. Just set it in the frequency divider. Also, when setting the receiving channel in the receiving circuit of the master unit or the slave unit,
Data having a frequency division ratio corresponding to the channel number CHNO may be formed, and this data may be set in the variable frequency dividing circuit of the PLL that determines the local oscillation frequency.

On the other hand, in a cordless telephone, for example, when a slave unit requests a connection between the two units to make a call, when a call is received, the master unit requests a connection between the two units by an incoming call. In this case, command signals indicating the request and parameters are transmitted and received between the master unit and the slave unit.

FIG. 10 shows an example of the signal format of the command signal CMND. This signal CMND has a 16-bit bit synchronization signal BSYN at the beginning, and subsequently has a 16-bit frame synchronization signal FSYN. In this case, the sync signal BSY
N and FSYN each have a predetermined bit pattern, but the frame synchronization signal FSYN transmitted from the slave unit to the master unit.
And the frame synchronization signal FSYN transmitted from the master unit to the slave unit have different bit patterns.

Further, the command signal CMND has a system identification code SYID of 25 bits following the signal FSYN, an error correction code ECC of 12 bits for this code SYID, and a control code CTRL of 5 bytes. In this case, the system identification code SYID is data for distinguishing the own device from other devices. The first byte of the control code CTRL is a code indicating the control content of the slave unit and the master unit, and the second to fifth bytes are parameters or data related to the first byte.

When the child device or the parent device receives this command signal CMND, the command signal CMND
It is checked whether the identification code SYID included in the identification code SYID matches the identification code SYID stored in its own machine. Only when they match, the command signal CMND is validated, and when they do not match, the command signal CMND is invalidated.

When the command signal CMND is transmitted and received between the master unit and the slave unit, the command signal CMND is M
It is transmitted / received in a state of being converted into an SK signal (modified MSK signal). This MSK signal is, for example, one cycle of a sine wave signal with a frequency of 2.4 kHz when the bit of the command signal CMND is "0", and a half cycle of a sine wave signal with a frequency of 1.2 kHz when it is "1". It

[0009]

By the way, when the data of the frequency division ratio as described above is formed in the microcomputer and supplied to the variable frequency divider circuit of the PLL, the 3-wire serial is used because of its usefulness and simplicity. Transfer (serial communication) is often used. That is, the data of the division ratio is serially transferred by the serial clock and the chip enable signal (data latch signal).

Therefore, in this case, three signal lines are required for (A) data of the division ratio (B) serial clock (C) chip enable signal.

In the case of converting the command signal CMND into the MSK signal, the microcomputer can form the command signal CMND and serially transfer the command signal CMND to the conversion circuit to convert the command signal CMND into the MSK signal. Also in this case, three signal lines are required for the (D) command signal CMND (E) serial clock (F) chip enable signal.

Therefore, if the PLL and the conversion circuit for the MSK signal are provided in one IC (integrated circuit), the number of signal lines increases, and the number of external terminals (external terminal pins) of the IC also increases. I will end up. Further, in order to supply the above signals from the microcomputer, it is necessary for the microcomputer to have output ports for outputting the respective signals.

Further, the frequency-division-ratio data is formed in a microcomputer, and a PLL for transmission or reception is formed.
When it is set in the variable frequency dividing circuit of No. 3, it takes a little time until the PLL enters the steady state, that is, until the frequency is locked. Therefore, when the master unit and the slave unit are connected via a channel, or when the channel is changed, it is necessary to detect that the frequency of the PLL is locked before executing the next process.

When the command signal CMND is received, it must be notified to the microcomputer, that is, the frame detection signal must be output to the microcomputer.

Therefore, when the PLL and the demodulation circuit for demodulating the command signal CMND from the MSK signal are provided in one IC, the IC includes (G) PLL frequency lock detection signal (H) received data. (Command signal CMND) (I) Frame detection signal (J) An external pin is required to output the clock that indicates the bit timing (bit synchronization) of the received data.

Further, these output signals are taken in by the microcomputer, which requires an input port for taking in each of these signals.

However, increasing the number of external terminals of the IC is not preferable from the viewpoint of the cost and function of the IC.
Further, since the number of input ports and output ports of the microcomputer is limited, it is not preferable that a large number of ports are required.

[0018]

In the present invention, P
In an integrated circuit in which an LL and a demodulation circuit that demodulates received data are integrated together, a lock detection circuit that detects that the PLL is locked, and a frame detection circuit that detects a frame signal of the received data. And a lock detection signal from the lock detection circuit and a switching circuit to which the frame detection signal from the frame detection circuit is supplied. The switching circuit is controlled by an external control signal to control the lock detection signal. The frame detection signal and the integrated circuit are selectively taken out to the outside.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Now, in a cordless telephone,
Considering the relationship between the PLL and the command signal CMND, the command signal CMND is formed when a request or data is accessed between the child device and the parent device, and the MSK signal of the command signal CMND is transmitted and received. .

Therefore, the command signal CMND is not formed when the channel between the slave unit and the master unit is not fixed. Alternatively, it need not be formed. In principle, it is impossible even if the command signal CMND is transmitted or received while switching the channel between the slave unit and the master unit. That is, the formation or transmission / reception of the command signal CMND and the channel switching do not temporally overlap.

In the cordless telephone, the P
Considering the relationship between LL and the received (received) command signal CMND, it becomes possible to receive the command signal CMND when the receiving PLL is locked to the frequency of the target channel. However, the command signal CMND cannot be received during the period in which the receiving PLL is trying to lock to the frequency of the target channel.

Also, the microcomputer does not simultaneously check whether the frequency of the PLL is locked and receive the command signal CMND. That is,
The microcomputer checks whether or not the PLL is locked, and if locked, then receives the command signal CMND.

In the present invention, attention is paid to the above points so that the number of external terminals of the IC can be reduced.

[Example of Cordless Telephone] First, an example of the receiving circuit and the transmitting circuit of the cordless telephone according to the present invention will be described with reference to FIGS. 1 and 2. In this example, the whole of the receiving circuit and the transmitting circuit is constructed so as to be integrated into a single-chip IC, and the IC is used as a slave unit. In addition, * 1, * 2 in Figure 1 and Figure 2
* 1 and * 2 are connected, and part 1 surrounded by the chain line is 1
Chip IC is made.

This IC 1 has a receiving circuit 10 and a transmitting circuit 40. The receiving circuit 10 is of the double superheterodyne type and is of direct conversion type. That is, the FM signal Sr of the downlink channel from the base unit is received by the antenna 2, and is orthogonal through the signal line of the terminal T11 → high frequency amplifier 11 → terminal T12 → bandpass filter 3 having all the downlink channels as pass bands → terminal T13. It is supplied to the first mixer circuits 12 and 22 for the I axis and the Q axis for conversion.

An oscillator circuit 30 is also provided. This oscillator circuit 30 has a stable reference frequency, for example, 14.4M.
It is for forming the oscillation signal S30 of Hz. Therefore, the oscillation circuit 30 has the crystal oscillator 6 through the terminal T16.
Are connected to form a crystal oscillation circuit.

Then, the oscillation signal S30 is used as the frequency dividing circuit 35.
Is divided into a signal S35 having a frequency of 1/1152, that is, a channel interval frequency of 12.5 kHz, and this signal S35 is supplied to the PLL 31 as a signal of its reference frequency.

Since this PLL 31 can be constructed in the same manner as a general PLL, its details are omitted, but V
It has a CO311 and a variable frequency divider 312,
From 11, an oscillation signal S31 having a frequency equal to the carrier frequency of the FM signal Sr is extracted. In this case,
Since the carrier frequency of the received FM signal Sr is equal to the transmission frequency of the master unit, the frequency of the oscillation signal S31 is also equal to the transmission frequency of the master unit.

The signal S31 is supplied to the mixer circuit 12 as the first local oscillation signal and is also supplied to the phase shift circuit 32 to be phase-shifted by π / 2.
32 is supplied to the mixer circuit 22 as the first local oscillation signal.

Therefore, for simplification, as shown in FIG. 3A, the received signal Sr has a signal component Sa in the band of its lower sideband and a signal component Sb in the band of its upper sideband, and ωo: Carrier frequency (angular frequency) of received signal Sr ωa: Angular frequency of signal component Sa ωa <ωo Ea: Amplitude of signal component Sa ωb: Angular frequency of signal component Sb ωb> ωo Eb: If the amplitude of the signal component Sb is Δωa = ωo−ωa Δωb = ωb−ωo, then Sr = Sa + Sb Sa = Ea · sinωat Sb = Eb · sinωbt.

Further, if E1 is the amplitude of the first local oscillation signals S31 and S32, then S31 = E1.sin.omega.ot S32 = E1.cos.omega.ot.

Therefore, S12, S22: S12 = Sr.S31 = (Ea.sin.omega.at + Eb.sin.omega.bt) .times.E1.sin.omega.ot = αa {-cos (ωa + ωo) t + cos (ωo- ωa) t} + αb {−cos (ωb + ωo) t + cos (ωb−ωo) t} = αa {−cos (ωa + ωo) t + cosΔωat} + αb {−cos (ωb + ωo) t + cosΔωbt} S22 = Sr · S32 = (Ea · sinωat + Eb · sinωa + at ) × E1 · cosωot = αa {sin (ωa + ωo) t−sin (ωo−ωa) t} + αb {sin (ωb + ωo) t + sin (ωb−ωo) t} = αa {sin (ωa + ωo) t−sinΔωat} + αb {sin (Ωb + ωo) t + sinΔωbt} αa = Ea · E1 / 2/2 αb = Eb · E1 / 2

Then, in the above equation, the angular frequencies Δωa, Δ
Since the signal component of ωb is the required intermediate frequency signal, these signals S12 and S22 are supplied to the low pass filters 13 and 23, and the signal components of the angular frequencies Δωa and Δωb are extracted as the first intermediate frequency signals S13 and S23, and S13 = Αa · cos Δωat + αb · cos Δωbt S23 = −αa · sin Δωat + αb · sin Δωbt In this case, as is clear from the above equation and FIG. 3A, the signals S13 and S23 are baseband signals.

Further, these signals S13 and S23 are supplied to the second mixer circuits 14 and 24 for the I axis and the Q axis of the orthogonal transformation.

Further, the oscillation signal S30 of the oscillation circuit 30 is supplied to the frequency dividing circuit 33 and is a signal S33 having a frequency of several times the highest audible frequency, for example, 262 frequency-divided to have a frequency of about 55 kHz.
It is divided into the signal S33 of z. Then, the signal S33 is supplied to the mixer circuit 14 as the second local oscillation signal and is also supplied to the phase shift circuit 34 to be phase shifted by π / 2.
The phase shift signal S34 is supplied to the mixer circuit 24 as the second local oscillation signal.

Therefore, S33 = E2sinωst S34 = E2cosωst E2: The amplitude of the second local oscillation signals S33 and S34 is set to ωs = 2πfs (fs = about 55 kHz), and S14 and S24: of the mixer circuits 14 and 24. As an output signal, S14 = S13 · S33 = (αa · cosΔωat + αb · cosΔωbt) × E2 · sinωst = βa {sin (Δωa + ωs) t−sin (Δωa−ωs) t} + βb {sin (Δωb + ωs) t-sin ( Δωb−ωs) t} S24 = S23 · S34 = (− αa · sin Δωat + αb · sin Δωbt) × E2 · cosωst = −βa {sin (Δωa + ωs) t + sin (Δωa−ωs) t} + βb {sin (Δωb + ωs) t + sin (Δωb) ωs) t} βa = αa · E2 / 2 βb = αb · E2 / 2.

Then, in these signals S14 and S24, signals S14 and S24 are set so that the frequency difference does not become a negative value.
When transforming 24, S14 = βa {sin (Δωa + ωs) t + sin (ωs−Δωa) t} + βb {sin (Δωb + ωs) t + sin (ωs−Δωb) t} = βa · sin (ωs + Δωa) t + βa · sin (ωs−Δωa) t + βb · sin (ωs + Δωb) t + βb · sin (ωs−Δωb) t S24 = −βa {sin (Δωa + ωs) t−sin (ωs−Δωa) t} + βb {sin (Δωb + ωs) t−sin (ωs−Δωb) t } = − Βa · sin (ωs + Δωa) t + βa · sin (ωs−Δωa) t + βb · sin (ωs + Δωb) t−βb · sin (ωs−Δωb) t.

Then, these signals S14 and S24 are supplied to the addition circuit 15 and added, and from the addition circuit 15, the addition represented by S15 = S14 + S24 = 2βa · sin (ωs−Δωa) t + 2βb · sin (ωs + Δωb) t The signal S15 is taken out.

The addition signal S15 is illustrated as follows.
As shown in FIG. 3B, this signal S15 is nothing but a signal obtained by frequency-converting the original received signal Sr into a signal having a carrier frequency (angular frequency) ωs. That is, the signal S15 is the second intermediate frequency signal having the intermediate frequency fs.

The second intermediate frequency signal S15 is supplied to the FM demodulation circuit 18 through the bandpass filter 16 for the intermediate frequency filter and the limiter amplifier 17 to demodulate the original audio signal, and this audio signal is Amplifier 1
It is supplied to the speaker 4 for the receiver through 9 and the terminal T14. The above is the configuration and operation of the receiving circuit 10 relating to the audio signal.

On the other hand, the transmitting circuit 40 directly converts the voice signal into the FM signal of the upstream channel, and the PLL
43 is provided, and the frequency dividing signal S35 from the frequency dividing circuit 35 is supplied to the PLL 43 as a signal of the reference frequency. In this way, the VCO 431 of the PLL 43 extracts the signal St of the carrier frequency of the upstream channel paired with the downstream channel received by the receiving circuit 10.

The voice signal from the microphone 5 for the transmitter is supplied to the low-pass filter 42 through the terminal T15 and the amplifier 41 to remove the unnecessary band component, and the voice signal from which the unnecessary component is removed will be described later. Is supplied as a control signal of the oscillation frequency to the VCO 431 of the PLL 43 through the switch circuit path 55.

Thus, the VCO 431 takes out the FM signal St which is an upstream channel paired with the downstream channel received by the receiving circuit 10 and which is FM-modulated by the audio signal from the low-pass filter 42.

The FM signal St is taken out to the terminal T17 through the drive amplifier 44 and the output amplifier 45, supplied to the antenna 2 and transmitted to the master unit.
The above is the configuration and operation of the audio signal of the transmission circuit 40.

In the above description, the case where the IC1 is used for the slave unit is used, but the terminals T14 and T15 are 4 lines / 2 of the master unit.
By connecting to the line conversion circuit and switching the frequency division ratios of the variable frequency dividing circuits 312 and 432 of the PLLs 31 and 43, the above operation is performed in the parent device. And at this time,
The receiving circuit 10 receives the uplink channel, and the transmitting circuit 20 transmits the downlink channel.

Therefore, this IC1 can also be used in the master unit. That is, this IC1 can be commonly used by the child device and the parent device.

Further, in the case of a general FM receiver, the intermediate frequency is set to 10.7 MHz, so that the intermediate frequency filter is composed of a ceramic filter and cannot be integrated into an IC.

However, in the receiving circuit 10 described above,
Since the first intermediate frequency signals S12 and S22 are in the base band and the second intermediate frequency fs is as low as 55 kHz, the filters 13, 23 and 16 can be configured by active filters having resistors, capacitors and amplifiers. . Therefore, the receiving circuit 10 includes the filter 3 and the V
It can be integrated into an IC except for the oscillation coil (not shown) of CO311. The same applies to the transmission circuit 40, which can be integrated into an IC.

Therefore, the receiving circuit 10 and the transmitting circuit 40 can be integrated into a single monolithic IC.

[Transfer of Data of Frequency Division Ratio and Transfer of Command Signal] (1) Case of Transfer of Data of Frequency Division Ratio of PLL PLLs 31 and 43 have variable frequency division circuits 312 and 432. Then, in the PLL 31, the oscillation signal S31 of the VCO 311 is supplied to the frequency dividing circuit 312, as in a general PLL.
The reference signal S35 is phase-compared with the frequency-divided signal, and the oscillation frequency of the VCO 311 is controlled by the comparison output. The same applies to the PLL 43.

Therefore, f31: frequency of signal S31 f31 = ωo / (2π) f43: carrier frequency (center frequency) of signal S43 N31: frequency division ratio of variable frequency dividing circuit 312 N43: frequency division of variable frequency dividing circuit 432. In terms of the ratio, as in a general PLL, in the steady state, f31 = 12.5 [kHz] × N31 f43 = 12.5 [kHz] × N43 12.5 [kHz] is the reference frequency of the signal S35.

Therefore, if the frequency division ratios N31 and N43 are set corresponding to the channel number CHNO of the channel to be used, transmission / reception can be performed on the channel of the channel number CHNO.

Therefore, in order to set the frequency division ratios N31 and N43, for example, as shown in FIG. 4, the IC 1 is provided with a switching circuit 51 and a frequency division ratio setting circuit 52.

In this case, since the frequency division ratios N31 and N43 are set, the data DATA of the channel number CHNO and its clock TC are set in the microcomputer (not shown).
K and the enable signal ENBL are formed. in this case,
For example, as shown on the left side of FIG. 7, the signals DATA and TCK are serial signals, and the data DATA is the clock TCK.
It is formed in synchronization with. The signal ENBL is the data DATA
The signal is at the "0" level during the period.

Then, these signals DATA to ENBL are connected to the terminal T.
It is supplied to the switching circuit 51 through 22 to T24.

Further, in this case, since the frequency division ratios N31 and N43 are set, the control signal MDPL of, for example, "1" level is generated in the microcomputer, and this signal MDPL is generated.
Is supplied as a control signal to the switching circuit 51 through the terminal T21.

Thus, when the frequency division ratios N31 and N43 are set, the signals DATA, CK and EN supplied to the switching circuit 51 are supplied.
BL is supplied to the division ratio setting circuit 52.

Then, in the setting circuit 52, from the data DATA of the channel number CHNO, the corresponding frequency division ratios N31 and N are set.
43 data is formed, and the data of the division ratio N31 is PL
It is supplied to the variable frequency dividing circuit 312 of L31 and latched. Thus, from the VCO 311 of the PLL 31, the FM
An oscillation signal S31 having a frequency f31 equal to the carrier frequency of the signal Sr is taken out.

Further, the data of the division ratio N43 formed in the setting circuit 52 is converted into the variable division circuit 432 of the PLL 43.
To be latched. Thus, V of PLL 43
From the CO 431, the carrier frequency f of the upstream channel
The FM signal St of 43 is taken out.

(2) In the case of command signal transfer For transmitting the command signal CMND, for example, as shown in FIG. 4, the IC1 is provided with a conversion circuit (modulation circuit) 53 for converting the command signal CMND into a digital MSK signal. , D / A converter 54 is provided.

When the command signal CMND is transmitted,
In the microcomputer, for example, as shown on the right side of FIG. 7, the data DATA of the command signal CMND, its clock TCK and the enable signal ENBL are formed. Then, these signals DATA to ENBL are supplied to the switching circuit 51 through the terminals T22 to T24.

Further, in this case, since the command signal CMND is transmitted, the control signal MDPL of, for example, "0" level is formed in the microcomputer, and this signal MDPL is generated.
Is supplied as a control signal to the switching circuit 51 through the terminal T21.

Thus, in the case of transmitting the command signal CMND, the signals DATA, CK and EN supplied to the switching circuit 51 are supplied.
BL is supplied to the conversion circuit 53.

Then, in the conversion circuit 53, the data DATA of the command signal CMND is digitally M bit by bit.
Converted to SK signal and the digital MSK signal is D / A
It is supplied to the converter 54 and converted into an analog MSK signal, and this MSK signal is supplied to the switch circuit 55.

At this time, when the control signal S55, which will be described later, is supplied to the switch circuit 55 and the command signal CMND is transmitted, the switch circuit 55 is connected in a state opposite to that shown in the drawing. Therefore, the MSK signal from the D / A converter 54 is supplied as a modulation signal to the VCO 431 of the PLL 43 through the switch circuit 55.

In this way, the FM signal St which is FM-modulated by the MSK signal is taken out from the VCO 431, and this FM signal St is transmitted to the master unit.

(3) Specific Example of Switching Circuit FIG. 5 shows a specific example of the switching circuit 51. That is,
The signal MDPL is supplied to the AND circuit 61 and
ENBL is supplied to the AND circuit 61 through the inverter 62. Therefore, when MDPL = "1" (dividing ratio N31,
In the case of setting N43), the output Q61 of the AND circuit 61
Becomes "1" when ENBL = "0", and ENBL =
When it is "1", it becomes "0".

Since this signal Q61 is supplied to the inverter 63, MDPL = "1" is output from the inverter 63.
Only in this case, the signal ENBL is taken out. Therefore, the signal ENBL from the inverter 63 is supplied to the frequency division ratio setting circuit 52.

Further, the signals TCK and DATA are AND circuits 64,
65 and the signal Q61 is supplied to the AND circuit 6
4 and 65. Therefore, the AND circuit 64,
From 65, signals TCK, DATA only when MDPL = "1"
Will be taken out.

Therefore, the signals TCK and DATA from the AND circuits 64 and 65 are supplied to the setting circuit 52.

Thus, when MDPL = “1”, FIG.
The signals DATA, TCK, and ENBL are supplied to the setting circuit 52 as shown on the left side of FIG.

In this case, the signals DATA and TCK are AND circuits 7.
It is also supplied to 2, 73, but these AND circuits 7
Since the signal MDPL is supplied to the inverters 2 and 73 through the inverter 71, when MDPL = "1", the signals DATA and TCK are not output from the AND circuits 72 and 73 and are not supplied to the conversion circuit 53.

Further, the signal ENBL is supplied to the exclusive OR circuit 74 and the AND circuit 73, but since the signal MDPL is also supplied to the exclusive OR circuit 74 and the AND circuit 75, ENBL = "1". If,
The output Q75 of the AND circuit 75 becomes "1", and this signal Q
75 (= “1”) is supplied as a signal ENBL to the conversion circuit 53 through the OR circuit 76.

If ENBL = "0", the output Q74 of the exclusive OR circuit 74 becomes "1", and this signal Q74 (= "1") is transmitted through the OR circuit 76 to the conversion circuit 5
3 is supplied as signal ENBL.

Therefore, when MDPL = “1”, the signals DATA and TCK are not supplied to the conversion circuit 53, and the signal ENBL supplied to the conversion circuit 53 is always “1”.
It is.

On the other hand, when MDPL = "0" (in the case of forming the MSK signal), the output Q61 of the AND circuit 61 is the signal
Regardless of ENBL, Q61 = “0”, and this signal Q61 is supplied to the inverter 63. Therefore, the signal ENBL from the inverter 63 becomes “1”, and this signal ENBL becomes the setting circuit 5.
2 is supplied. Also, because Q61 = "0", signal TC
K and DATA are blocked by the AND circuits 64 and 65 and are not supplied to the setting circuit 52.

Thus, when MDPL = “0”, the signal
DATA, TCK, and ENBL are not supplied to the setting circuit 52.

However, in this case, since MDPL = "1",
The signals DATA and TCK are supplied to the conversion circuit 53 through AND circuits 72 and 73. If ENBL = "1",
Q74 = "1", and this signal Q74 (= "1") is supplied to the conversion circuit 53 as the signal ENBL through the OR circuit 76.

If ENBL = "0", Q74 =
When it becomes "0", Q75 becomes "0", and these signals Q74 and Q75 are supplied to the conversion circuit 53 through the OR circuit 76 as the signal ENBL.

Therefore, when MDPL = “0”, the signals DATA, TCK and ENBL are supplied to the conversion circuit 53.

As is clear from FIG. 7, the output signal of the OR circuit 76 becomes "0" only during the period when the data DATA is being supplied to the conversion circuit 53. Therefore, this output signal is changed to the switch circuit 55. Can be used as the control signal S55.

Thus, according to the switching circuit 51, the signals DATA, TCK and ENBL are changed according to the signal MDPL.
It can be selectively supplied to the division ratio setting circuit 52 and the conversion circuit 53. That is, IC1 has four terminals T21
It is possible to input the six kinds of signals shown in the above items (A) to (F) to the IC 1 only by providing .about.T24.

Therefore, since the number of terminals is reduced, I
The C1 package can be downsized, the mounting area can be reduced, and it is effective for downsizing the target device. Further, also in the microcomputer which controls the IC 1, the number of output ports can be reduced, which is also effective in this respect.

Further, the setting circuit 52 and the conversion circuit 53.
When data DATA is supplied to one circuit, it is possible to reduce mixing of the data DATA as low-frequency noise or clock TCK and its harmonics as high-frequency noise into the other circuit. it can.

The signal ENBL supplied to the conversion circuit 53 is also used.
Is ENBL = (MDPL * ENBL) + (MDPL * ENBL) *: Exclusive OR +: OR *: AND, so even if the logic state (state) when the conversion circuit 53 is not accessed is different, No problems will occur.

That is, when switching is performed by the AND signal between the signal MDPL and the signal ENBL, the conversion circuit 53 is enabled at the moment of switching to the conversion circuit 53,
In this switching circuit 53, since the switching circuit 53 is switched to the conversion circuit 53 in accordance with the above equation, when the conversion circuit 53 is not selected, the OR circuit 76 to the conversion circuit 53. The signal ENBL supplied to is fixed to "1" and the conversion circuit 53 does not become unstable.

[PLL Lock Detection and Command Signal Frame Detection] The output circuit of the lock detection signal indicating whether the PLL 31 is locked and the frame detection signal of the command signal CMND is configured in the IC 1 as shown in FIG. 6, for example. To be done.

That is, when the command signal CMND is transmitted from the master unit, the MSK signal modulated by the command signal CMND is output from the demodulation circuit 17 of the receiving circuit 10. This MSK signal is a bandpass filter. The original command signal CMND supplied to the demodulation circuit 82 via 81 is demodulated, and this signal CMND is taken out to the terminal T25.

Further, at this time, the command signal CMND from the demodulation circuit 82 is supplied to the clock recovery circuit 83 constituted by a PLL, for example, and the clock RCK bit-synchronized with the command signal CMND is taken out, and this clock RCK is a terminal. It is output to T26.

Further, the command signal from the demodulation circuit 82
CMND is supplied to the frame detection circuit 84, and a command signal
For example, a frame detection signal FRMD which is “1” during the period of the frame synchronization signal FSYN of CMND and which is “0” during the other period is taken out, and this detection signal FRMD is supplied to the AND circuit 91. The AND circuit 91 is composed of the circuits 92 to 94.
Together with this, the switching circuit 90 is configured.

On the other hand, the detection circuit 85 for detecting whether or not the PLL 31 is locked is connected to the PLL 31. In this case, the phase comparison circuit 313 is provided in the PLL 31, and the signal frequency-divided by the variable frequency division circuit 312 to the frequency of 1 / N 31 and the reference signal (frequency division signal) S 35 from the frequency division circuit 35 are provided. Since the phases are compared with each other, the detection circuit 85 determines the PLL from the DC level of the output signal of the phase comparison circuit 313.
It is possible to detect whether 31 has locked.

From the detection circuit 85, the PLL
When 31 locks (when it becomes steady state),
The detection signal LKD which becomes “1” and becomes “0” when not locked is taken out, and this detection signal LKD is output from the AND circuit 92.
Is supplied to.

Then, the control signal MDPL from the terminal T21 is
The inverter 93 is supplied with the AND circuit 92.
Is supplied to the AND circuit 91 through the AND circuit 91,
The output of 92 is taken out to the terminal T27 through the OR circuit 84.

Therefore, as shown on the left side of FIG.
When PL = “1”, the lock detection signal LKD of the PLL 31 is output to the terminal T27 through the AND circuit 92 and the OR circuit 94. Further, as shown on the right side of FIG. 8, when MDPL = “0”, the frame detection signal FRMD of the command signal CMND is output to the terminal T27 through the AND circuit 91 and the OR circuit 94.

Therefore, by switching the control signal MDPL, the lock detection signal LKD of the PLL 31 and the frame detection signal FRMD of the command signal CMND can be selectively taken out to the terminal T27. That is, only by providing the terminal T27 in the IC1, the lock detection signal LKD of the PLL31
And the frame detection signal FRMD of the command signal CMND can be extracted.

Specifically, MDPL = “1” is set by the microcomputer, and P is set by the signals DATA, TCK, ENBL.
The frequency dividing ratios N31 and N43 of the variable frequency dividing circuits 312 and 432 of the LLs 31 and 43 are set, and the PLL 31 locks when the lock detection signal LKD of the PLL 31 becomes "1". Therefore, MDPL =
It is sufficient to wait until the frame detection signal FRMD is obtained at the terminal T27 as "0".

Therefore, since the number of terminals is reduced, I
The C1 package can be downsized, the mounting area can be reduced, and it is effective for downsizing the target device. Further, also in the microcomputer which processes the signal from the IC 1, the number of input ports can be reduced, which is also effective in this respect.

Further, when the detection signal of one circuit of the detection circuit 84 and the detection circuit 85 is taken out to the terminal T27, the detection signal of the other circuit is blocked by the AND circuit 91 or 92. Mutual detection circuit 8
It is possible to reduce the occurrence of noise interference due to the communication of No. 4, 85.

[Others] In the above description, the present invention is applied to a cordless telephone, but the present invention can be applied to any transmitter / receiver of a PLL synthesizer system while transmitting / receiving digital data.
Similarly, it is also possible to detect the lock of the transmission PLL 43 and take out the lock detection signal to the terminal T27 instead of the lock detection signal LKD of the PLL 31.

[0100]

According to the present invention, the number of terminals can be reduced, the IC package can be downsized, the mounting area can be reduced, and the target device can be downsized. In addition, the number of ports can be reduced in a microcomputer that processes IC signals, which is also effective in this respect. Furthermore, the influence of noise can be reduced.

[Brief description of drawings]

FIG. 1 is a system diagram showing a part of an example of the present invention.

FIG. 2 is a system diagram showing an example of a continuation of FIG.

FIG. 3 is a frequency spectrum diagram for explaining the circuits of FIGS. 1 and 2.

FIG. 4 is a system diagram showing one form of a part of the circuit of FIG.

5 is a system diagram showing one form of a part of the circuit of FIG. 1. FIG.

FIG. 6 is a system diagram showing one form of a part of the circuit of FIG.

FIG. 7 is a waveform diagram for explaining the operation of the circuits of FIGS. 4 and 5.

8 is a waveform diagram for explaining the operation of the circuit of FIG.

FIG. 9 is a diagram for explaining the present invention.

FIG. 10 is a diagram for explaining the present invention.

[Explanation of symbols]

 1 IC 4 Speaker 5 Microphone 10 Reception Circuit 12, 22 1st Mixer Circuit 14, 24 2nd Mixer Circuit 17 Demodulation Circuit 30 Oscillation Circuit 31, 43 PLL 40 Transmission Circuit 51, 90 Switching Circuit 52 Dividing Ratio Setting Circuit 53 Conversion Circuit 54 D / A converter 82 Demodulation circuit 83 Clock reproduction circuit 84 Frame detection circuit 85 Lock detection circuit 311, 431 VCO 312, 432 Variable frequency divider circuit 313 Phase comparison circuit

Claims (3)

[Claims] 1. An integrated circuit in which a PLL and a demodulation circuit that demodulates received data are integrated together, and a lock detection circuit that detects that the PLL is locked, and a frame signal of the received data. A frame detection circuit for detecting, a lock detection signal of the lock detection circuit, and a switching circuit to which the frame detection signal of the frame detection circuit is supplied, and control the switching circuit by an external control signal. An integrated circuit adapted to selectively take out the lock detection signal and the frame detection signal to the outside. 2. The integrated circuit according to claim 1, further comprising: another switching circuit supplied with data from the outside, and a conversion circuit converting the supplied data into a signal for transmission. The other switching circuit is also controlled by a control signal from the outside to transfer the data from the outside to the conversion circuit and the PLL.
And an integrated circuit adapted to be selectively supplied to the variable frequency dividing circuit. 3. P for determining a transmission frequency and a reception frequency.
LL, a lock detection circuit that detects that the PLL is locked, a frame detection circuit that detects a frame signal of received data, a lock detection signal of the lock detection circuit, and a frame detection signal of the frame detection circuit. And a switching circuit to which the lock detection signal and the frame detection signal are selectively taken out by controlling the switching circuit by a control signal from the outside. Machine.